arch/arm/include/asm/arch-mx6/crm_regs.h

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
   8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
   9
  10 #define CCM_CCOSR               0x020c4060
  11 #define CCM_CCGR0               0x020C4068
  12 #define CCM_CCGR1               0x020C406c
  13 #define CCM_CCGR2               0x020C4070
  14 #define CCM_CCGR3               0x020C4074
  15 #define CCM_CCGR4               0x020C4078
  16 #define CCM_CCGR5               0x020C407c
  17 #define CCM_CCGR6               0x020C4080
  18
  19 #define PMU_MISC2               0x020C8170
  20
  21 #ifndef __ASSEMBLY__
  22 struct mxc_ccm_reg {
  23         u32 ccr;        /* 0x0000 */
  24         u32 ccdr;
  25         u32 csr;
  26         u32 ccsr;
  27         u32 cacrr;      /* 0x0010*/
  28         u32 cbcdr;
  29         u32 cbcmr;
  30         u32 cscmr1;
  31         u32 cscmr2;     /* 0x0020 */
  32         u32 cscdr1;
  33         u32 cs1cdr;
  34         u32 cs2cdr;
  35         u32 cdcdr;      /* 0x0030 */
  36         u32 chsccdr;
  37         u32 cscdr2;
  38         u32 cscdr3;
  39         u32 cscdr4;     /* 0x0040 */
  40         u32 resv0;
  41         u32 cdhipr;
  42         u32 cdcr;
  43         u32 ctor;       /* 0x0050 */
  44         u32 clpcr;
  45         u32 cisr;
  46         u32 cimr;
  47         u32 ccosr;      /* 0x0060 */
  48         u32 cgpr;
  49         u32 CCGR0;
  50         u32 CCGR1;
  51         u32 CCGR2;      /* 0x0070 */
  52         u32 CCGR3;
  53         u32 CCGR4;
  54         u32 CCGR5;
  55         u32 CCGR6;      /* 0x0080 */
  56         u32 CCGR7;
  57         u32 cmeor;
  58 };
  59 #endif
  60
  61 /* Define the bits in register CCR */
  62 #define MXC_CCM_CCR_RBC_EN                              (1 << 27)
  63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK                 (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
  64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET               21
  65 #define MXC_CCM_CCR_WB_COUNT_MASK                       (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
  66 #define MXC_CCM_CCR_WB_COUNT_OFFSET                     (1 << 16)
  67 #define MXC_CCM_CCR_COSC_EN                             (1 << 12)
  68 #ifdef CONFIG_SOC_MX6SX
  69 #define MXC_CCM_CCR_OSCNT_MASK                          0x7F
  70 #else
  71 #define MXC_CCM_CCR_OSCNT_MASK                          0xFF
  72 #endif
  73 #define MXC_CCM_CCR_OSCNT_OFFSET                        0
  74
  75 /* Define the bits in register CCDR */
  76 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK                   (1 << 16)
  77 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK                   (1 << 17)
  78
  79 /* Define the bits in register CSR */
  80 #define MXC_CCM_CSR_COSC_READY                          (1 << 5)
  81 #define MXC_CCM_CSR_REF_EN_B                            (1 << 0)
  82
  83 /* Define the bits in register CCSR */
  84 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS                  (1 << 15)
  85 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS                  (1 << 14)
  86 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS                  (1 << 13)
  87 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS                  (1 << 12)
  88 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS                  (1 << 11)
  89 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS                  (1 << 10)
  90 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS                  (1 << 9)
  91 #define MXC_CCM_CCSR_STEP_SEL                           (1 << 8)
  92 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL                    (1 << 2)
  93 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL                    (1 << 1)
  94 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL                    (1 << 0)
  95
  96 /* Define the bits in register CACRR */
  97 #define MXC_CCM_CACRR_ARM_PODF_OFFSET                   0
  98 #define MXC_CCM_CACRR_ARM_PODF_MASK                     (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
  99
 100 /* Define the bits in register CBCDR */
 101 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK             (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
 102 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET           27
 103 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                  (1 << 26)
 104 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                    (1 << 25)
 105 #ifndef CONFIG_SOC_MX6SX
 106 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK                (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
 107 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET              19
 108 #endif
 109 #define MXC_CCM_CBCDR_AXI_PODF_MASK                     (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
 110 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET                   16
 111 #define MXC_CCM_CBCDR_AHB_PODF_MASK                     (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
 112 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET                   10
 113 #define MXC_CCM_CBCDR_IPG_PODF_MASK                     (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
 114 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET                   8
 115 #define MXC_CCM_CBCDR_AXI_ALT_SEL                       (1 << 7)
 116 #define MXC_CCM_CBCDR_AXI_SEL                           (1 << 6)
 117 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK                (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
 118 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET              3
 119 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK            (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
 120 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET          0
 121
 122 /* Define the bits in register CBCMR */
 123 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK            (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
 124 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET          29
 125 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK              (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
 126 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET            26
 127 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK              (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
 128 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET            23
 129 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
 130 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET        21
 131 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL              (1 << 20)
 132 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK           (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
 133 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET         18
 134 #ifndef CONFIG_SOC_MX6SX
 135 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK                (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
 136 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET              16
 137 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK              (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
 138 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET            14
 139 #endif
 140 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK              (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
 141 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET            12
 142 #ifndef CONFIG_SOC_MX6SX
 143 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                    (1 << 11)
 144 #endif
 145 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                  (1 << 10)
 146 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK         (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
 147 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET       8
 148 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK           (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
 149 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET         4
 150 #ifndef CONFIG_SOC_MX6SX
 151 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                 (1 << 1)
 152 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                 (1 << 0)
 153 #endif
 154
 155 /* Define the bits in register CSCMR1 */
 156 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK               (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
 157 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET             29
 158 #ifdef CONFIG_SOC_MX6SX
 159 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                  (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
 160 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET                26
 161 #else
 162 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK                    (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
 163 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET                  27
 164 #endif
 165 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK          (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
 166 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET        23
 167 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
 168 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK               (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
 169 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET             20
 170 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL                   (1 << 19)
 171 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL                   (1 << 18)
 172 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL                   (1 << 17)
 173 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL                   (1 << 16)
 174 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK                (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
 175 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET              14
 176 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK                (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
 177 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              12
 178 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
 179 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              10
 180 #ifdef CONFIG_SOC_MX6SX
 181 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK               (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 182 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET             7
 183 #endif
 184 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 185 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                 (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
 186 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET               6
 187 #endif
 188 #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET               0
 189 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                 (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
 190
 191 /* Define the bits in register CSCMR2 */
 192 #ifdef CONFIG_SOC_MX6SX
 193 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                 (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
 194 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET               21
 195 #endif
 196 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK                (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
 197 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET              19
 198 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                  (1 << 11)
 199 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                  (1 << 10)
 200 #ifdef CONFIG_SOC_MX6SX
 201 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                 (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 202 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET               8
 203 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK                (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
 204 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET              2
 205 #else
 206 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                 (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 207 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET               2
 208 #endif
 209
 210 /* Define the bits in register CSCDR1 */
 211 #ifndef CONFIG_SOC_MX6SX
 212 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK                (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
 213 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET              25
 214 #endif
 215 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
 216 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET               22
 217 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
 218 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET               19
 219 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
 220 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET               16
 221 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                 (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
 222 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET               11
 223 #ifndef CONFIG_SOC_MX6SX
 224 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET           8
 225 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK             (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
 226 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET           6
 227 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK             (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 228 #endif
 229 #ifdef CONFIG_SOC_MX6SL
 230 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 231 #define MXC_CCM_CSCDR1_UART_CLK_SEL                     (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 232 #else
 233 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 234 #ifdef CONFIG_SOC_MX6SX
 235 #define MXC_CCM_CSCDR1_UART_CLK_SEL                     (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 236 #endif
 237 #endif
 238 #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET              6
 239 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET             0
 240
 241 /* Define the bits in register CS1CDR */
 242 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK               (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
 243 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET             25
 244 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK               (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
 245 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET             22
 246 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK               (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
 247 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET             16
 248 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK               (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
 249 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET             9
 250 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK               (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
 251 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET             6
 252 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK               (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
 253 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET             0
 254
 255 /* Define the bits in register CS2CDR */
 256 #ifdef CONFIG_SOC_MX6SX
 257 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK              (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 258 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET            21
 259 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 260 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK              (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
 261 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET            18
 262 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
 263 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK               (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
 264 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET             15
 265 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                 (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
 266 #else
 267 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK               (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
 268 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET             21
 269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)                 (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
 270 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK               (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
 271 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET             18
 272 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)                 (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
 273 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK                (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
 274 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET              16
 275 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)                  (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
 276 #endif
 277 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK             (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
 278 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET           12
 279 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK             (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 280 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET           9
 281 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK               (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
 282 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET             6
 283 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK               (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
 284 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET             0
 285
 286 /* Define the bits in register CDCDR */
 287 #ifndef CONFIG_SOC_MX6SX
 288 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                  (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
 289 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET                29
 290 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK               (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
 291 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET             28
 292 #endif
 293 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
 294 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET            25
 295 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
 296 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET            22
 297 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK               (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
 298 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET             20
 299 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
 300 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET            12
 301 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK              (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
 302 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET            9
 303 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK               (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
 304 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET             7
 305
 306 /* Define the bits in register CHSCCDR */
 307 #ifdef CONFIG_SOC_MX6SX
 308 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
 309 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET         15
 310 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                  (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
 311 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET                12
 312 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK               (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
 313 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET             9
 314 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK             (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
 315 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET           6
 316 #define MXC_CCM_CHSCCDR_M4_PODF_MASK                    (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
 317 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET                  3
 318 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK                 (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
 319 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET               0
 320 #else
 321 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
 322 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET     15
 323 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK              (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
 324 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET            12
 325 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
 326 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET         9
 327 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK       (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
 328 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET     6
 329 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK              (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 330 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET            3
 331 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK           (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 332 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET         0
 333 #endif
 334
 335 #define CHSCCDR_CLK_SEL_LDB_DI0                         3
 336 #define CHSCCDR_PODF_DIVIDE_BY_3                        2
 337 #define CHSCCDR_IPU_PRE_CLK_540M_PFD                    5
 338
 339 /* Define the bits in register CSCDR2 */
 340 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
 341 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET            19
 342 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 343 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK        (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
 344 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET      15
 345 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK               (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
 346 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET             12
 347 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK            (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
 348 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET          9
 349 /* All IPU2_DI0 are LCDIF2 on MX6SX */
 350 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK        (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
 351 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET      6
 352 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK               (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
 353 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET             3
 354 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK            (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
 355 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET          0
 356
 357 /* Define the bits in register CSCDR3 */
 358 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK               (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
 359 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET             16
 360 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK            (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
 361 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET          14
 362 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK               (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
 363 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET             11
 364 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK            (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
 365 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET          9
 366
 367 /* Define the bits in register CDHIPR */
 368 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY                    (1 << 16)
 369 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY              (1 << 5)
 370 #ifndef CONFIG_SOC_MX6SX
 371 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY               (1 << 4)
 372 #endif
 373 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY             (1 << 3)
 374 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY               (1 << 2)
 375 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY                    (1 << 1)
 376 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY                    (1 << 0)
 377
 378 /* Define the bits in register CLPCR */
 379 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE                    (1 << 27)
 380 #define MXC_CCM_CLPCR_MASK_SCU_IDLE                     (1 << 26)
 381 #ifndef CONFIG_SOC_MX6SX
 382 #define MXC_CCM_CLPCR_MASK_CORE3_WFI                    (1 << 25)
 383 #define MXC_CCM_CLPCR_MASK_CORE2_WFI                    (1 << 24)
 384 #define MXC_CCM_CLPCR_MASK_CORE1_WFI                    (1 << 23)
 385 #endif
 386 #define MXC_CCM_CLPCR_MASK_CORE0_WFI                    (1 << 22)
 387 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS               (1 << 21)
 388 #ifndef CONFIG_SOC_MX6SX
 389 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS               (1 << 19)
 390 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                    (1 << 17)
 391 #endif
 392 #define MXC_CCM_CLPCR_WB_PER_AT_LPM                     (1 << 16)
 393 #define MXC_CCM_CLPCR_COSC_PWRDOWN                      (1 << 11)
 394 #define MXC_CCM_CLPCR_STBY_COUNT_MASK                   (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
 395 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                 9
 396 #define MXC_CCM_CLPCR_VSTBY                             (1 << 8)
 397 #define MXC_CCM_CLPCR_DIS_REF_OSC                       (1 << 7)
 398 #define MXC_CCM_CLPCR_SBYOS                             (1 << 6)
 399 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM                (1 << 5)
 400 #ifndef CONFIG_SOC_MX6SX
 401 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                 (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
 402 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET               3
 403 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY           (1 << 2)
 404 #endif
 405 #define MXC_CCM_CLPCR_LPM_MASK                          (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
 406 #define MXC_CCM_CLPCR_LPM_OFFSET                        0
 407
 408 /* Define the bits in register CISR */
 409 #define MXC_CCM_CISR_ARM_PODF_LOADED                    (1 << 26)
 410 #ifndef CONFIG_SOC_MX6SX
 411 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED               (1 << 23)
 412 #endif
 413 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED              (1 << 22)
 414 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED               (1 << 21)
 415 #define MXC_CCM_CISR_AHB_PODF_LOADED                    (1 << 20)
 416 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED             (1 << 19)
 417 #define MXC_CCM_CISR_AXI_PODF_LOADED                    (1 << 17)
 418 #define MXC_CCM_CISR_COSC_READY                         (1 << 6)
 419 #define MXC_CCM_CISR_LRF_PLL                            (1 << 0)
 420
 421 /* Define the bits in register CIMR */
 422 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED               (1 << 26)
 423 #ifndef CONFIG_SOC_MX6SX
 424 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED          (1 << 23)
 425 #endif
 426 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED         (1 << 22)
 427 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED          (1 << 21)
 428 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED               (1 << 20)
 429 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED        (1 << 19)
 430 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED               (1 << 17)
 431 #define MXC_CCM_CIMR_MASK_COSC_READY                    (1 << 6)
 432 #define MXC_CCM_CIMR_MASK_LRF_PLL                       (1 << 0)
 433
 434 /* Define the bits in register CCOSR */
 435 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET                    (1 << 24)
 436 #define MXC_CCM_CCOSR_CKO2_DIV_MASK                     (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
 437 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                   21
 438 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                   16
 439 #define MXC_CCM_CCOSR_CKO2_SEL_MASK                     (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
 440 #define MXC_CCM_CCOSR_CLK_OUT_SEL                       (0x1 << 8)
 441 #define MXC_CCM_CCOSR_CKOL_EN                           (0x1 << 7)
 442 #define MXC_CCM_CCOSR_CKOL_DIV_MASK                     (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
 443 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                   4
 444 #define MXC_CCM_CCOSR_CKOL_SEL_MASK                     (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
 445 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                   0
 446
 447 /* Define the bits in registers CGPR */
 448 #define MXC_CCM_CGPR_FAST_PLL_EN                        (1 << 16)
 449 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE             (1 << 4)
 450 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS                   (1 << 2)
 451 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER                  (1 << 0)
 452
 453 /* Define the bits in registers CCGRx */
 454 #define MXC_CCM_CCGR_CG_MASK                            3
 455
 456 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                   0
 457 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
 458 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                   2
 459 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
 460 #define MXC_CCM_CCGR0_APBHDMA_OFFSET                    4
 461 #define MXC_CCM_CCGR0_APBHDMA_MASK                      (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
 462 #define MXC_CCM_CCGR0_ASRC_OFFSET                       6
 463 #define MXC_CCM_CCGR0_ASRC_MASK                         (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
 464 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET            8
 465 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK              (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
 466 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET          10
 467 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK            (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
 468 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET           12
 469 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK             (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
 470 #define MXC_CCM_CCGR0_CAN1_OFFSET                       14
 471 #define MXC_CCM_CCGR0_CAN1_MASK                         (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
 472 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET                16
 473 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK                  (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
 474 #define MXC_CCM_CCGR0_CAN2_OFFSET                       18
 475 #define MXC_CCM_CCGR0_CAN2_MASK                         (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
 476 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET                20
 477 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK                  (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
 478 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET            22
 479 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK              (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
 480 #define MXC_CCM_CCGR0_DCIC1_OFFSET                      24
 481 #define MXC_CCM_CCGR0_DCIC1_MASK                        (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 482 #define MXC_CCM_CCGR0_DCIC2_OFFSET                      26
 483 #define MXC_CCM_CCGR0_DCIC2_MASK                        (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
 484 #ifdef CONFIG_SOC_MX6SX
 485 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET                   30
 486 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK                     (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
 487 #else
 488 #define MXC_CCM_CCGR0_DTCP_OFFSET                       28
 489 #define MXC_CCM_CCGR0_DTCP_MASK                         (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
 490 #endif
 491
 492 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET                    0
 493 #define MXC_CCM_CCGR1_ECSPI1S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
 494 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET                    2
 495 #define MXC_CCM_CCGR1_ECSPI2S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
 496 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET                    4
 497 #define MXC_CCM_CCGR1_ECSPI3S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
 498 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET                    6
 499 #define MXC_CCM_CCGR1_ECSPI4S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 500 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                    8
 501 #define MXC_CCM_CCGR1_ECSPI5S_MASK                      (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
 502 #ifndef CONFIG_SOC_MX6SX
 503 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET            10
 504 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK              (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
 505 #endif
 506 #define MXC_CCM_CCGR1_EPIT1S_OFFSET                     12
 507 #define MXC_CCM_CCGR1_EPIT1S_MASK                       (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
 508 #define MXC_CCM_CCGR1_EPIT2S_OFFSET                     14
 509 #define MXC_CCM_CCGR1_EPIT2S_MASK                       (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 510 #define MXC_CCM_CCGR1_ESAIS_OFFSET                      16
 511 #define MXC_CCM_CCGR1_ESAIS_MASK                        (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
 512 #ifdef CONFIG_SOC_MX6SX
 513 #define MXC_CCM_CCGR1_WAKEUP_OFFSET                     18
 514 #define MXC_CCM_CCGR1_WAKEUP_MASK                       (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
 515 #endif
 516 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET                    20
 517 #define MXC_CCM_CCGR1_GPT_BUS_MASK                      (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 518 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                 22
 519 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK                   (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
 520 #ifndef CONFIG_SOC_MX6SX
 521 #define MXC_CCM_CCGR1_GPU2D_OFFSET                      24
 522 #define MXC_CCM_CCGR1_GPU2D_MASK                        (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 523 #endif
 524 #define MXC_CCM_CCGR1_GPU3D_OFFSET                      26
 525 #define MXC_CCM_CCGR1_GPU3D_MASK                        (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
 526 #ifdef CONFIG_SOC_MX6SX
 527 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET                    28
 528 #define MXC_CCM_CCGR1_OCRAM_S_MASK                      (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
 529 #define MXC_CCM_CCGR1_CANFD_OFFSET                      30
 530 #define MXC_CCM_CCGR1_CANFD_MASK                        (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
 531 #endif
 532
 533 #ifndef CONFIG_SOC_MX6SX
 534 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET            0
 535 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK              (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 536 #else
 537 #define MXC_CCM_CCGR2_CSI_OFFSET                        2
 538 #define MXC_CCM_CCGR2_CSI_MASK                          (3 << MXC_CCM_CCGR2_CSI_OFFSET)
 539 #endif
 540 #ifndef CONFIG_SOC_MX6SX
 541 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET            4
 542 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK              (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 543 #endif
 544 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET                6
 545 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
 546 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET                8
 547 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 548 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET                10
 549 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                  (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
 550 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET                8
 551 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 552 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                 12
 553 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                   (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 554 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET           14
 555 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK             (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
 556 #define MXC_CCM_CCGR2_IPMUX1_OFFSET                     16
 557 #define MXC_CCM_CCGR2_IPMUX1_MASK                       (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
 558 #define MXC_CCM_CCGR2_IPMUX2_OFFSET                     18
 559 #define MXC_CCM_CCGR2_IPMUX2_MASK                       (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
 560 #define MXC_CCM_CCGR2_IPMUX3_OFFSET                     20
 561 #define MXC_CCM_CCGR2_IPMUX3_MASK                       (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 562 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET  22
 563 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK    (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
 564 #ifdef CONFIG_SOC_MX6SX
 565 #define MXC_CCM_CCGR2_LCD_OFFSET                        28
 566 #define MXC_CCM_CCGR2_LCD_MASK                          (3 << MXC_CCM_CCGR2_LCD_OFFSET)
 567 #define MXC_CCM_CCGR2_PXP_OFFSET                        30
 568 #define MXC_CCM_CCGR2_PXP_MASK                          (3 << MXC_CCM_CCGR2_PXP_OFFSET)
 569 #else
 570 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET   24
 571 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK     (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
 572 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
 573 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 574 #endif
 575
 576 #ifdef CONFIG_SOC_MX6SX
 577 #define MXC_CCM_CCGR3_M4_OFFSET                                 2
 578 #define MXC_CCM_CCGR3_M4_MASK                                   (3 << MXC_CCM_CCGR3_M4_OFFSET)
 579 #define MXC_CCM_CCGR3_ENET_OFFSET                               4
 580 #define MXC_CCM_CCGR3_ENET_MASK                                 (3 << MXC_CCM_CCGR3_ENET_OFFSET)
 581 #define MXC_CCM_CCGR3_QSPI_OFFSET                               14
 582 #define MXC_CCM_CCGR3_QSPI_MASK                                 (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
 583 #else
 584 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET                           0
 585 #define MXC_CCM_CCGR3_IPU1_IPU_MASK                             (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 586 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET                       2
 587 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                         (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
 588 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET                       4
 589 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                         (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
 590 #endif
 591 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET                           6
 592 #define MXC_CCM_CCGR3_IPU2_IPU_MASK                             (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
 593 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET                       8
 594 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK                         (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
 595 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET                       10
 596 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                         (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 597 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                            12
 598 #define MXC_CCM_CCGR3_LDB_DI0_MASK                              (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
 599 #ifdef CONFIG_SOC_MX6SX
 600 #define MXC_CCM_CCGR3_QSPI1_OFFSET                              14
 601 #define MXC_CCM_CCGR3_QSPI1_MASK                                (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
 602 #else
 603 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET                            14
 604 #define MXC_CCM_CCGR3_LDB_DI1_MASK                              (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
 605 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET                      16
 606 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                        (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
 607 #endif
 608 #define MXC_CCM_CCGR3_MLB_OFFSET                                18
 609 #define MXC_CCM_CCGR3_MLB_MASK                                  (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 610 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET        20
 611 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK          (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
 612 #ifndef CONFIG_SOC_MX6SX
 613 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET        22
 614 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK          (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 615 #endif
 616 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET               24
 617 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                 (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
 618 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET               26
 619 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                 (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 620 #define MXC_CCM_CCGR3_OCRAM_OFFSET                              28
 621 #define MXC_CCM_CCGR3_OCRAM_MASK                                (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
 622 #ifndef CONFIG_SOC_MX6SX
 623 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                       30
 624 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                         (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 625 #endif
 626
 627 #define MXC_CCM_CCGR4_PCIE_OFFSET                               0
 628 #define MXC_CCM_CCGR4_PCIE_MASK                                 (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
 629 #ifdef CONFIG_SOC_MX6SX
 630 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                         10
 631 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                           (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
 632 #else
 633 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET               8
 634 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                 (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
 635 #endif
 636 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET                 12
 637 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                   (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
 638 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET      14
 639 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK        (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
 640 #define MXC_CCM_CCGR4_PWM1_OFFSET                               16
 641 #define MXC_CCM_CCGR4_PWM1_MASK                                 (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
 642 #define MXC_CCM_CCGR4_PWM2_OFFSET                               18
 643 #define MXC_CCM_CCGR4_PWM2_MASK                                 (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
 644 #define MXC_CCM_CCGR4_PWM3_OFFSET                               20
 645 #define MXC_CCM_CCGR4_PWM3_MASK                                 (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
 646 #define MXC_CCM_CCGR4_PWM4_OFFSET                               22
 647 #define MXC_CCM_CCGR4_PWM4_MASK                                 (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
 648 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET            24
 649 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK              (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
 650 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET       26
 651 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK         (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
 652 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET   28
 653 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK     (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
 654 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET           30
 655 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK             (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
 656
 657 #define MXC_CCM_CCGR5_ROM_OFFSET                                0
 658 #define MXC_CCM_CCGR5_ROM_MASK                                  (3 << MXC_CCM_CCGR5_ROM_OFFSET)
 659 #ifndef CONFIG_SOC_MX6SX
 660 #define MXC_CCM_CCGR5_SATA_OFFSET                               4
 661 #define MXC_CCM_CCGR5_SATA_MASK                                 (3 << MXC_CCM_CCGR5_SATA_OFFSET)
 662 #endif
 663 #define MXC_CCM_CCGR5_SDMA_OFFSET                               6
 664 #define MXC_CCM_CCGR5_SDMA_MASK                                 (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
 665 #define MXC_CCM_CCGR5_SPBA_OFFSET                               12
 666 #define MXC_CCM_CCGR5_SPBA_MASK                                 (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
 667 #define MXC_CCM_CCGR5_SPDIF_OFFSET                              14
 668 #define MXC_CCM_CCGR5_SPDIF_MASK                                (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
 669 #define MXC_CCM_CCGR5_SSI1_OFFSET                               18
 670 #define MXC_CCM_CCGR5_SSI1_MASK                                 (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
 671 #define MXC_CCM_CCGR5_SSI2_OFFSET                               20
 672 #define MXC_CCM_CCGR5_SSI2_MASK                                 (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
 673 #define MXC_CCM_CCGR5_SSI3_OFFSET                               22
 674 #define MXC_CCM_CCGR5_SSI3_MASK                                 (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
 675 #define MXC_CCM_CCGR5_UART_OFFSET                               24
 676 #define MXC_CCM_CCGR5_UART_MASK                                 (3 << MXC_CCM_CCGR5_UART_OFFSET)
 677 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET                        26
 678 #define MXC_CCM_CCGR5_UART_SERIAL_MASK                          (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 679 #ifdef CONFIG_SOC_MX6SX
 680 #define MXC_CCM_CCGR5_SAI1_OFFSET                               20
 681 #define MXC_CCM_CCGR5_SAI1_MASK                                 (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 682 #define MXC_CCM_CCGR5_SAI2_OFFSET                               30
 683 #define MXC_CCM_CCGR5_SAI2_MASK                                 (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
 684 #endif
 685
 686 #define MXC_CCM_CCGR6_USBOH3_OFFSET                             0
 687 #define MXC_CCM_CCGR6_USBOH3_MASK                               (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 688 #define MXC_CCM_CCGR6_USDHC1_OFFSET                             2
 689 #define MXC_CCM_CCGR6_USDHC1_MASK                               (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
 690 #define MXC_CCM_CCGR6_USDHC2_OFFSET                             4
 691 #define MXC_CCM_CCGR6_USDHC2_MASK                               (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
 692 #define MXC_CCM_CCGR6_USDHC3_OFFSET                             6
 693 #define MXC_CCM_CCGR6_USDHC3_MASK                               (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
 694 #define MXC_CCM_CCGR6_USDHC4_OFFSET                             8
 695 #define MXC_CCM_CCGR6_USDHC4_MASK                               (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 696 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                           10
 697 #define MXC_CCM_CCGR6_EMI_SLOW_MASK                             (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
 698 /* The following *CCGR6* exist only on i.MX6SX */
 699 #define MXC_CCM_CCGR6_PWM8_OFFSET                               16
 700 #define MXC_CCM_CCGR6_PWM8_MASK                                 (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 701 #define MXC_CCM_CCGR6_VADC_OFFSET                               20
 702 #define MXC_CCM_CCGR6_VADC_MASK                                 (3 << MXC_CCM_CCGR6_VADC_OFFSET)
 703 #define MXC_CCM_CCGR6_GIS_OFFSET                                22
 704 #define MXC_CCM_CCGR6_GIS_MASK                                  (3 << MXC_CCM_CCGR6_GIS_OFFSET)
 705 #define MXC_CCM_CCGR6_I2C4_OFFSET                               24
 706 #define MXC_CCM_CCGR6_I2C4_MASK                                 (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
 707 #define MXC_CCM_CCGR6_PWM5_OFFSET                               26
 708 #define MXC_CCM_CCGR6_PWM5_MASK                                 (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
 709 #define MXC_CCM_CCGR6_PWM6_OFFSET                               28
 710 #define MXC_CCM_CCGR6_PWM6_MASK                                 (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
 711 #define MXC_CCM_CCGR6_PWM7_OFFSET                               30
 712 #define MXC_CCM_CCGR6_PWM7_MASK                                 (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
 713 /* These two do not exist on i.MX6SX */
 714 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET                          12
 715 #define MXC_CCM_CCGR6_VDOAXICLK_MASK                            (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
 716
 717 #define BM_ANADIG_USB_PLL_480_CTRL_LOCK                         (1 << 31)
 718 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS                       (1 << 16)
 719 #define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC               14
 720 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC               (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
 721 #define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v)            \
 722         (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) &   \
 723                 BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
 724 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M      0x0
 725 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1     0x1
 726 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2     0x2
 727 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR          0x3
 728 #define BM_ANADIG_USB_PLL_480_CTRL_ENABLE                       (1 << 13)
 729 #define BM_ANADIG_USB_PLL_480_CTRL_POWER                        (1 << 12)
 730 #define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF                (1 << 11)
 731 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP                    (1 << 10)
 732 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP                      (1 << 9)
 733 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF                    (1 << 8)
 734 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF                      (1 << 7)
 735 #define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS                  (1 << 6)
 736 #define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0                     2
 737 #define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0                     (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
 738 #define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v)          \
 739         (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
 740                 BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
 741 #define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT                   0
 742 #define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT                   (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
 743 #define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v)           \
 744         (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
 745                 BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
 746
 747 #define BM_ANADIG_PLL_528_LOCK                                  (1 << 31)
 748 #define BM_ANADIG_PLL_528_PLL_SEL                               (1 << 19)
 749 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL                        (1 << 18)
 750 #define BM_ANADIG_PLL_528_LVDS_SEL                              (1 << 17)
 751 #define BM_ANADIG_PLL_528_BYPASS                                (1 << 16)
 752 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC                        14
 753 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC                        (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
 754 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)          \
 755         (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
 756                 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
 757 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M               0x0
 758 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1              0x1
 759 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2              0x2
 760 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR                   0x3
 761 #define BM_ANADIG_PLL_528_ENABLE                                (1 << 13)
 762 #define BM_ANADIG_PLL_528_POWERDOWN                             (1 << 12)
 763 #define BM_ANADIG_PLL_528_HOLD_RING_OFF                         (1 << 11)
 764 #define BM_ANADIG_PLL_528_DOUBLE_CP                             (1 << 10)
 765 #define BM_ANADIG_PLL_528_HALF_CP                               (1 << 9)
 766 #define BM_ANADIG_PLL_528_DOUBLE_LF                             (1 << 8)
 767 #define BM_ANADIG_PLL_528_HALF_LF                               (1 << 7)
 768 #define BP_ANADIG_PLL_528_DIV_SELECT                            0
 769 #define BM_ANADIG_PLL_528_DIV_SELECT                            (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
 770 #define BF_ANADIG_PLL_528_DIV_SELECT(v)          \
 771         (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
 772                 BM_ANADIG_PLL_528_DIV_SELECT)
 773
 774 #define BP_ANADIG_PLL_528_SS_STOP                               16
 775 #define BM_ANADIG_PLL_528_SS_STOP                               (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
 776 #define BF_ANADIG_PLL_528_SS_STOP(v)          \
 777         (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
 778                 BM_ANADIG_PLL_528_SS_STOP)
 779 #define BM_ANADIG_PLL_528_SS_ENABLE                             (1 << 15)
 780 #define BP_ANADIG_PLL_528_SS_STEP                               0
 781 #define BM_ANADIG_PLL_528_SS_STEP                               (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
 782 #define BF_ANADIG_PLL_528_SS_STEP(v)          \
 783         (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
 784                 BM_ANADIG_PLL_528_SS_STEP)
 785
 786 #define BP_ANADIG_PLL_528_NUM_A                                 0
 787 #define BM_ANADIG_PLL_528_NUM_A                                 (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
 788 #define BF_ANADIG_PLL_528_NUM_A(v)          \
 789         (((v) << BP_ANADIG_PLL_528_NUM_A) & \
 790                 BM_ANADIG_PLL_528_NUM_A)
 791
 792 #define BP_ANADIG_PLL_528_DENOM_B                               0
 793 #define BM_ANADIG_PLL_528_DENOM_B                               (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
 794 #define BF_ANADIG_PLL_528_DENOM_B(v)          \
 795         (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
 796                 BM_ANADIG_PLL_528_DENOM_B)
 797
 798 #define BM_ANADIG_PLL_AUDIO_LOCK                                (1 << 31)
 799 #define BM_ANADIG_PLL_AUDIO_SSC_EN                              (1 << 21)
 800 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT                     19
 801 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT                     (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
 802 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)          \
 803         (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
 804                 BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
 805 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN                       (1 << 18)
 806 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE                       (1 << 17)
 807 #define BM_ANADIG_PLL_AUDIO_BYPASS                              (1 << 16)
 808 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC                      14
 809 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC                      (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
 810 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)          \
 811         (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
 812                 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
 813 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M             0x0
 814 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1            0x1
 815 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2            0x2
 816 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR                 0x3
 817 #define BM_ANADIG_PLL_AUDIO_ENABLE                              (1 << 13)
 818 #define BM_ANADIG_PLL_AUDIO_POWERDOWN                           (1 << 12)
 819 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF                       (1 << 11)
 820 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP                           (1 << 10)
 821 #define BM_ANADIG_PLL_AUDIO_HALF_CP                             (1 << 9)
 822 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF                           (1 << 8)
 823 #define BM_ANADIG_PLL_AUDIO_HALF_LF                             (1 << 7)
 824 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT                          0
 825 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT                          (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
 826 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)          \
 827         (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
 828                 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
 829
 830 #define BP_ANADIG_PLL_AUDIO_NUM_A                               0
 831 #define BM_ANADIG_PLL_AUDIO_NUM_A                               (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
 832 #define BF_ANADIG_PLL_AUDIO_NUM_A(v)          \
 833         (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
 834                 BM_ANADIG_PLL_AUDIO_NUM_A)
 835
 836 #define BP_ANADIG_PLL_AUDIO_DENOM_B                             0
 837 #define BM_ANADIG_PLL_AUDIO_DENOM_B                             (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
 838 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v)          \
 839         (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
 840                 BM_ANADIG_PLL_AUDIO_DENOM_B)
 841
 842 #define BM_ANADIG_PLL_VIDEO_LOCK                                (1 << 31)
 843 #define BM_ANADIG_PLL_VIDEO_SSC_EN                              (1 << 21)
 844 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT                     19
 845 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT                     (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
 846 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)          \
 847         (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
 848                 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
 849 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN                       (1 << 18)
 850 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE                       (1 << 17)
 851 #define BM_ANADIG_PLL_VIDEO_BYPASS                              (1 << 16)
 852 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC                      14
 853 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC                      (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
 854 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)          \
 855         (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
 856                 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
 857 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M             0x0
 858 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1            0x1
 859 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2            0x2
 860 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR                 0x3
 861 #define BM_ANADIG_PLL_VIDEO_ENABLE                              (1 << 13)
 862 #define BM_ANADIG_PLL_VIDEO_POWERDOWN                           (1 << 12)
 863 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF                       (1 << 11)
 864 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP                           (1 << 10)
 865 #define BM_ANADIG_PLL_VIDEO_HALF_CP                             (1 << 9)
 866 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF                           (1 << 8)
 867 #define BM_ANADIG_PLL_VIDEO_HALF_LF                             (1 << 7)
 868 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT                          0
 869 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT                          (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
 870 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)          \
 871         (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
 872                 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
 873
 874 #define BP_ANADIG_PLL_VIDEO_NUM_A                               0
 875 #define BM_ANADIG_PLL_VIDEO_NUM_A                               (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
 876 #define BF_ANADIG_PLL_VIDEO_NUM_A(v)          \
 877         (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
 878                 BM_ANADIG_PLL_VIDEO_NUM_A)
 879
 880 #define BP_ANADIG_PLL_VIDEO_DENOM_B                             0
 881 #define BM_ANADIG_PLL_VIDEO_DENOM_B                             (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
 882 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v)          \
 883         (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
 884                 BM_ANADIG_PLL_VIDEO_DENOM_B)
 885
 886 #define BM_ANADIG_PLL_ENET_LOCK                                 (1 << 31)
 887 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE                       (1 << 21)
 888 #define BM_ANADIG_PLL_ENET_ENABLE_SATA                          (1 << 20)
 889 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE                          (1 << 19)
 890 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN                        (1 << 18)
 891 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE                        (1 << 17)
 892 #define BM_ANADIG_PLL_ENET_BYPASS                               (1 << 16)
 893 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC                       14
 894 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC                       (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
 895 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)          \
 896         (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
 897                 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
 898 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M              0x0
 899 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1             0x1
 900 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2             0x2
 901 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR                  0x3
 902 #define BM_ANADIG_PLL_ENET_ENABLE                               (1 << 13)
 903 #define BM_ANADIG_PLL_ENET_POWERDOWN                            (1 << 12)
 904 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF                        (1 << 11)
 905 #define BM_ANADIG_PLL_ENET_DOUBLE_CP                            (1 << 10)
 906 #define BM_ANADIG_PLL_ENET_HALF_CP                              (1 << 9)
 907 #define BM_ANADIG_PLL_ENET_DOUBLE_LF                            (1 << 8)
 908 #define BM_ANADIG_PLL_ENET_HALF_LF                              (1 << 7)
 909 #define BP_ANADIG_PLL_ENET_DIV_SELECT                           0
 910 #define BM_ANADIG_PLL_ENET_DIV_SELECT                           (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
 911 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)          \
 912         (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
 913                 BM_ANADIG_PLL_ENET_DIV_SELECT)
 914
 915 #define BM_ANADIG_PFD_480_PFD3_CLKGATE                          (1 << 31)
 916 #define BM_ANADIG_PFD_480_PFD3_STABLE                           (1 << 30)
 917 #define BP_ANADIG_PFD_480_PFD3_FRAC                             24
 918 #define BM_ANADIG_PFD_480_PFD3_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
 919 #define BF_ANADIG_PFD_480_PFD3_FRAC(v)          \
 920         (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
 921                 BM_ANADIG_PFD_480_PFD3_FRAC)
 922 #define BM_ANADIG_PFD_480_PFD2_CLKGATE                          (1 << 23)
 923 #define BM_ANADIG_PFD_480_PFD2_STABLE                           (1 << 22)
 924 #define BP_ANADIG_PFD_480_PFD2_FRAC                             16
 925 #define BM_ANADIG_PFD_480_PFD2_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
 926 #define BF_ANADIG_PFD_480_PFD2_FRAC(v)          \
 927         (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
 928                 BM_ANADIG_PFD_480_PFD2_FRAC)
 929 #define BM_ANADIG_PFD_480_PFD1_CLKGATE                          (1 << 15)
 930 #define BM_ANADIG_PFD_480_PFD1_STABLE                           (1 << 14)
 931 #define BP_ANADIG_PFD_480_PFD1_FRAC                             8
 932 #define BM_ANADIG_PFD_480_PFD1_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
 933 #define BF_ANADIG_PFD_480_PFD1_FRAC(v)          \
 934         (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
 935                 BM_ANADIG_PFD_480_PFD1_FRAC)
 936 #define BM_ANADIG_PFD_480_PFD0_CLKGATE                          (1 << 7)
 937 #define BM_ANADIG_PFD_480_PFD0_STABLE                           (1 << 6)
 938 #define BP_ANADIG_PFD_480_PFD0_FRAC                             0
 939 #define BM_ANADIG_PFD_480_PFD0_FRAC                             (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
 940 #define BF_ANADIG_PFD_480_PFD0_FRAC(v)          \
 941         (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
 942                 BM_ANADIG_PFD_480_PFD0_FRAC)
 943
 944 #define BM_ANADIG_PFD_528_PFD3_CLKGATE                          (1 << 31)
 945 #define BM_ANADIG_PFD_528_PFD3_STABLE                           (1 << 30)
 946 #define BP_ANADIG_PFD_528_PFD3_FRAC                             24
 947 #define BM_ANADIG_PFD_528_PFD3_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
 948 #define BF_ANADIG_PFD_528_PFD3_FRAC(v)          \
 949         (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
 950                 BM_ANADIG_PFD_528_PFD3_FRAC)
 951 #define BM_ANADIG_PFD_528_PFD2_CLKGATE                          (1 << 23)
 952 #define BM_ANADIG_PFD_528_PFD2_STABLE                           (1 << 22)
 953 #define BP_ANADIG_PFD_528_PFD2_FRAC                             16
 954 #define BM_ANADIG_PFD_528_PFD2_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
 955 #define BF_ANADIG_PFD_528_PFD2_FRAC(v)          \
 956         (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
 957                 BM_ANADIG_PFD_528_PFD2_FRAC)
 958 #define BM_ANADIG_PFD_528_PFD1_CLKGATE                          (1 << 15)
 959 #define BM_ANADIG_PFD_528_PFD1_STABLE                           (1 << 14)
 960 #define BP_ANADIG_PFD_528_PFD1_FRAC                             8
 961 #define BM_ANADIG_PFD_528_PFD1_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
 962 #define BF_ANADIG_PFD_528_PFD1_FRAC(v)          \
 963         (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
 964                 BM_ANADIG_PFD_528_PFD1_FRAC)
 965 #define BM_ANADIG_PFD_528_PFD0_CLKGATE                          (1 << 7)
 966 #define BM_ANADIG_PFD_528_PFD0_STABLE                           (1 << 6)
 967 #define BP_ANADIG_PFD_528_PFD0_FRAC                             0
 968 #define BM_ANADIG_PFD_528_PFD0_FRAC                             (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
 969 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)          \
 970         (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
 971                 BM_ANADIG_PFD_528_PFD0_FRAC)
 972
 973 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF                   (1 << 3)
 974
 975 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */