2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
65 /* CCR_WB does not exist on i.MX6SX/UL */
66 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
67 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
68 #define MXC_CCM_CCR_COSC_EN (1 << 12)
69 #ifdef CONFIG_SOC_MX6SX
70 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
72 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
74 #define MXC_CCM_CCR_OSCNT_OFFSET 0
76 /* Define the bits in register CCDR */
77 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
78 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
79 /* Exists on i.MX6QP */
80 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
82 /* Define the bits in register CSR */
83 #define MXC_CCM_CSR_COSC_READY (1 << 5)
84 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
86 /* Define the bits in register CCSR */
87 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
88 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
89 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
90 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
91 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
92 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
93 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
94 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
95 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
96 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
97 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
99 /* Define the bits in register CACRR */
100 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
101 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
103 /* Define the bits in register CBCDR */
104 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
105 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
106 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
107 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
108 /* MMDC_CH0 not exists on i.MX6SX */
109 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
110 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
111 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
113 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
115 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
116 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
117 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
118 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
119 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
120 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
121 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
122 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
124 /* Define the bits in register CBCMR */
125 #if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
126 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
127 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
128 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
129 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
130 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
131 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
133 #define MXC_CCM_CBCMR_LCDIF_PODF_MASK (0x7 << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET)
134 #define MXC_CCM_CBCMR_LCDIF_PODF_OFFSET 23
136 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
137 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
138 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
139 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
140 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
141 #ifndef CONFIG_SOC_MX6SX
142 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
143 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
144 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
145 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
147 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
148 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
149 #ifndef CONFIG_SOC_MX6SX
150 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
152 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
153 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
154 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
155 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
156 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
157 /* Exists on i.MX6QP */
158 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
160 /* Define the bits in register CSCMR1 */
161 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
162 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
163 /* QSPI1 exist on i.MX6SX/UL */
164 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
165 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
166 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
167 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
168 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
169 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
170 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
171 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
172 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
173 /* CSCMR1_GPMI/BCH exist on i.MX6UL */
174 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
175 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
176 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
177 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
178 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
179 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
180 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
181 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
182 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
183 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
184 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
185 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
186 /* QSPI1 exist on i.MX6SX/UL */
187 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
188 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
189 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
190 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
191 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
193 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
195 /* Define the bits in register CSCMR2 */
196 #ifdef CONFIG_SOC_MX6SX
197 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
198 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
200 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
201 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
202 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
203 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
204 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
205 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
206 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
208 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
209 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
211 /* Define the bits in register CSCDR1 */
212 #ifndef CONFIG_SOC_MX6SX
213 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
214 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
216 /* CSCDR1_GPMI/BCH exist on i.MX6UL */
217 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)
218 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
219 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET)
220 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
222 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
223 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
224 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
225 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
226 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
227 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
228 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
229 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
230 #ifndef CONFIG_SOC_MX6SX
231 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
232 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
233 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
234 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
236 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
237 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
238 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
239 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
241 /* Define the bits in register CS1CDR */
242 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
243 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
244 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
245 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
246 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
247 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
248 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
249 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
250 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
251 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
252 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
253 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
255 /* Define the bits in register CS2CDR */
256 /* QSPI2 on i.MX6SX */
257 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
258 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
259 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
260 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
261 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
262 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
263 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
264 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
265 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
267 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
268 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
270 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
271 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
272 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
274 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
275 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
276 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
277 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
278 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
279 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
281 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
282 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
283 is_cpu_type(MXC_CPU_MX6ULL)) ? \
284 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
285 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
286 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
287 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
288 is_cpu_type(MXC_CPU_MX6ULL)) ? \
289 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
290 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
291 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
292 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \
293 is_cpu_type(MXC_CPU_MX6ULL)) ? \
294 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
295 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
297 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
298 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
299 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
300 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
301 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
302 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
303 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
304 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
306 /* Define the bits in register CDCDR */
307 #ifndef CONFIG_SOC_MX6SX
308 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
309 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
310 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
311 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
313 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
314 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
315 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
316 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
317 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
318 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
319 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
320 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
321 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
322 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
323 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
324 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
326 /* Define the bits in register CHSCCDR */
327 #ifdef CONFIG_SOC_MX6SX
328 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
329 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
330 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
331 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
332 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
333 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
334 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
335 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
336 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
337 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
338 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
339 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
341 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
342 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
343 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
344 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
345 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
346 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
347 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
348 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
349 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
350 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
351 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
352 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
355 #define CHSCCDR_CLK_SEL_LDB_DI0 3
356 #define CHSCCDR_PODF_DIVIDE_BY_3 2
357 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
359 /* Define the bits in register CSCDR2 */
360 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
361 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
362 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
363 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
365 /* All IPU2_DI1 are LCDIF1 on MX6SX */
366 #if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
367 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
368 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
369 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
370 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
371 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
372 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
374 #define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET)
375 #define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET 15
376 #define MXC_CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET)
377 #define MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET 12
378 #define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET)
379 #define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET 9
381 /* All IPU2_DI0 are LCDIF2 on MX6SX */
382 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
383 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
384 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
385 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
386 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
387 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
389 /* Define the bits in register CSCDR3 */
390 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
391 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
392 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
393 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
394 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
395 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
396 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
397 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
399 /* Define the bits in register CDHIPR */
400 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
401 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
402 #ifndef CONFIG_SOC_MX6SX
403 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
405 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
406 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
407 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
408 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
410 /* Define the bits in register CLPCR */
411 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
412 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
413 #ifndef CONFIG_SOC_MX6SX
414 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
415 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
416 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
418 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
419 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
420 #ifndef CONFIG_SOC_MX6SX
421 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
422 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
424 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
425 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
426 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
427 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
428 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
429 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
430 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
431 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
432 #ifndef CONFIG_SOC_MX6SX
433 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
434 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
435 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
437 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
438 #define MXC_CCM_CLPCR_LPM_OFFSET 0
440 /* Define the bits in register CISR */
441 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
442 #ifndef CONFIG_SOC_MX6SX
443 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
445 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
446 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
447 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
448 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
449 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
450 #define MXC_CCM_CISR_COSC_READY (1 << 6)
451 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
453 /* Define the bits in register CIMR */
454 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
455 #ifndef CONFIG_SOC_MX6SX
456 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
458 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
459 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
460 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
461 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
462 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
463 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
464 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
466 /* Define the bits in register CCOSR */
467 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
468 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
469 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
470 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
471 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
472 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
473 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
474 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
475 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
476 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
477 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
479 /* Define the bits in registers CGPR */
480 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
481 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
482 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
483 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
485 /* Define the bits in registers CCGRx */
486 #define MXC_CCM_CCGR_CG_MASK 3
488 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
489 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
490 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
491 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
492 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
493 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
494 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
495 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
496 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
497 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
498 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
499 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
500 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
501 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
502 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
503 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
504 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
505 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
506 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
507 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
508 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
509 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
510 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
511 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
512 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
513 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
514 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
515 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
516 #ifdef CONFIG_SOC_MX6SX
517 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
518 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
520 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
521 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
524 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
525 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
526 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
527 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
528 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
529 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
530 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
531 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
532 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
533 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
534 /* CCGR1_ENET does not exist on i.MX6SX/UL */
535 #define MXC_CCM_CCGR1_ENET_OFFSET 10
536 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
537 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
538 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
539 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
540 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
541 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
542 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
543 #ifdef CONFIG_SOC_MX6SX
544 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
545 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
547 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
548 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
549 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
550 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
551 #ifndef CONFIG_SOC_MX6SX
552 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
553 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
555 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
556 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
557 #ifdef CONFIG_SOC_MX6SX
558 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
559 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
560 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
561 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
564 #if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
565 defined(CONFIG_SOC_MX6ULL)
566 #define MXC_CCM_CCGR2_CSI_OFFSET 2
567 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
569 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
570 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
572 #if !defined(CONFIG_SOC_MX6SX) && !(defined(CONFIG_SOC_MX6UL) || \
573 defined(CONFIG_SOC_MX6ULL))
574 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
575 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
577 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
578 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
579 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
580 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
581 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
582 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
583 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
584 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
585 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
586 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
587 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
588 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
589 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
590 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
591 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
592 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
593 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
594 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
595 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
596 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
597 #if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \
598 defined(CONFIG_SOC_MX6ULL)
599 #define MXC_CCM_CCGR2_LCD_OFFSET 28
600 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
601 #define MXC_CCM_CCGR2_PXP_OFFSET 30
602 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
604 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
605 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
606 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
607 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
610 /* Exist on i.MX6SX */
611 #define MXC_CCM_CCGR3_M4_OFFSET 2
612 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
613 #define MXC_CCM_CCGR3_ENET_OFFSET 4
614 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
615 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
616 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
618 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
619 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
620 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
621 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
622 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
623 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
625 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
626 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
627 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
628 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
629 /* IPU2_DI1 on i.MX6Q, i.MX6DL */
630 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
631 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
632 /* LCDIF on i.MX6UL */
633 #define MXC_CCM_CCGR3_LCDIF_OFFSET 10
634 #define MXC_CCM_CCGR3_LCDIF_MASK (3 << MXC_CCM_CCGR3_LCDIF_OFFSET)
636 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
637 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
639 /* QSPI1 exists on i.MX6SX/UL */
640 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
641 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
643 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
644 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
645 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
646 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
648 /* A7_CLKDIV/WDOG1 on i.MX6UL */
649 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
650 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
651 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
652 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
654 #define MXC_CCM_CCGR3_MLB_OFFSET 18
655 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
656 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
657 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
658 #ifndef CONFIG_SOC_MX6SX
659 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
660 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
662 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
663 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
664 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
665 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
667 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
668 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
669 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
670 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
672 /* GPIO4 on i.MX6UL */
673 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
674 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
677 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
678 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
681 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
682 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
683 /* QSPI2 on i.MX6SX */
684 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
685 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
686 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
687 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
688 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
689 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
690 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
691 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
692 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
693 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
694 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
695 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
696 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
697 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
698 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
699 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
700 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
701 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
702 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
703 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
704 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
705 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
706 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
707 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
709 #define MXC_CCM_CCGR5_ROM_OFFSET 0
710 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
711 #ifndef CONFIG_SOC_MX6SX
712 #define MXC_CCM_CCGR5_SATA_OFFSET 4
713 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
715 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
716 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
717 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
718 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
719 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
720 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
721 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
722 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
723 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
724 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
725 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
726 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
727 #define MXC_CCM_CCGR5_UART_OFFSET 24
728 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
729 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
730 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
731 #ifdef CONFIG_SOC_MX6SX
732 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
733 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
734 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
735 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
738 /* PRG_CLK0 exists on i.MX6QP */
739 #define MXC_CCM_CCGR6_PRG_CLK0_OFFSET 24
740 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << MXC_CCM_CCGR6_PRG_CLK0_OFFSET)
742 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
743 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
744 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
745 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
746 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
747 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
748 /* GPMI/BCH on i.MX6UL */
749 #define MXC_CCM_CCGR6_BCH_OFFSET 6
750 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
751 #define MXC_CCM_CCGR6_GPMI_OFFSET 8
752 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
754 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
755 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
756 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
757 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
758 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
759 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
760 /* The following *CCGR6* exist only on i.MX6SX */
761 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
762 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
763 #define MXC_CCM_CCGR6_VADC_OFFSET 20
764 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
765 #define MXC_CCM_CCGR6_GIS_OFFSET 22
766 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
767 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
768 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
769 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
770 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
771 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
772 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
773 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
774 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
775 /* These two do not exist on i.MX6SX */
776 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
777 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
779 #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
780 #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
781 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
782 #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
783 #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
784 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
785 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
786 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
787 (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
788 BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
789 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
790 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
791 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
792 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
793 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
794 #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
795 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
796 #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
797 #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
798 #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
799 #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
800 #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
801 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
802 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
803 (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
804 BM_ANADIG_PLL_ARM_DIV_SELECT)
806 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
807 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
808 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
809 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
810 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
811 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
812 BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
813 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
814 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
815 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
816 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
817 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
818 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
819 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
820 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
821 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
822 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
823 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
824 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
825 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
826 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
827 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
828 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
829 BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
830 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
831 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
832 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
833 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
834 BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
836 #define BM_ANADIG_PLL_528_LOCK (1 << 31)
837 #define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
838 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
839 #define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
840 #define BM_ANADIG_PLL_528_BYPASS (1 << 16)
841 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
842 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
843 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
844 (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
845 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
846 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
847 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
848 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
849 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
850 #define BM_ANADIG_PLL_528_ENABLE (1 << 13)
851 #define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
852 #define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
853 #define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
854 #define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
855 #define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
856 #define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
857 #define BP_ANADIG_PLL_528_DIV_SELECT 0
858 #define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
859 #define BF_ANADIG_PLL_528_DIV_SELECT(v) \
860 (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
861 BM_ANADIG_PLL_528_DIV_SELECT)
863 #define BP_ANADIG_PLL_528_SS_STOP 16
864 #define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
865 #define BF_ANADIG_PLL_528_SS_STOP(v) \
866 (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
867 BM_ANADIG_PLL_528_SS_STOP)
868 #define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
869 #define BP_ANADIG_PLL_528_SS_STEP 0
870 #define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
871 #define BF_ANADIG_PLL_528_SS_STEP(v) \
872 (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
873 BM_ANADIG_PLL_528_SS_STEP)
875 #define BP_ANADIG_PLL_528_NUM_A 0
876 #define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
877 #define BF_ANADIG_PLL_528_NUM_A(v) \
878 (((v) << BP_ANADIG_PLL_528_NUM_A) & \
879 BM_ANADIG_PLL_528_NUM_A)
881 #define BP_ANADIG_PLL_528_DENOM_B 0
882 #define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
883 #define BF_ANADIG_PLL_528_DENOM_B(v) \
884 (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
885 BM_ANADIG_PLL_528_DENOM_B)
887 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
888 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
889 #define BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT 19
890 #define BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
891 #define BF_ANADIG_PLL_AUDIO_POST_DIV_SELECT(v) \
892 (((v) << BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT) & \
893 BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT)
894 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
895 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
896 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
897 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
898 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
899 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
900 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
901 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
902 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
903 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
904 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
905 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
906 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
907 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
908 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
909 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
910 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
911 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
912 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
913 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
914 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
915 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
916 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
917 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
919 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
920 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
921 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
922 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
923 BM_ANADIG_PLL_AUDIO_NUM_A)
925 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
926 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
927 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
928 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
929 BM_ANADIG_PLL_AUDIO_DENOM_B)
931 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
932 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
933 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
934 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
935 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
936 (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
937 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
938 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
939 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
940 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
941 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
942 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
943 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
944 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
945 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
946 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
947 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
948 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
949 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
950 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
951 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
952 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
953 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
954 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
955 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
956 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
957 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
958 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
959 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
960 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
961 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
963 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
964 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
965 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
966 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
967 BM_ANADIG_PLL_VIDEO_NUM_A)
969 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
970 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
971 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
972 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
973 BM_ANADIG_PLL_VIDEO_DENOM_B)
975 #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
976 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
977 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
978 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
979 (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
980 BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
981 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
982 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
983 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
984 (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
985 BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
986 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
987 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
988 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
989 (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
990 BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
991 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
992 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
993 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
994 (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
995 BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
996 #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
997 #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
998 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
999 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
1000 (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
1001 BM_ANADIG_PLL_MLB_PHASE_SEL)
1002 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
1004 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
1005 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
1006 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
1007 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
1008 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
1009 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
1010 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
1011 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1012 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1013 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1014 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
1015 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1016 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1017 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1018 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1019 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1020 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
1021 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
1022 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
1023 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
1024 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
1025 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
1026 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
1027 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1028 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
1029 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1030 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
1031 BM_ANADIG_PLL_ENET_DIV_SELECT)
1033 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
1034 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
1035 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1036 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
1037 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1038 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
1039 BM_ANADIG_PFD_480_PFD3_FRAC)
1040 #define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
1041 #define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
1042 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1043 #define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
1044 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1045 (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
1046 BM_ANADIG_PFD_480_PFD2_FRAC)
1047 #define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
1048 #define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
1049 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1050 #define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
1051 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1052 (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
1053 BM_ANADIG_PFD_480_PFD1_FRAC)
1054 #define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
1055 #define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
1056 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1057 #define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
1058 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1059 (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
1060 BM_ANADIG_PFD_480_PFD0_FRAC)
1062 #define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
1063 #define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
1064 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1065 #define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
1066 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1067 (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
1068 BM_ANADIG_PFD_528_PFD3_FRAC)
1069 #define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
1070 #define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
1071 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1072 #define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
1073 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1074 (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
1075 BM_ANADIG_PFD_528_PFD2_FRAC)
1076 #define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
1077 #define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
1078 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1079 #define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
1080 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1081 (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
1082 BM_ANADIG_PFD_528_PFD1_FRAC)
1083 #define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
1084 #define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
1085 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1086 #define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
1087 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1088 (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
1089 BM_ANADIG_PFD_528_PFD0_FRAC)
1091 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
1092 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1093 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
1094 (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
1095 BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1096 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
1097 #define BP_ANADIG_ANA_MISC0_ANAMUX 21
1098 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
1099 #define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
1100 (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
1101 BM_ANADIG_ANA_MISC0_ANAMUX)
1102 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
1103 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
1104 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1105 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
1106 (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
1107 BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1108 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
1109 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
1110 #define BP_ANADIG_ANA_MISC0_OSC_I 14
1111 #define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
1112 #define BF_ANADIG_ANA_MISC0_OSC_I(v) \
1113 (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
1114 BM_ANADIG_ANA_MISC0_OSC_I)
1115 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
1116 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
1117 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
1118 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1119 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
1120 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
1121 BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1122 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
1123 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
1124 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1125 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
1126 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
1127 BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1128 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
1129 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
1130 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
1131 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
1133 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
1134 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
1135 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
1136 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
1137 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1138 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
1139 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1140 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
1141 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1142 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
1143 (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
1144 BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1145 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
1146 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1147 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
1148 (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
1149 BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1151 #define BP_ANADIG_ANA_MISC2_CONTROL3 30
1152 #define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
1153 #define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
1154 (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
1155 BM_ANADIG_ANA_MISC2_CONTROL3)
1156 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
1157 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1158 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
1159 (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
1160 BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1161 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
1162 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1163 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
1164 (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
1165 BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1166 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
1167 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1168 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
1169 (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
1170 BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1171 #define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
1172 #define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
1173 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
1174 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
1175 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
1176 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1177 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
1178 (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
1179 BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1180 #define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
1181 #define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
1182 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
1183 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
1184 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
1185 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
1186 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
1187 (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
1188 BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
1189 #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
1190 #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
1191 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
1192 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
1193 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
1194 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1195 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
1196 (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
1197 BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1199 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
1200 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
1201 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
1202 (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
1203 BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
1204 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
1205 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
1206 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
1207 (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
1208 BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
1209 #define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
1210 #define BP_ANADIG_TEMPSENSE0_VBGADJ 3
1211 #define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
1212 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
1213 (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
1214 BM_ANADIG_TEMPSENSE0_VBGADJ)
1215 #define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
1216 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
1217 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
1219 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
1220 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1221 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
1222 (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
1223 BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1226 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */