2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
65 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
66 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
67 #define MXC_CCM_CCR_COSC_EN (1 << 12)
68 #ifdef CONFIG_SOC_MX6SX
69 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
71 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
73 #define MXC_CCM_CCR_OSCNT_OFFSET 0
75 /* Define the bits in register CCDR */
76 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
77 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
78 /* Exists on i.MX6QP */
79 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
81 /* Define the bits in register CSR */
82 #define MXC_CCM_CSR_COSC_READY (1 << 5)
83 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
85 /* Define the bits in register CCSR */
86 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
87 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
88 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
89 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
90 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
91 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
92 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
93 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
94 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
95 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
96 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
98 /* Define the bits in register CACRR */
99 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
100 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
102 /* Define the bits in register CBCDR */
103 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
104 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
105 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
106 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
107 #ifndef CONFIG_SOC_MX6SX
108 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
109 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
111 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
113 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
115 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
116 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
117 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
118 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
119 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
120 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
121 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
122 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
124 /* Define the bits in register CBCMR */
125 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
126 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
127 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
128 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
129 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
130 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
131 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
132 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
133 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
134 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
135 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
136 #ifndef CONFIG_SOC_MX6SX
137 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
138 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
139 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
140 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
142 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
143 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
144 #ifndef CONFIG_SOC_MX6SX
145 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
147 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
148 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
149 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
150 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
151 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
152 /* Exists on i.MX6QP */
153 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
155 /* Define the bits in register CSCMR1 */
156 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
157 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
158 #ifdef CONFIG_SOC_MX6SX
159 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
160 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
162 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
163 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
165 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
166 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
167 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
168 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
169 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
170 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
171 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
172 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
173 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
174 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
175 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
176 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
177 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
178 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
179 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
180 #ifdef CONFIG_SOC_MX6SX
181 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
182 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
184 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
185 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
186 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
188 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
190 /* Define the bits in register CSCMR2 */
191 #ifdef CONFIG_SOC_MX6SX
192 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
193 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
195 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
196 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
197 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
198 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
199 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
200 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
201 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
203 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
204 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
206 /* Define the bits in register CSCDR1 */
207 #ifndef CONFIG_SOC_MX6SX
208 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
209 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
211 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
212 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
213 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
214 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
215 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
216 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
217 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
218 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
219 #ifndef CONFIG_SOC_MX6SX
220 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
221 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
222 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
223 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
225 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
226 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
227 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */
228 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
230 /* Define the bits in register CS1CDR */
231 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
232 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
233 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
234 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
235 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
236 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
237 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
238 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
239 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
240 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
241 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
242 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
244 /* Define the bits in register CS2CDR */
245 #ifdef CONFIG_SOC_MX6SX
246 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
247 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
248 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
249 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
250 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
251 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
252 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
253 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
254 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
256 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
257 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
258 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
259 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
260 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
261 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
263 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
264 (is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
265 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
266 (is_mx6dqp() ? 15 : 16)
267 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
268 (is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
271 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
272 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
273 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
274 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
275 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
276 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
277 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
278 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
280 /* Define the bits in register CDCDR */
281 #ifndef CONFIG_SOC_MX6SX
282 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
283 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
284 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
285 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
287 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
288 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
289 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
290 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
291 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
292 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
293 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
294 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
295 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
296 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
297 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
298 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
300 /* Define the bits in register CHSCCDR */
301 #ifdef CONFIG_SOC_MX6SX
302 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
303 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
304 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
305 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
306 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
307 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
308 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
309 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
310 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
311 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
312 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
313 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
315 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET)
316 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
317 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
318 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
319 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
320 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
321 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET)
322 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
323 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
324 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
325 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
326 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
329 #define CHSCCDR_CLK_SEL_LDB_DI0 3
330 #define CHSCCDR_PODF_DIVIDE_BY_3 2
331 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
333 /* Define the bits in register CSCDR2 */
334 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
335 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
336 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
337 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
339 /* All IPU2_DI1 are LCDIF1 on MX6SX */
340 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
341 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
342 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
343 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
344 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
345 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
346 /* All IPU2_DI0 are LCDIF2 on MX6SX */
347 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
348 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
349 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
350 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
351 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
352 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
354 /* Define the bits in register CSCDR3 */
355 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
356 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
357 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
358 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
359 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
360 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
361 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
362 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
364 /* Define the bits in register CDHIPR */
365 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
366 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
367 #ifndef CONFIG_SOC_MX6SX
368 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
370 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
371 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
372 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
373 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
375 /* Define the bits in register CLPCR */
376 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
377 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
378 #ifndef CONFIG_SOC_MX6SX
379 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
380 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
381 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
383 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
384 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
385 #ifndef CONFIG_SOC_MX6SX
386 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
387 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
389 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
390 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
391 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
392 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
393 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
394 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
395 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
396 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
397 #ifndef CONFIG_SOC_MX6SX
398 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
399 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
400 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
402 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
403 #define MXC_CCM_CLPCR_LPM_OFFSET 0
405 /* Define the bits in register CISR */
406 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
407 #ifndef CONFIG_SOC_MX6SX
408 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
410 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
411 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
412 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
413 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
414 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
415 #define MXC_CCM_CISR_COSC_READY (1 << 6)
416 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
418 /* Define the bits in register CIMR */
419 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
420 #ifndef CONFIG_SOC_MX6SX
421 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
423 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
424 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
425 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
426 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
427 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
428 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
429 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
431 /* Define the bits in register CCOSR */
432 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
433 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
434 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
435 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
436 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
437 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
438 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
439 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
440 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
441 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
442 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
444 /* Define the bits in registers CGPR */
445 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
446 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
447 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
448 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
450 /* Define the bits in registers CCGRx */
451 #define MXC_CCM_CCGR_CG_MASK 3
453 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
454 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
455 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
456 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
457 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
458 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
459 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
460 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
461 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
462 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
463 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
464 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
465 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
466 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
467 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
468 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
469 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
470 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
471 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
472 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
473 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
474 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
475 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
476 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
477 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
478 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
479 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
480 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
481 #ifdef CONFIG_SOC_MX6SX
482 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
483 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
485 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
486 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
489 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
490 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
491 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
492 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
493 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
494 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
495 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
496 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
497 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
498 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
499 #ifndef CONFIG_SOC_MX6SX
500 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
501 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
503 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
504 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
505 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
506 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
507 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
508 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
509 #ifdef CONFIG_SOC_MX6SX
510 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
511 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
513 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
514 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
515 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
516 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
517 #ifndef CONFIG_SOC_MX6SX
518 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
519 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
521 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
522 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
523 #ifdef CONFIG_SOC_MX6SX
524 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
525 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
526 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
527 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
530 #ifndef CONFIG_SOC_MX6SX
531 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
532 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
534 #define MXC_CCM_CCGR2_CSI_OFFSET 2
535 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
537 #ifndef CONFIG_SOC_MX6SX
538 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
539 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
541 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
542 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
543 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
544 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
545 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
546 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
547 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
548 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
549 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
550 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
551 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
552 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
553 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
554 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
555 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
556 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
557 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
558 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
559 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
560 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
561 #ifdef CONFIG_SOC_MX6SX
562 #define MXC_CCM_CCGR2_LCD_OFFSET 28
563 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
564 #define MXC_CCM_CCGR2_PXP_OFFSET 30
565 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
567 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
568 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
569 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
570 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
573 #ifdef CONFIG_SOC_MX6SX
574 #define MXC_CCM_CCGR3_M4_OFFSET 2
575 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
576 #define MXC_CCM_CCGR3_ENET_OFFSET 4
577 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
578 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
579 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
581 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
582 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
583 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
584 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
585 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
586 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
588 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
589 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
590 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
591 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
592 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
593 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
594 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
595 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
596 #ifdef CONFIG_SOC_MX6SX
597 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
598 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
600 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
601 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
602 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
603 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
605 #define MXC_CCM_CCGR3_MLB_OFFSET 18
606 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
607 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
608 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
609 #ifndef CONFIG_SOC_MX6SX
610 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
611 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
613 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
614 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
615 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
616 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
617 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
618 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
619 #ifndef CONFIG_SOC_MX6SX
620 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
621 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
624 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
625 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
626 #ifdef CONFIG_SOC_MX6SX
627 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
628 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
630 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
631 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
633 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
634 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
635 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
636 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
637 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
638 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
639 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
640 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
641 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
642 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
643 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
644 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
645 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
646 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
647 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
648 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
649 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
650 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
651 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
652 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
654 #define MXC_CCM_CCGR5_ROM_OFFSET 0
655 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
656 #ifndef CONFIG_SOC_MX6SX
657 #define MXC_CCM_CCGR5_SATA_OFFSET 4
658 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
660 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
661 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
662 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
663 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
664 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
665 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
666 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
667 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
668 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
669 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
670 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
671 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
672 #define MXC_CCM_CCGR5_UART_OFFSET 24
673 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
674 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
675 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
676 #ifdef CONFIG_SOC_MX6SX
677 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
678 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
679 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
680 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
683 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
684 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
685 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
686 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
687 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
688 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
689 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
690 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
691 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
692 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
693 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
694 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
695 /* The following *CCGR6* exist only on i.MX6SX */
696 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
697 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
698 #define MXC_CCM_CCGR6_VADC_OFFSET 20
699 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
700 #define MXC_CCM_CCGR6_GIS_OFFSET 22
701 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
702 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
703 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
704 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
705 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
706 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
707 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
708 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
709 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
710 /* These two do not exist on i.MX6SX */
711 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
712 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
714 #define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31)
715 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16)
716 #define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14
717 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
718 #define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
719 (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
720 BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
721 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
722 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
723 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
724 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
725 #define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13)
726 #define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12)
727 #define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
728 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10)
729 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9)
730 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8)
731 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7)
732 #define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
733 #define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2
734 #define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
735 #define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \
736 (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
737 BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
738 #define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0
739 #define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
740 #define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \
741 (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
742 BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
744 #define BM_ANADIG_PLL_528_LOCK (1 << 31)
745 #define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
746 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
747 #define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
748 #define BM_ANADIG_PLL_528_BYPASS (1 << 16)
749 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
750 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
751 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
752 (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
753 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
754 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
755 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
756 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
757 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
758 #define BM_ANADIG_PLL_528_ENABLE (1 << 13)
759 #define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
760 #define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
761 #define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
762 #define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
763 #define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
764 #define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
765 #define BP_ANADIG_PLL_528_DIV_SELECT 0
766 #define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
767 #define BF_ANADIG_PLL_528_DIV_SELECT(v) \
768 (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
769 BM_ANADIG_PLL_528_DIV_SELECT)
771 #define BP_ANADIG_PLL_528_SS_STOP 16
772 #define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
773 #define BF_ANADIG_PLL_528_SS_STOP(v) \
774 (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
775 BM_ANADIG_PLL_528_SS_STOP)
776 #define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
777 #define BP_ANADIG_PLL_528_SS_STEP 0
778 #define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
779 #define BF_ANADIG_PLL_528_SS_STEP(v) \
780 (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
781 BM_ANADIG_PLL_528_SS_STEP)
783 #define BP_ANADIG_PLL_528_NUM_A 0
784 #define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
785 #define BF_ANADIG_PLL_528_NUM_A(v) \
786 (((v) << BP_ANADIG_PLL_528_NUM_A) & \
787 BM_ANADIG_PLL_528_NUM_A)
789 #define BP_ANADIG_PLL_528_DENOM_B 0
790 #define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
791 #define BF_ANADIG_PLL_528_DENOM_B(v) \
792 (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
793 BM_ANADIG_PLL_528_DENOM_B)
795 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
796 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
797 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
798 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
799 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
800 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
801 BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
802 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
803 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
804 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
805 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
806 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
807 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
808 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
809 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
810 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
811 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
812 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
813 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
814 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
815 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
816 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
817 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
818 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
819 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
820 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
821 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
822 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
823 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
824 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
825 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
827 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
828 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
829 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
830 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
831 BM_ANADIG_PLL_AUDIO_NUM_A)
833 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
834 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
835 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
836 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
837 BM_ANADIG_PLL_AUDIO_DENOM_B)
839 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
840 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
841 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
842 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
843 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
844 (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
845 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
846 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
847 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
848 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
849 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
850 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
851 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
852 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
853 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
854 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
855 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
856 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
857 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
858 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
859 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
860 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
861 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
862 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
863 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
864 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
865 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
866 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
867 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
868 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
869 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
871 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
872 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
873 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
874 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
875 BM_ANADIG_PLL_VIDEO_NUM_A)
877 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
878 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
879 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
880 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
881 BM_ANADIG_PLL_VIDEO_DENOM_B)
883 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
884 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
885 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
886 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
887 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
888 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
889 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
890 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
891 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
892 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
893 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
894 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
895 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
896 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
897 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
898 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
899 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
900 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
901 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
902 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
903 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
904 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
905 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
906 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
907 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
908 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
909 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
910 BM_ANADIG_PLL_ENET_DIV_SELECT)
912 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
913 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
914 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
915 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
916 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
917 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
918 BM_ANADIG_PFD_480_PFD3_FRAC)
919 #define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
920 #define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
921 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
922 #define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
923 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
924 (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
925 BM_ANADIG_PFD_480_PFD2_FRAC)
926 #define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
927 #define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
928 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
929 #define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
930 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
931 (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
932 BM_ANADIG_PFD_480_PFD1_FRAC)
933 #define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
934 #define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
935 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
936 #define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
937 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
938 (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
939 BM_ANADIG_PFD_480_PFD0_FRAC)
941 #define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
942 #define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
943 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
944 #define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
945 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
946 (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
947 BM_ANADIG_PFD_528_PFD3_FRAC)
948 #define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
949 #define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
950 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
951 #define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
952 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
953 (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
954 BM_ANADIG_PFD_528_PFD2_FRAC)
955 #define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
956 #define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
957 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
958 #define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
959 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
960 (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
961 BM_ANADIG_PFD_528_PFD1_FRAC)
962 #define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
963 #define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
964 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
965 #define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
966 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
967 (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
968 BM_ANADIG_PFD_528_PFD0_FRAC)
970 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
972 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */