2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
61 mxs_reg_32(pll_arm); /* 0x000 */
62 mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */
63 mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */
64 mxs_reg_32(pll_528); /* 0x030 */
65 reg_32(pll_528_ss); /* 0x040 */
66 reg_32(pll_528_num); /* 0x050 */
67 reg_32(pll_528_denom); /* 0x060 */
68 mxs_reg_32(pll_audio); /* 0x070 */
69 reg_32(pll_audio_num); /* 0x080 */
70 reg_32(pll_audio_denom); /* 0x090 */
71 mxs_reg_32(pll_video); /* 0x0a0 */
72 reg_32(pll_video_num); /* 0x0b0 */
73 reg_32(pll_video_denom); /* 0x0c0 */
74 mxs_reg_32(pll_mlb); /* 0x0d0 */
75 mxs_reg_32(pll_enet); /* 0x0e0 */
76 mxs_reg_32(pfd_480); /* 0x0f0 */
77 mxs_reg_32(pfd_528); /* 0x100 */
78 mxs_reg_32(reg_1p1); /* 0x110 */
79 mxs_reg_32(reg_3p0); /* 0x120 */
80 mxs_reg_32(reg_2p5); /* 0x130 */
81 mxs_reg_32(reg_core); /* 0x140 */
82 mxs_reg_32(ana_misc0); /* 0x150 */
83 mxs_reg_32(ana_misc1); /* 0x160 */
84 mxs_reg_32(ana_misc2); /* 0x170 */
85 mxs_reg_32(tempsense0); /* 0x180 */
86 mxs_reg_32(tempsense1); /* 0x190 */
87 mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */
88 mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */
89 mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
90 mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
91 mxs_reg_32(usb1_loopback); /* 0x1e0 */
92 mxs_reg_32(usb1_misc); /* 0x1f0 */
93 mxs_reg_32(usb2_vbus_detect); /* 0x200 */
94 mxs_reg_32(usb2_chrg_detect); /* 0x210 */
95 mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
96 mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
97 mxs_reg_32(usb2_loopback); /* 0x240 */
98 mxs_reg_32(usb2_misc); /* 0x250 */
99 reg_32(digprog); /* 0x260 */
100 reg_32(rsrvd); /* 0x270 */
101 reg_32(digprog_sololite); /* 0x280 */
105 /* Define the bits in register CCR */
106 #define MXC_CCM_CCR_RBC_EN (1 << 27)
107 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
108 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
109 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
110 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
111 #define MXC_CCM_CCR_COSC_EN (1 << 12)
112 #define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET)
113 #define MXC_CCM_CCR_OSCNT_OFFSET 0
115 /* Define the bits in register CCDR */
116 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
117 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
119 /* Define the bits in register CSR */
120 #define MXC_CCM_CSR_COSC_READY (1 << 5)
121 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
123 /* Define the bits in register CCSR */
124 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
125 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
126 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
127 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
128 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
129 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
130 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
131 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
132 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
133 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
134 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
136 /* Define the bits in register CACRR */
137 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
138 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
140 /* Define the bits in register CBCDR */
141 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
142 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
143 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
144 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
145 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
146 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
147 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
148 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
149 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
150 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
151 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
152 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
153 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
154 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
155 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
156 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
157 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
158 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
160 /* Define the bits in register CBCMR */
161 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
162 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
163 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
164 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
165 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
166 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
167 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
168 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
169 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
170 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
171 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
172 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
173 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
174 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
175 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
176 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
177 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
178 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
179 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
180 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
181 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
182 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
183 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
184 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
185 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
187 /* Define the bits in register CSCMR1 */
188 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
189 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
190 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
191 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
192 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
193 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
194 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
195 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
196 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
197 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
198 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
199 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
200 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
201 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
202 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
203 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
204 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
205 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
206 #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
207 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
209 /* Define the bits in register CSCMR2 */
210 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
211 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
212 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
213 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
214 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
215 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
217 /* Define the bits in register CSCDR1 */
218 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
219 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
220 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
221 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
222 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
223 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
224 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
225 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
226 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
227 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
228 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
229 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
230 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
231 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
233 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
234 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
236 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
238 #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
239 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
241 /* Define the bits in register CS1CDR */
242 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
243 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
244 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
245 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
246 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
247 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
248 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
249 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
250 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
251 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
253 /* Define the bits in register CS2CDR */
254 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
255 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
256 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
257 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
258 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
259 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
260 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
261 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
262 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
263 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
264 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
265 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
266 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
267 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
268 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
269 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
270 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
272 /* Define the bits in register CDCDR */
273 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
274 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
275 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
276 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
277 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
278 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
279 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
280 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
281 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
282 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
283 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
284 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
285 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
286 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
287 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
289 /* Define the bits in register CHSCCDR */
290 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
291 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
292 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
293 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
294 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
295 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
296 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
297 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
298 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
299 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
300 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
301 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
303 /* Define the bits in register CSCDR2 */
304 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
305 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
306 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
307 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
308 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
309 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
310 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
311 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
312 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
313 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
314 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
315 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
316 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
317 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
319 /* Define the bits in register CSCDR3 */
320 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
321 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
322 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
323 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
324 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
325 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
326 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
327 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
329 /* Define the bits in register CDHIPR */
330 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
331 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
332 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
333 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
334 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
335 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
336 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
338 /* Define the bits in register CLPCR */
339 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
340 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
341 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
342 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
343 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
344 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
345 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
346 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
347 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
348 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
349 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
350 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
351 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
352 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
353 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
354 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
355 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
356 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
357 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
358 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
359 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
360 #define MXC_CCM_CLPCR_LPM_OFFSET 0
362 /* Define the bits in register CISR */
363 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
364 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
365 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
366 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
367 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
368 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
369 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
370 #define MXC_CCM_CISR_COSC_READY (1 << 6)
371 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
373 /* Define the bits in register CIMR */
374 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
375 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
376 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
377 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
378 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
379 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
380 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
381 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
382 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
384 /* Define the bits in register CCOSR */
385 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
386 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
387 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
388 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
389 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
390 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
391 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
392 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
393 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
394 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
396 /* Define the bits in registers CGPR */
397 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
398 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
399 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
401 /* Define the bits in registers CCGRx */
402 #define MXC_CCM_CCGR_CG_MASK 3
404 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
405 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
406 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
407 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
408 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
409 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
410 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
411 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
412 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
413 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
414 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
415 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
416 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
417 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
418 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
419 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
420 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
421 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
422 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
423 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
424 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
425 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
426 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
427 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
428 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
429 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
430 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
431 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
432 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
433 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
435 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
436 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
437 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
438 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
439 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
440 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
441 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
442 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
443 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
444 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
445 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
446 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
447 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
448 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
449 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
450 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
451 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
452 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
453 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
454 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
455 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
456 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
457 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
458 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
459 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
460 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
462 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
463 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
464 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
465 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
466 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
467 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
468 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
469 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
470 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
471 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
472 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
473 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
474 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
475 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
476 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
477 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
478 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
479 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
480 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
481 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
482 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
483 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
484 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
485 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
486 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
487 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
489 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
490 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
491 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
492 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
493 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
494 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
495 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
496 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
497 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
498 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
499 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
500 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
501 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
502 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
503 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
504 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
505 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
506 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
507 #define MXC_CCM_CCGR3_MLB_OFFSET 18
508 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
509 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
510 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
511 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
512 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
513 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
514 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
515 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
516 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
517 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
518 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
519 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
520 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
522 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
523 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
524 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
525 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
526 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
527 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
528 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
529 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
530 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
531 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
532 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
533 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
534 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
535 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
536 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
537 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
538 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
539 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
540 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
541 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
542 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
543 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
544 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
545 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
547 #define MXC_CCM_CCGR5_ROM_OFFSET 0
548 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
549 #define MXC_CCM_CCGR5_SATA_OFFSET 4
550 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
551 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
552 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
553 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
554 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
555 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
556 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
557 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
558 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
559 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
560 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
561 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
562 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
563 #define MXC_CCM_CCGR5_UART_OFFSET 24
564 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
565 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
566 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
568 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
569 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
570 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
571 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
572 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
573 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
574 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
575 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
576 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
577 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
578 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
579 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
580 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
581 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
583 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
584 #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
585 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
586 #define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
587 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
588 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
589 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
590 #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
591 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
592 #define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
593 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
594 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
595 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
596 #define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
597 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
598 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
599 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
600 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
601 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
602 #define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
603 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
604 #define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
605 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
607 #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
608 #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
609 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
610 #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
611 #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
612 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
613 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
614 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
615 (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
616 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
617 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
618 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
619 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
620 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
621 #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
622 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
623 #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
624 #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
625 #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
626 #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
627 #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
628 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
629 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
630 (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
631 BM_ANADIG_PLL_ARM_DIV_SELECT)
633 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
634 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
635 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
636 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
637 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
638 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
639 BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
640 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0)
641 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1)
642 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2)
643 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3)
644 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
645 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
646 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
647 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
648 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
649 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
650 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
651 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
652 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
653 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
654 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
655 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
656 BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
657 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
658 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
659 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
660 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
661 BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
663 #define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
664 #define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
665 #define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
666 #define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
667 #define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
668 (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \
669 BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
670 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0)
671 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
672 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
673 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
674 #define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
675 #define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
676 #define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
677 #define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
678 #define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
679 #define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
680 #define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
681 #define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
682 #define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
683 #define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
684 #define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \
685 (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \
686 BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
687 #define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
688 #define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
689 #define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \
690 (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \
691 BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
693 #define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
694 #define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
695 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
696 #define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
697 #define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
698 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
699 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
700 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
701 (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
702 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
703 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
704 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
705 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
706 #define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
707 #define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
708 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
709 #define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
710 #define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
711 #define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
712 #define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
713 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
714 #define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
715 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
716 (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
718 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
719 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
720 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
721 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
722 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
723 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
724 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
725 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
726 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
727 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
728 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
729 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
730 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
731 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
732 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
733 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
734 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
735 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
736 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
737 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
738 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
739 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
740 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
741 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
742 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
743 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
744 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
745 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
747 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
748 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
749 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
750 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
752 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
753 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
754 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
755 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
757 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
758 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
759 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
760 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
761 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
762 (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
763 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
764 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
765 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
766 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
767 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
768 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
769 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
770 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
771 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
772 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
773 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
774 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
775 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
776 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
777 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
778 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
779 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
780 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
781 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
782 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
783 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
784 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
786 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
787 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
788 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
789 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
791 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
792 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
793 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
794 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
796 #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
797 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
798 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
799 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
800 (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
801 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
802 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
803 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
804 (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
805 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
806 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
807 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
808 (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
809 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
810 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
811 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
812 (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
813 #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
814 #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
815 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
816 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
817 (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
818 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
820 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
821 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
822 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
823 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
824 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
825 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
826 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
827 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
828 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
829 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
830 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
831 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
832 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
833 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
834 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
835 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
836 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
837 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
838 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
839 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
840 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
841 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
842 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
843 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
844 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
846 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
847 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
848 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
849 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
850 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
851 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC)
853 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
854 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
855 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
856 (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
857 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
858 #define BP_ANADIG_ANA_MISC0_ANAMUX 21
859 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
860 #define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
861 (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX)
862 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
863 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
864 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
865 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
866 (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
867 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
868 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
869 #define BP_ANADIG_ANA_MISC0_OSC_I 14
870 #define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
871 #define BF_ANADIG_ANA_MISC0_OSC_I(v) \
872 (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I)
873 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
874 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
875 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
876 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
877 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
878 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
879 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
880 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
881 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
882 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
883 (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
884 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
885 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
886 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
887 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
889 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
890 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
891 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
892 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
893 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
894 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
895 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
896 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
897 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
898 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
899 (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
900 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
901 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
902 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
903 (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
905 #define BP_ANADIG_ANA_MISC2_CONTROL3 30
906 #define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
907 #define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
908 (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & BM_ANADIG_ANA_MISC2_CONTROL3)
909 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
910 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
911 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
912 (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
913 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
914 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
915 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
916 (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
917 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
918 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
919 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
920 (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
921 #define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
922 #define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
923 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
924 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
925 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
926 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
927 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
928 (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
929 #define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
930 #define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
931 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
932 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
933 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
934 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
935 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
936 (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
937 #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
938 #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
939 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
940 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
941 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
942 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
943 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
944 (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
946 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
947 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
948 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
949 (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
950 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
951 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
952 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
953 (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
954 #define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
955 #define BP_ANADIG_TEMPSENSE0_VBGADJ 3
956 #define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
957 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
958 (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & BM_ANADIG_TEMPSENSE0_VBGADJ)
959 #define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
960 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
961 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
963 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
964 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
965 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
966 (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
969 #define PLL2_PFD0_FREQ 352000000
970 #define PLL2_PFD1_FREQ 594000000
972 #define PLL2_PFD0_FREQ 306580000
973 #define PLL2_PFD1_FREQ 528000000
975 #define PLL2_PFD2_FREQ 396000000
976 #define PLL2_PFD2_DIV_FREQ (PLL2_PFD2_FREQ / 2)
977 #define PLL3_PFD0_FREQ 720000000
978 #define PLL3_PFD1_FREQ 540000000
979 #define PLL3_PFD2_FREQ 508200000
980 #define PLL3_PFD3_FREQ 454700000
981 #define PLL3_80M 80000000
982 #define PLL3_60M 60000000
984 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */