arch/arm/include/asm/arch-mx6/imx-regs.h

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  20 #define __ASM_ARCH_MX6_IMX_REGS_H__
  21
  22 #define ARCH_MXC
  23
  24 #define CONFIG_SYS_CACHELINE_SIZE       32
  25
  26 #define ROMCP_ARB_BASE_ADDR             0x00000000
  27 #define ROMCP_ARB_END_ADDR              0x000FFFFF
  28 #define CAAM_ARB_BASE_ADDR              0x00100000
  29 #define CAAM_ARB_END_ADDR               0x00103FFF
  30 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
  31 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
  32 #define HDMI_ARB_BASE_ADDR              0x00120000
  33 #define HDMI_ARB_END_ADDR               0x00128FFF
  34 #define GPU_3D_ARB_BASE_ADDR            0x00130000
  35 #define GPU_3D_ARB_END_ADDR             0x00133FFF
  36 #define GPU_2D_ARB_BASE_ADDR            0x00134000
  37 #define GPU_2D_ARB_END_ADDR             0x00137FFF
  38 #define DTCP_ARB_BASE_ADDR              0x00138000
  39 #define DTCP_ARB_END_ADDR               0x0013BFFF
  40
  41 /* GPV - PL301 configuration ports */
  42 #define GPV2_BASE_ADDR                  0x00200000
  43 #define GPV3_BASE_ADDR                  0x00300000
  44 #define GPV4_BASE_ADDR                  0x00800000
  45 #define IRAM_BASE_ADDR                  0x00900000
  46 #define SCU_BASE_ADDR                   0x00A00000
  47 #define IC_INTERFACES_BASE_ADDR         0x00A00100
  48 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
  49 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
  50 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
  51 #define GPV0_BASE_ADDR                  0x00B00000
  52 #define GPV1_BASE_ADDR                  0x00C00000
  53 #define PCIE_ARB_BASE_ADDR              0x01000000
  54 #define PCIE_ARB_END_ADDR               0x01FFFFFF
  55
  56 #define AIPS1_ARB_BASE_ADDR             0x02000000
  57 #define AIPS1_ARB_END_ADDR              0x020FFFFF
  58 #define AIPS2_ARB_BASE_ADDR             0x02100000
  59 #define AIPS2_ARB_END_ADDR              0x021FFFFF
  60 #define SATA_ARB_BASE_ADDR              0x02200000
  61 #define SATA_ARB_END_ADDR               0x02203FFF
  62 #define OPENVG_ARB_BASE_ADDR            0x02204000
  63 #define OPENVG_ARB_END_ADDR             0x02207FFF
  64 #define HSI_ARB_BASE_ADDR               0x02208000
  65 #define HSI_ARB_END_ADDR                0x0220BFFF
  66 #define IPU1_ARB_BASE_ADDR              0x02400000
  67 #define IPU1_ARB_END_ADDR               0x027FFFFF
  68 #define IPU2_ARB_BASE_ADDR              0x02800000
  69 #define IPU2_ARB_END_ADDR               0x02BFFFFF
  70 #define WEIM_ARB_BASE_ADDR              0x08000000
  71 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
  72
  73 #define MMDC0_ARB_BASE_ADDR             0x10000000
  74 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
  75 #define MMDC1_ARB_BASE_ADDR             0x80000000
  76 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
  77
  78 #define IPU_SOC_BASE_ADDR               IPU1_ARB_BASE_ADDR
  79 #define IPU_SOC_OFFSET                  0x00200000
  80
  81 /* Defines for Blocks connected via AIPS (SkyBlue) */
  82 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
  83 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
  84 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
  85 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
  86
  87 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
  88 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
  89 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
  90 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
  91 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
  92 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
  93 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
  94 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
  95 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
  96 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
  97 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
  98 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
  99 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 100 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 101 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
 102
 103 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
 104 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
 105 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
 106 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
 107 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
 108 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
 109 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
 110 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
 111 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
 112 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
 113 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
 114 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 115 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
 116 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 117 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 118 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 119 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 120 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
 121 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
 122 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
 123 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
 124 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
 125 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
 126 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
 127 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
 128 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
 129 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
 130 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
 131 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 132 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 133 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
 134
 135 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
 136 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 137 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 138 #define ARM_BASE_ADDR               (ATZ2_BASE_ADDR + 0x40000)
 139 #define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
 140 #define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
 141 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 142 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
 143 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
 144 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 145 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
 146 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
 147 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
 148 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
 149 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
 150 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
 151 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 152 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
 153 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 154 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 155 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
 156 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 157 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 158 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 159 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 160 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
 161 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 162 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 163 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 164 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
 165 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
 166 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 167 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 168 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
 169 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 170 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 171
 172 #define CHIP_REV_1_0                 0x10
 173 #define IRAM_SIZE                    0x00040000
 174 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 175 #define FEC_QUIRK_ENET_MAC
 176
 177 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 178 #include <asm/types.h>
 179
 180 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 181
 182 /* System Reset Controller (SRC) */
 183 struct src {
 184         u32     scr;
 185         u32     sbmr1;
 186         u32     srsr;
 187         u32     reserved1[2];
 188         u32     sisr;
 189         u32     simr;
 190         u32     sbmr2;
 191         u32     gpr1;
 192         u32     gpr2;
 193         u32     gpr3;
 194         u32     gpr4;
 195         u32     gpr5;
 196         u32     gpr6;
 197         u32     gpr7;
 198         u32     gpr8;
 199         u32     gpr9;
 200         u32     gpr10;
 201 };
 202
 203 /* ECSPI registers */
 204 struct cspi_regs {
 205         u32 rxdata;
 206         u32 txdata;
 207         u32 ctrl;
 208         u32 cfg;
 209         u32 intr;
 210         u32 dma;
 211         u32 stat;
 212         u32 period;
 213 };
 214
 215 /*
 216  * CSPI register definitions
 217  */
 218 #define MXC_ECSPI
 219 #define MXC_CSPICTRL_EN         (1 << 0)
 220 #define MXC_CSPICTRL_MODE       (1 << 1)
 221 #define MXC_CSPICTRL_XCH        (1 << 2)
 222 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
 223 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
 224 #define MXC_CSPICTRL_PREDIV(x)  (((x) & 0xF) << 12)
 225 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
 226 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
 227 #define MXC_CSPICTRL_MAXBITS    0xfff
 228 #define MXC_CSPICTRL_TC         (1 << 7)
 229 #define MXC_CSPICTRL_RXOVF      (1 << 6)
 230 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
 231 #define MAX_SPI_BYTES   32
 232
 233 /* Bit position inside CTRL register to be associated with SS */
 234 #define MXC_CSPICTRL_CHAN       18
 235
 236 /* Bit position inside CON register to be associated with SS */
 237 #define MXC_CSPICON_POL         4
 238 #define MXC_CSPICON_PHA         0
 239 #define MXC_CSPICON_SSPOL       12
 240 #define MXC_SPI_BASE_ADDRESSES \
 241         ECSPI1_BASE_ADDR, \
 242         ECSPI2_BASE_ADDR, \
 243         ECSPI3_BASE_ADDR, \
 244         ECSPI4_BASE_ADDR, \
 245         ECSPI5_BASE_ADDR
 246
 247 struct iim_regs {
 248         u32     ctrl;
 249         u32     ctrl_set;
 250         u32     ctrl_clr;
 251         u32     ctrl_tog;
 252         u32     timing;
 253         u32     rsvd0[3];
 254         u32     data;
 255         u32     rsvd1[3];
 256         u32     read_ctrl;
 257         u32     rsvd2[3];
 258         u32     fuse_data;
 259         u32     rsvd3[3];
 260         u32     sticky;
 261         u32     rsvd4[3];
 262         u32     scs;
 263         u32     scs_set;
 264         u32     scs_clr;
 265         u32     scs_tog;
 266         u32     crc_addr;
 267         u32     rsvd5[3];
 268         u32     crc_value;
 269         u32     rsvd6[3];
 270         u32     version;
 271         u32     rsvd7[0xdb];
 272
 273         struct fuse_bank {
 274                 u32     fuse_regs[0x20];
 275         } bank[15];
 276 };
 277
 278 struct fuse_bank4_regs {
 279         u32     sjc_resp_low;
 280         u32     rsvd0[3];
 281         u32     sjc_resp_high;
 282         u32     rsvd1[3];
 283         u32     mac_addr_low;
 284         u32     rsvd2[3];
 285         u32     mac_addr_high;
 286         u32     rsvd3[0x13];
 287 };
 288
 289 struct aipstz_regs {
 290         u32     mprot0;
 291         u32     mprot1;
 292         u32     rsvd[0xe];
 293         u32     opacr0;
 294         u32     opacr1;
 295         u32     opacr2;
 296         u32     opacr3;
 297         u32     opacr4;
 298 };
 299
 300 struct anatop_regs {
 301         u32     pll_sys;                /* 0x000 */
 302         u32     pll_sys_set;            /* 0x004 */
 303         u32     pll_sys_clr;            /* 0x008 */
 304         u32     pll_sys_tog;            /* 0x00c */
 305         u32     usb1_pll_480_ctrl;      /* 0x010 */
 306         u32     usb1_pll_480_ctrl_set;  /* 0x014 */
 307         u32     usb1_pll_480_ctrl_clr;  /* 0x018 */
 308         u32     usb1_pll_480_ctrl_tog;  /* 0x01c */
 309         u32     usb2_pll_480_ctrl;      /* 0x020 */
 310         u32     usb2_pll_480_ctrl_set;  /* 0x024 */
 311         u32     usb2_pll_480_ctrl_clr;  /* 0x028 */
 312         u32     usb2_pll_480_ctrl_tog;  /* 0x02c */
 313         u32     pll_528;                /* 0x030 */
 314         u32     pll_528_set;            /* 0x034 */
 315         u32     pll_528_clr;            /* 0x038 */
 316         u32     pll_528_tog;            /* 0x03c */
 317         u32     pll_528_ss;             /* 0x040 */
 318         u32     rsvd0[3];
 319         u32     pll_528_num;            /* 0x050 */
 320         u32     rsvd1[3];
 321         u32     pll_528_denom;          /* 0x060 */
 322         u32     rsvd2[3];
 323         u32     pll_audio;              /* 0x070 */
 324         u32     pll_audio_set;          /* 0x074 */
 325         u32     pll_audio_clr;          /* 0x078 */
 326         u32     pll_audio_tog;          /* 0x07c */
 327         u32     pll_audio_num;          /* 0x080 */
 328         u32     rsvd3[3];
 329         u32     pll_audio_denom;        /* 0x090 */
 330         u32     rsvd4[3];
 331         u32     pll_video;              /* 0x0a0 */
 332         u32     pll_video_set;          /* 0x0a4 */
 333         u32     pll_video_clr;          /* 0x0a8 */
 334         u32     pll_video_tog;          /* 0x0ac */
 335         u32     pll_video_num;          /* 0x0b0 */
 336         u32     rsvd5[3];
 337         u32     pll_video_denom;        /* 0x0c0 */
 338         u32     rsvd6[3];
 339         u32     pll_mlb;                /* 0x0d0 */
 340         u32     pll_mlb_set;            /* 0x0d4 */
 341         u32     pll_mlb_clr;            /* 0x0d8 */
 342         u32     pll_mlb_tog;            /* 0x0dc */
 343         u32     pll_enet;               /* 0x0e0 */
 344         u32     pll_enet_set;           /* 0x0e4 */
 345         u32     pll_enet_clr;           /* 0x0e8 */
 346         u32     pll_enet_tog;           /* 0x0ec */
 347         u32     pfd_480;                /* 0x0f0 */
 348         u32     pfd_480_set;            /* 0x0f4 */
 349         u32     pfd_480_clr;            /* 0x0f8 */
 350         u32     pfd_480_tog;            /* 0x0fc */
 351         u32     pfd_528;                /* 0x100 */
 352         u32     pfd_528_set;            /* 0x104 */
 353         u32     pfd_528_clr;            /* 0x108 */
 354         u32     pfd_528_tog;            /* 0x10c */
 355         u32     reg_1p1;                /* 0x110 */
 356         u32     reg_1p1_set;            /* 0x114 */
 357         u32     reg_1p1_clr;            /* 0x118 */
 358         u32     reg_1p1_tog;            /* 0x11c */
 359         u32     reg_3p0;                /* 0x120 */
 360         u32     reg_3p0_set;            /* 0x124 */
 361         u32     reg_3p0_clr;            /* 0x128 */
 362         u32     reg_3p0_tog;            /* 0x12c */
 363         u32     reg_2p5;                /* 0x130 */
 364         u32     reg_2p5_set;            /* 0x134 */
 365         u32     reg_2p5_clr;            /* 0x138 */
 366         u32     reg_2p5_tog;            /* 0x13c */
 367         u32     reg_core;               /* 0x140 */
 368         u32     reg_core_set;           /* 0x144 */
 369         u32     reg_core_clr;           /* 0x148 */
 370         u32     reg_core_tog;           /* 0x14c */
 371         u32     ana_misc0;              /* 0x150 */
 372         u32     ana_misc0_set;          /* 0x154 */
 373         u32     ana_misc0_clr;          /* 0x158 */
 374         u32     ana_misc0_tog;          /* 0x15c */
 375         u32     ana_misc1;              /* 0x160 */
 376         u32     ana_misc1_set;          /* 0x164 */
 377         u32     ana_misc1_clr;          /* 0x168 */
 378         u32     ana_misc1_tog;          /* 0x16c */
 379         u32     ana_misc2;              /* 0x170 */
 380         u32     ana_misc2_set;          /* 0x174 */
 381         u32     ana_misc2_clr;          /* 0x178 */
 382         u32     ana_misc2_tog;          /* 0x17c */
 383         u32     tempsense0;             /* 0x180 */
 384         u32     tempsense0_set;         /* 0x184 */
 385         u32     tempsense0_clr;         /* 0x188 */
 386         u32     tempsense0_tog;         /* 0x18c */
 387         u32     tempsense1;             /* 0x190 */
 388         u32     tempsense1_set;         /* 0x194 */
 389         u32     tempsense1_clr;         /* 0x198 */
 390         u32     tempsense1_tog;         /* 0x19c */
 391         u32     usb1_vbus_detect;       /* 0x1a0 */
 392         u32     usb1_vbus_detect_set;   /* 0x1a4 */
 393         u32     usb1_vbus_detect_clr;   /* 0x1a8 */
 394         u32     usb1_vbus_detect_tog;   /* 0x1ac */
 395         u32     usb1_chrg_detect;       /* 0x1b0 */
 396         u32     usb1_chrg_detect_set;   /* 0x1b4 */
 397         u32     usb1_chrg_detect_clr;   /* 0x1b8 */
 398         u32     usb1_chrg_detect_tog;   /* 0x1bc */
 399         u32     usb1_vbus_det_stat;     /* 0x1c0 */
 400         u32     usb1_vbus_det_stat_set; /* 0x1c4 */
 401         u32     usb1_vbus_det_stat_clr; /* 0x1c8 */
 402         u32     usb1_vbus_det_stat_tog; /* 0x1cc */
 403         u32     usb1_chrg_det_stat;     /* 0x1d0 */
 404         u32     usb1_chrg_det_stat_set; /* 0x1d4 */
 405         u32     usb1_chrg_det_stat_clr; /* 0x1d8 */
 406         u32     usb1_chrg_det_stat_tog; /* 0x1dc */
 407         u32     usb1_loopback;          /* 0x1e0 */
 408         u32     usb1_loopback_set;      /* 0x1e4 */
 409         u32     usb1_loopback_clr;      /* 0x1e8 */
 410         u32     usb1_loopback_tog;      /* 0x1ec */
 411         u32     usb1_misc;              /* 0x1f0 */
 412         u32     usb1_misc_set;          /* 0x1f4 */
 413         u32     usb1_misc_clr;          /* 0x1f8 */
 414         u32     usb1_misc_tog;          /* 0x1fc */
 415         u32     usb2_vbus_detect;       /* 0x200 */
 416         u32     usb2_vbus_detect_set;   /* 0x204 */
 417         u32     usb2_vbus_detect_clr;   /* 0x208 */
 418         u32     usb2_vbus_detect_tog;   /* 0x20c */
 419         u32     usb2_chrg_detect;       /* 0x210 */
 420         u32     usb2_chrg_detect_set;   /* 0x214 */
 421         u32     usb2_chrg_detect_clr;   /* 0x218 */
 422         u32     usb2_chrg_detect_tog;   /* 0x21c */
 423         u32     usb2_vbus_det_stat;     /* 0x220 */
 424         u32     usb2_vbus_det_stat_set; /* 0x224 */
 425         u32     usb2_vbus_det_stat_clr; /* 0x228 */
 426         u32     usb2_vbus_det_stat_tog; /* 0x22c */
 427         u32     usb2_chrg_det_stat;     /* 0x230 */
 428         u32     usb2_chrg_det_stat_set; /* 0x234 */
 429         u32     usb2_chrg_det_stat_clr; /* 0x238 */
 430         u32     usb2_chrg_det_stat_tog; /* 0x23c */
 431         u32     usb2_loopback;          /* 0x240 */
 432         u32     usb2_loopback_set;      /* 0x244 */
 433         u32     usb2_loopback_clr;      /* 0x248 */
 434         u32     usb2_loopback_tog;      /* 0x24c */
 435         u32     usb2_misc;              /* 0x250 */
 436         u32     usb2_misc_set;          /* 0x254 */
 437         u32     usb2_misc_clr;          /* 0x258 */
 438         u32     usb2_misc_tog;          /* 0x25c */
 439         u32     digprog;                /* 0x260 */
 440 };
 441
 442 struct iomuxc_base_regs {
 443         u32     gpr[14];        /* 0x000 */
 444         u32     obsrv[5];       /* 0x038 */
 445         u32     swmux_ctl[197]; /* 0x04c */
 446         u32     swpad_ctl[250]; /* 0x360 */
 447         u32     swgrp[26];      /* 0x748 */
 448         u32     daisy[104];     /* 0x7b0..94c */
 449 };
 450
 451 struct src_regs {
 452         u32     scr;            /* 0x00 */
 453         u32     sbmr1;          /* 0x04 */
 454         u32     srsr;           /* 0x08 */
 455         u32     reserved1;      /* 0x0c */
 456         u32     reserved2;      /* 0x10 */
 457         u32     sisr;           /* 0x14 */
 458         u32     simr;           /* 0x18 */
 459         u32     sbmr2;          /* 0x1c */
 460         u32     gpr1;           /* 0x20 */
 461         u32     gpr2;           /* 0x24 */
 462         u32     gpr3;           /* 0x28 */
 463         u32     gpr4;           /* 0x2c */
 464         u32     gpr5;           /* 0x30 */
 465         u32     gpr6;           /* 0x34 */
 466         u32     gpr7;           /* 0x38 */
 467         u32     gpr8;           /* 0x3c */
 468         u32     gpr9;           /* 0x40 */
 469         u32     gpr10;          /* 0x44 */
 470 };
 471
 472 #endif /* __ASSEMBLER__*/
 473 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */