2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18 * Auto Generate file, please don't edit it
22 #ifndef __MACH_IOMUX_MX6Q_H__
23 #define __MACH_IOMUX_MX6Q_H__
25 #include <asm/arch/iomux-v3.h>
28 * Use to set PAD control
30 #define MX6_PAD_CTL_HYS (1 << 16)
32 #define MX6_PAD_CTL_PUS_100K_DOWN (MX6_PAD_CTL_PULL | (0 << 14))
33 #define MX6_PAD_CTL_PUS_47K_UP (MX6_PAD_CTL_PULL | (1 << 14))
34 #define MX6_PAD_CTL_PUS_100K_UP (MX6_PAD_CTL_PULL | (2 << 14))
35 #define MX6_PAD_CTL_PUS_22K_UP (MX6_PAD_CTL_PULL | (3 << 14))
37 #define MX6_PAD_CTL_PULL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE)
38 #define MX6_PAD_CTL_PUE (1 << 13)
39 #define MX6_PAD_CTL_PKE (1 << 12)
40 #define MX6_PAD_CTL_ODE (1 << 11)
42 #define MX6_PAD_CTL_SPEED_LOW (1 << 6)
43 #define MX6_PAD_CTL_SPEED_MED (2 << 6)
44 #define MX6_PAD_CTL_SPEED_HIGH (3 << 6)
46 #define MX6_PAD_CTL_DSE_DISABLE (0 << 3)
47 #define MX6_PAD_CTL_DSE_240ohm (1 << 3)
48 #define MX6_PAD_CTL_DSE_120ohm (2 << 3)
49 #define MX6_PAD_CTL_DSE_80ohm (3 << 3)
50 #define MX6_PAD_CTL_DSE_60ohm (4 << 3)
51 #define MX6_PAD_CTL_DSE_48ohm (5 << 3)
52 #define MX6_PAD_CTL_DSE_40ohm (6 << 3)
53 #define MX6_PAD_CTL_DSE_34ohm (7 << 3)
55 #define MX6_PAD_CTL_SRE_FAST (1 << 0)
56 #define MX6_PAD_CTL_SRE_SLOW (0 << 0)
58 #define MX6Q_UART_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
59 MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
61 #define MX6Q_ECSPI_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \
62 MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
64 #define MX6Q_USDHC_PAD_CTRL (MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_MED | \
65 MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
67 #define MX6Q_ENET_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
68 MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
70 #define MX6Q_I2C_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
71 MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
72 MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
74 #define MX6Q_PWM_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
75 MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
78 #define MX6Q_HIGH_DRV MX6_PAD_CTL_DSE_120ohm
80 #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
81 IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
82 #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
83 IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
84 #define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
85 IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
86 #define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
87 IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
88 #define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
89 IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
90 #define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
91 IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
92 #define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
93 IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
94 #define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
95 IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
97 #define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
98 IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
99 #define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
100 IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
101 #define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
102 IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
103 #define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
104 IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
105 #define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
106 IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
107 #define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
108 IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
109 #define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
110 IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
111 #define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
112 IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
114 #define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
115 IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
116 #define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
117 IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
118 #define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
119 IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
120 #define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
121 IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
122 #define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
123 IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
124 #define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
125 IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
126 #define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
127 IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
129 #define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
130 IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
131 #define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
132 IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
133 #define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
134 IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
135 #define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
136 IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
137 #define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
138 IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
139 #define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
140 IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
142 #define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
143 IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
144 #define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
145 IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
146 #define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
147 IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
148 #define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
149 IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
151 #define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
152 IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
153 #define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
154 IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
155 #define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
156 IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
157 #define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
158 IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
159 #define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
160 IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
162 #define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
163 IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
164 #define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
165 IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
166 #define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
167 IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
168 #define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
169 IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
170 #define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
171 IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
173 #define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
174 IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
175 #define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
176 IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
177 #define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
178 IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
179 #define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
180 IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
182 #define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
183 IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
184 #define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
185 IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
186 #define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
187 IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
188 #define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
189 IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
191 #define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
192 IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
193 #define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
194 IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
195 #define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
196 IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
197 #define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
198 IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
200 #define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
201 IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
202 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
203 IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
204 #define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
205 IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
206 #define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
207 IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
208 #define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
209 IOMUX_PAD(0x0388, 0x0074, 0x17, 0x083C, 0, 0)
211 #define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
212 IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
213 #define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
214 IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
215 #define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
216 IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
217 #define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
218 IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
219 #define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
220 IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
222 #define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
223 IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
224 #define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
225 IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
226 #define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
227 IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
228 #define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
229 IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
231 #define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
232 IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
233 #define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
234 IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
235 #define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
236 IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
237 #define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
238 IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
240 #define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
241 IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
242 #define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
243 IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
244 #define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
245 IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
246 #define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
247 IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
249 #define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
250 IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
251 #define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
252 IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
253 #define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
254 IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
255 #define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
256 IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
257 #define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
258 IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
259 #define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
260 IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
261 #define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
262 IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
263 #define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
264 IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
266 #define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
267 IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
268 #define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
269 IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
270 #define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
271 IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
272 #define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
273 IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
274 #define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
275 IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
276 #define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
277 IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
278 #define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
279 IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
280 #define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
281 IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
283 #define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
284 IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
285 #define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
286 IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
287 #define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
288 IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
289 #define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
290 IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
291 #define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
292 IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
293 #define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
294 IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
295 #define _MX6Q_PAD_EIM_D16__I2C2_SDA \
296 IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
298 #define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
299 IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
300 #define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
301 IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
302 #define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
303 IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
304 #define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
305 IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
306 #define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
307 IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
308 #define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
309 IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
310 #define _MX6Q_PAD_EIM_D17__I2C3_SCL \
311 IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
312 #define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
313 IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
315 #define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
316 IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
317 #define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
318 IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
319 #define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
320 IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
321 #define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
322 IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
323 #define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
324 IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
325 #define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
326 IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
327 #define _MX6Q_PAD_EIM_D18__I2C3_SDA \
328 IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
329 #define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
330 IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
332 #define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
333 IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
334 #define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
335 IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
336 #define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
337 IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
338 #define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
339 IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
340 #define _MX6Q_PAD_EIM_D19__UART1_CTS \
341 IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0)
342 #define _MX6Q_PAD_EIM_D19__UART1_RTS \
343 IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
344 #define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
345 IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
346 #define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
347 IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
348 #define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
349 IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
351 #define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
352 IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
353 #define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
354 IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
355 #define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
356 IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
357 #define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
358 IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
359 #define _MX6Q_PAD_EIM_D20__UART1_CTS \
360 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
361 #define _MX6Q_PAD_EIM_D20__UART1_RTS \
362 IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
363 #define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
364 IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
365 #define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
366 IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
368 #define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
369 IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
370 #define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
371 IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
372 #define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
373 IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
374 #define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
375 IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
376 #define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
377 IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
378 #define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
379 IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
380 #define _MX6Q_PAD_EIM_D21__I2C1_SCL \
381 IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
382 #define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
383 IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
385 #define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
386 IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
387 #define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
388 IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
389 #define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
390 IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
391 #define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
392 IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
393 #define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
394 IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
395 #define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
396 IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
397 #define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
398 IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
399 #define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
400 IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
402 #define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
403 IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
404 #define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
405 IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
406 #define _MX6Q_PAD_EIM_D23__UART3_CTS \
407 IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0)
408 #define _MX6Q_PAD_EIM_D23__UART3_RTS \
409 IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
410 #define _MX6Q_PAD_EIM_D23__UART1_DCD \
411 IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
412 #define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
413 IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
414 #define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
415 IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
416 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
417 IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
418 #define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
419 IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
421 #define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
422 IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
423 #define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
424 IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
425 #define _MX6Q_PAD_EIM_EB3__UART3_CTS \
426 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
427 #define _MX6Q_PAD_EIM_EB3__UART3_RTS \
428 IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
429 #define _MX6Q_PAD_EIM_EB3__UART1_RI \
430 IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
431 #define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
432 IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
433 #define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
434 IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
435 #define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
436 IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
437 #define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
438 IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
440 #define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
441 IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
442 #define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
443 IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
444 #define _MX6Q_PAD_EIM_D24__UART3_TXD \
445 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
446 #define _MX6Q_PAD_EIM_D24__UART3_RXD \
447 IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
448 #define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
449 IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
450 #define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
451 IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
452 #define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
453 IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
454 #define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
455 IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
456 #define _MX6Q_PAD_EIM_D24__UART1_DTR \
457 IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
459 #define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
460 IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
461 #define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
462 IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
463 #define _MX6Q_PAD_EIM_D25__UART3_TXD \
464 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
465 #define _MX6Q_PAD_EIM_D25__UART3_RXD \
466 IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
467 #define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
468 IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
469 #define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
470 IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
471 #define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
472 IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
473 #define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
474 IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
475 #define _MX6Q_PAD_EIM_D25__UART1_DSR \
476 IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
478 #define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
479 IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
480 #define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
481 IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
482 #define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
483 IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
484 #define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
485 IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
486 #define _MX6Q_PAD_EIM_D26__UART2_TXD \
487 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
488 #define _MX6Q_PAD_EIM_D26__UART2_RXD \
489 IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
490 #define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
491 IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
492 #define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
493 IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
494 #define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
495 IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
497 #define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
498 IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
499 #define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
500 IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
501 #define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
502 IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
503 #define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
504 IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
505 #define _MX6Q_PAD_EIM_D27__UART2_TXD \
506 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
507 #define _MX6Q_PAD_EIM_D27__UART2_RXD \
508 IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
509 #define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
510 IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
511 #define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
512 IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
513 #define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
514 IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
516 #define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
517 IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
518 #define _MX6Q_PAD_EIM_D28__I2C1_SDA \
519 IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
520 #define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
521 IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
522 #define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
523 IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
524 #define _MX6Q_PAD_EIM_D28__UART2_CTS \
525 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
526 #define _MX6Q_PAD_EIM_D28__UART2_RTS \
527 IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
528 #define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
529 IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
530 #define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
531 IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
532 #define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
533 IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
535 #define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
536 IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
537 #define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
538 IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
539 #define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
540 IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
541 #define _MX6Q_PAD_EIM_D29__UART2_CTS \
542 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
543 #define _MX6Q_PAD_EIM_D29__UART2_RTS \
544 IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
545 #define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
546 IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
547 #define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
548 IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
549 #define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
550 IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
552 #define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
553 IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
554 #define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
555 IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
556 #define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
557 IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
558 #define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
559 IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
560 #define _MX6Q_PAD_EIM_D30__UART3_CTS \
561 IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 2, 0)
562 #define _MX6Q_PAD_EIM_D30__UART3_RTS \
563 IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
564 #define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
565 IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
566 #define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
567 IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
568 #define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
569 IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
571 #define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
572 IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
573 #define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
574 IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
575 #define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
576 IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
577 #define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
578 IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
579 #define _MX6Q_PAD_EIM_D31__UART3_CTS \
580 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
581 #define _MX6Q_PAD_EIM_D31__UART3_RTS \
582 IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
583 #define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
584 IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
585 #define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
586 IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
587 #define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
588 IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
590 #define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
591 IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
592 #define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
593 IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
594 #define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
595 IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
596 #define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
597 IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
598 #define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
599 IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
600 #define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
601 IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
602 #define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
603 IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
604 #define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
605 IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
607 #define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
608 IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
609 #define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
610 IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
611 #define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
612 IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
613 #define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
614 IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
615 #define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
616 IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
617 #define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
618 IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
619 #define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
620 IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
621 #define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
622 IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
624 #define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
625 IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
626 #define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
627 IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
628 #define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
629 IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
630 #define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
631 IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
632 #define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
633 IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
634 #define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
635 IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
637 #define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
638 IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
639 #define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
640 IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
641 #define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
642 IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
643 #define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
644 IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
645 #define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
646 IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
647 #define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
648 IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
649 #define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
650 IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
652 #define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
653 IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
654 #define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
655 IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
656 #define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
657 IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
658 #define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
659 IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
660 #define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
661 IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
662 #define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
663 IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
664 #define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
665 IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
667 #define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
668 IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
669 #define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
670 IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
671 #define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
672 IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
673 #define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
674 IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
675 #define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
676 IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
677 #define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
678 IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
679 #define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
680 IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
682 #define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
683 IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
684 #define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
685 IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
686 #define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
687 IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
688 #define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
689 IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
690 #define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
691 IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
692 #define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
693 IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
694 #define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
695 IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
697 #define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
698 IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
699 #define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
700 IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
701 #define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
702 IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
703 #define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
704 IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
705 #define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
706 IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
707 #define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
708 IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
709 #define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
710 IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
712 #define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
713 IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
714 #define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
715 IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
716 #define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
717 IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
718 #define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
719 IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
720 #define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
721 IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
722 #define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
723 IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
724 #define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
725 IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
727 #define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
728 IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
729 #define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
730 IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
731 #define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
732 IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
733 #define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
734 IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
735 #define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
736 IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
737 #define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
738 IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
740 #define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
741 IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
742 #define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
743 IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
744 #define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
745 IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
746 #define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
747 IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
748 #define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
749 IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
750 #define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
751 IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
753 #define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
754 IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
755 #define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
756 IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
757 #define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
758 IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
759 #define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
760 IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
761 #define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
762 IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
763 #define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
764 IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
766 #define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
767 IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
768 #define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
769 IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
770 #define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
771 IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
772 #define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
773 IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
774 #define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
775 IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
776 #define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
777 IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
778 #define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
779 IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
781 #define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
782 IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
783 #define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
784 IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
785 #define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
786 IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
787 #define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
788 IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
789 #define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
790 IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
791 #define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
792 IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
794 #define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
795 IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
796 #define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
797 IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
798 #define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
799 IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
800 #define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
801 IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
802 #define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
803 IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
804 #define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
805 IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
806 #define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
807 IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
808 #define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
809 IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
811 #define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
812 IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
813 #define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
814 IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
815 #define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
816 IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
817 #define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
818 IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
819 #define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
820 IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
821 #define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
822 IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
823 #define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
824 IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
826 #define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
827 IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
828 #define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
829 IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
830 #define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
831 IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
832 #define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
833 IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
834 #define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
835 IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
836 #define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
837 IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
838 #define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
839 IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
841 #define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
842 IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
843 #define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
844 IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
845 #define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
846 IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
847 #define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
848 IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
849 #define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
850 IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
851 #define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
852 IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
853 #define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
854 IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
855 #define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
856 IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
858 #define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
859 IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
860 #define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
861 IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
862 #define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
863 IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
864 #define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
865 IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
866 #define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
867 IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
868 #define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
869 IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
870 #define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
871 IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
872 #define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
873 IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
875 #define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
876 IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
877 #define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
878 IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
879 #define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
880 IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
881 #define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
882 IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
883 #define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
884 IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
885 #define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
886 IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
887 #define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
888 IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
889 #define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
890 IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
892 #define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
893 IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
894 #define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
895 IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
896 #define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
897 IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
898 #define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
899 IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
900 #define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
901 IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
902 #define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
903 IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
904 #define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
905 IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
906 #define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
907 IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
909 #define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
910 IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
911 #define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
912 IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
913 #define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
914 IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
915 #define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
916 IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
917 #define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
918 IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
919 #define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
920 IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
921 #define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
922 IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
923 #define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
924 IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
926 #define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
927 IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
928 #define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
929 IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
930 #define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
931 IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
932 #define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
933 IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
934 #define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
935 IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
936 #define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
937 IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
938 #define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
939 IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
940 #define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
941 IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
943 #define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
944 IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
945 #define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
946 IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
947 #define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
948 IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
949 #define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
950 IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
951 #define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
952 IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
953 #define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
954 IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
955 #define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
956 IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
958 #define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
959 IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
960 #define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
961 IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
962 #define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
963 IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
964 #define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
965 IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
966 #define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
967 IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
968 #define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
969 IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
970 #define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
971 IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
973 #define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
974 IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
975 #define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
976 IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
977 #define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
978 IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
979 #define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
980 IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
981 #define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
982 IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
983 #define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
984 IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
985 #define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
986 IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
988 #define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
989 IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
990 #define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
991 IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
992 #define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
993 IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
994 #define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
995 IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
996 #define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
997 IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
998 #define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
999 IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
1000 #define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
1001 IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
1003 #define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
1004 IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
1005 #define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
1006 IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
1007 #define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
1008 IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
1009 #define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
1010 IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
1011 #define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
1012 IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
1013 #define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
1014 IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
1015 #define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
1016 IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
1017 #define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
1018 IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
1020 #define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
1021 IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
1022 #define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
1023 IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
1024 #define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
1025 IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
1026 #define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
1027 IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
1028 #define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
1029 IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
1030 #define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
1031 IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
1032 #define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
1033 IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
1034 #define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
1035 IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
1037 #define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
1038 IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
1039 #define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
1040 IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
1041 #define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
1042 IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
1043 #define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
1044 IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
1045 #define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
1046 IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
1047 #define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
1048 IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
1049 #define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
1050 IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
1051 #define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
1052 IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
1054 #define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
1055 IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
1056 #define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
1057 IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
1058 #define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
1059 IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
1060 #define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
1061 IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
1062 #define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
1063 IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
1064 #define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
1065 IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
1066 #define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
1067 IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
1068 #define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
1069 IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
1071 #define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
1072 IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
1073 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
1074 IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
1075 #define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
1076 IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
1077 #define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
1078 IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
1079 #define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
1080 IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
1081 #define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
1082 IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
1083 #define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
1084 IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
1086 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
1087 IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
1088 #define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
1089 IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
1090 #define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
1091 IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
1092 #define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
1093 IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
1094 #define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
1095 IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
1097 #define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
1098 IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
1099 #define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
1100 IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
1101 #define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
1102 IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
1103 #define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
1104 IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
1106 #define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
1107 IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
1108 #define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
1109 IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
1110 #define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
1111 IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
1112 #define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
1113 IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
1114 #define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
1115 IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
1116 #define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
1117 IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
1119 #define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
1120 IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
1121 #define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
1122 IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
1123 #define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
1124 IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
1125 #define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
1126 IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
1127 #define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
1128 IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
1129 #define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
1130 IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
1131 #define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
1132 IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
1134 #define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
1135 IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
1136 #define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
1137 IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
1138 #define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
1139 IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
1140 #define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
1141 IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
1142 #define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
1143 IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
1144 #define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
1145 IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
1146 #define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
1147 IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
1148 #define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
1149 IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
1151 #define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
1152 IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
1153 #define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
1154 IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
1155 #define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
1156 IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
1157 #define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
1158 IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
1159 #define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
1160 IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
1161 #define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
1162 IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
1163 #define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
1164 IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
1165 #define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
1166 IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
1168 #define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
1169 IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
1170 #define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
1171 IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
1172 #define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
1173 IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
1174 #define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
1175 IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
1176 #define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
1177 IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
1178 #define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
1179 IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
1180 #define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
1181 IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
1182 #define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
1183 IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
1185 #define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
1186 IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
1187 #define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
1188 IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
1189 #define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
1190 IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
1191 #define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
1192 IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
1193 #define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
1194 IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
1195 #define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
1196 IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
1197 #define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
1198 IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
1200 #define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
1201 IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
1202 #define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
1203 IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
1204 #define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
1205 IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
1206 #define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
1207 IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
1208 #define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
1209 IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
1210 #define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
1211 IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
1212 #define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
1213 IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
1214 #define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
1215 IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
1217 #define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
1218 IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
1219 #define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
1220 IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
1221 #define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
1222 IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
1223 #define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
1224 IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
1225 #define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
1226 IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
1227 #define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
1228 IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
1229 #define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
1230 IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
1231 #define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
1232 IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
1234 #define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
1235 IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
1236 #define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
1237 IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
1238 #define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
1239 IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
1240 #define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
1241 IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
1242 #define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
1243 IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
1244 #define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
1245 IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
1246 #define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
1247 IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
1248 #define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
1249 IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
1251 #define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
1252 IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
1253 #define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
1254 IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
1255 #define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
1256 IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
1257 #define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
1258 IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
1259 #define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
1260 IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
1261 #define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
1262 IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
1263 #define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
1264 IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
1265 #define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
1266 IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
1268 #define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
1269 IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
1270 #define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
1271 IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
1272 #define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
1273 IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
1274 #define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
1275 IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
1276 #define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
1277 IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
1278 #define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
1279 IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
1280 #define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
1281 IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
1282 #define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
1283 IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
1285 #define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
1286 IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
1287 #define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
1288 IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
1289 #define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
1290 IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
1291 #define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
1292 IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
1293 #define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
1294 IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
1295 #define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
1296 IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
1297 #define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
1298 IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
1299 #define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
1300 IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
1302 #define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
1303 IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
1304 #define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
1305 IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
1306 #define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
1307 IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
1308 #define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
1309 IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
1310 #define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
1311 IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
1312 #define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
1313 IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
1314 #define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
1315 IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
1316 #define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
1317 IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
1319 #define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
1320 IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
1321 #define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
1322 IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
1323 #define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
1324 IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
1325 #define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
1326 IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
1327 #define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
1328 IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
1329 #define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
1330 IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
1331 #define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
1332 IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
1333 #define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
1334 IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
1336 #define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
1337 IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
1338 #define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
1339 IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
1340 #define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
1341 IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
1342 #define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
1343 IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
1344 #define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
1345 IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
1346 #define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
1347 IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
1348 #define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
1349 IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
1350 #define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
1351 IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
1353 #define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
1354 IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
1355 #define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
1356 IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
1357 #define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
1358 IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
1359 #define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
1360 IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
1361 #define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
1362 IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
1363 #define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
1364 IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
1365 #define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
1366 IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
1368 #define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
1369 IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
1370 #define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
1371 IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
1372 #define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
1373 IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
1374 #define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
1375 IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
1376 #define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
1377 IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
1378 #define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
1379 IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
1380 #define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
1381 IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
1383 #define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
1384 IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
1385 #define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
1386 IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
1387 #define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
1388 IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
1389 #define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
1390 IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
1391 #define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
1392 IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
1393 #define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
1394 IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
1396 #define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
1397 IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
1398 #define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
1399 IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
1400 #define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
1401 IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
1402 #define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
1403 IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
1404 #define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
1405 IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
1406 #define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
1407 IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
1408 #define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
1409 IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
1411 #define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
1412 IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
1413 #define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
1414 IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
1415 #define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
1416 IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
1417 #define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
1418 IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
1419 #define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
1420 IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
1421 #define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
1422 IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
1424 #define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
1425 IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
1426 #define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
1427 IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
1428 #define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
1429 IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
1430 #define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
1431 IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
1432 #define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
1433 IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
1434 #define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
1435 IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
1436 #define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
1437 IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
1438 #define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
1439 IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
1441 #define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
1442 IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
1443 #define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
1444 IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
1445 #define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
1446 IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
1447 #define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
1448 IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
1449 #define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
1450 IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
1451 #define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
1452 IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
1453 #define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
1454 IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
1455 #define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
1456 IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
1458 #define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
1459 IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
1460 #define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
1461 IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
1462 #define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
1463 IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
1464 #define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
1465 IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
1466 #define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
1467 IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
1468 #define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
1469 IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
1470 #define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
1471 IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
1472 #define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
1473 IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
1475 #define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
1476 IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
1477 #define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
1478 IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
1479 #define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
1480 IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
1481 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
1482 IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
1483 #define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
1484 IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
1485 #define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
1486 IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
1487 #define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
1488 IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
1489 #define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
1490 IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
1492 #define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
1493 IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
1494 #define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
1495 IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
1496 #define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
1497 IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
1498 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
1499 IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
1500 #define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
1501 IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
1502 #define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
1503 IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
1504 #define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
1505 IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
1506 #define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
1507 IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
1509 #define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
1510 IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
1511 #define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
1512 IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
1513 #define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
1514 IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
1515 #define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
1516 IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
1517 #define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
1518 IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
1519 #define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
1520 IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
1521 #define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
1522 IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
1523 #define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
1524 IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
1526 #define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
1527 IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
1528 #define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
1529 IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
1530 #define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
1531 IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
1532 #define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
1533 IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
1534 #define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
1535 IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
1536 #define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
1537 IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
1538 #define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
1539 IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
1540 #define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
1541 IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
1543 #define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
1544 IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
1545 #define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
1546 IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
1547 #define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
1548 IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
1549 #define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
1550 IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
1551 #define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
1552 IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
1553 #define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
1554 IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
1555 #define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
1556 IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
1557 #define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
1558 IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
1560 #define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
1561 IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
1562 #define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
1563 IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
1564 #define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
1565 IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
1566 #define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
1567 IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
1568 #define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
1569 IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
1570 #define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
1571 IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
1572 #define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
1573 IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
1574 #define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
1575 IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
1577 #define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
1578 IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
1579 #define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
1580 IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
1581 #define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
1582 IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
1583 #define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
1584 IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
1585 #define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
1586 IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
1587 #define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
1588 IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
1590 #define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
1591 IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
1592 #define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
1593 IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
1594 #define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
1595 IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
1596 #define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
1597 IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
1598 #define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
1599 IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
1600 #define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
1601 IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
1603 #define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
1604 IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
1605 #define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
1606 IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
1607 #define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
1608 IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
1609 #define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
1610 IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
1611 #define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
1612 IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
1613 #define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
1614 IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
1615 #define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
1616 IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
1618 #define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
1619 IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
1620 #define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
1621 IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
1622 #define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
1623 IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
1624 #define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
1625 IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
1626 #define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
1627 IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
1628 #define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
1629 IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
1631 #define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
1632 IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
1633 #define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
1634 IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
1635 #define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
1636 IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
1637 #define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
1638 IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
1639 #define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
1640 IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
1641 #define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
1642 IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
1643 #define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
1644 IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
1646 #define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
1647 IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
1648 #define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
1649 IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
1650 #define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
1651 IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
1652 #define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
1653 IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
1654 #define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
1655 IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
1656 #define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
1657 IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
1658 #define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
1659 IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
1661 #define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
1662 IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
1663 #define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
1664 IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
1665 #define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
1666 IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
1667 #define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
1668 IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
1669 #define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
1670 IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
1672 #define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
1673 IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
1674 #define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
1675 IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
1676 #define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
1677 IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
1678 #define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
1679 IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
1680 #define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
1681 IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
1682 #define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
1683 IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
1684 #define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
1685 IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
1687 #define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
1688 IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
1689 #define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
1690 IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
1691 #define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
1692 IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
1693 #define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
1694 IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
1695 #define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
1696 IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
1698 #define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
1699 IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
1700 #define _MX6Q_PAD_ENET_MDC__ENET_MDC \
1701 IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
1702 #define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
1703 IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
1704 #define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
1705 IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
1706 #define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
1707 IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
1708 #define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
1709 IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
1710 #define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
1711 IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
1713 #define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
1714 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1716 #define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
1717 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1719 #define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
1720 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1722 #define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
1723 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1725 #define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
1726 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1728 #define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
1729 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1731 #define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
1732 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1734 #define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
1735 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1737 #define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
1738 IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
1740 #define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
1741 IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
1743 #define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
1744 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1746 #define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
1747 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1749 #define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
1750 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1752 #define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
1753 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1755 #define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
1756 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1758 #define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
1759 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1761 #define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
1762 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1764 #define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
1765 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1767 #define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
1768 IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
1770 #define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
1771 IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
1773 #define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
1774 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1776 #define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
1777 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1779 #define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
1780 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1782 #define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
1783 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1785 #define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
1786 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1788 #define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
1789 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1791 #define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
1792 IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
1794 #define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
1795 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1797 #define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
1798 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1800 #define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
1801 IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
1803 #define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
1804 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1806 #define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
1807 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1809 #define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
1810 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1812 #define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
1813 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1815 #define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
1816 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1818 #define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
1819 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1821 #define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
1822 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1824 #define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
1825 IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
1827 #define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
1828 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1830 #define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
1831 IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
1833 #define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
1834 IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
1836 #define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
1837 IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
1839 #define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
1840 IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
1842 #define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
1843 IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
1845 #define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
1846 IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
1848 #define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
1849 IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
1851 #define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
1852 IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
1854 #define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
1855 IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
1857 #define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
1858 IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
1860 #define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
1861 IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
1863 #define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
1864 IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
1866 #define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
1867 IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
1869 #define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
1870 IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
1872 #define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
1873 IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
1875 #define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
1876 IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
1878 #define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
1879 IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
1881 #define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
1882 IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
1884 #define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
1885 IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
1887 #define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
1888 IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
1890 #define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
1891 IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
1893 #define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
1894 IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
1896 #define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
1897 IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
1899 #define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
1900 IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
1902 #define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
1903 IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
1905 #define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
1906 IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
1908 #define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
1909 IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
1911 #define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
1912 IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
1914 #define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
1915 IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
1917 #define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
1918 IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
1920 #define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
1921 IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
1923 #define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
1924 IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
1926 #define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
1927 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1929 #define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
1930 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1932 #define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
1933 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1935 #define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
1936 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1938 #define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
1939 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1941 #define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
1942 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1944 #define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
1945 IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
1947 #define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
1948 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1950 #define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
1951 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1953 #define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
1954 IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
1956 #define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
1957 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1959 #define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
1960 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1962 #define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
1963 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1965 #define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
1966 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1968 #define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
1969 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1971 #define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
1972 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1974 #define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
1975 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1977 #define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
1978 IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
1980 #define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
1981 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1983 #define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
1984 IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
1986 #define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
1987 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1989 #define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
1990 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1992 #define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
1993 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1995 #define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
1996 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
1998 #define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
1999 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2001 #define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
2002 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2004 #define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
2005 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2007 #define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
2008 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2010 #define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
2011 IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
2013 #define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
2014 IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
2016 #define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
2017 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2019 #define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
2020 IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
2022 #define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
2023 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2025 #define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
2026 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2028 #define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
2029 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2031 #define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
2032 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2034 #define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
2035 IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
2037 #define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
2038 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2040 #define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
2041 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2043 #define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
2044 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2046 #define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
2047 IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
2048 #define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
2049 IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
2050 #define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
2051 IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
2052 #define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
2053 IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
2054 #define _MX6Q_PAD_KEY_COL0__UART4_TXD \
2055 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
2056 #define _MX6Q_PAD_KEY_COL0__UART4_RXD \
2057 IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
2058 #define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
2059 IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
2060 #define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
2061 IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
2062 #define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
2063 IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
2065 #define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
2066 IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
2067 #define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
2068 IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
2069 #define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
2070 IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
2071 #define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
2072 IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
2073 #define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
2074 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
2075 #define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
2076 IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
2077 #define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
2078 IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
2079 #define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
2080 IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
2081 #define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
2082 IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
2084 #define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
2085 IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
2086 #define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
2087 IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
2088 #define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
2089 IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
2090 #define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
2091 IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
2092 #define _MX6Q_PAD_KEY_COL1__UART5_TXD \
2093 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
2094 #define _MX6Q_PAD_KEY_COL1__UART5_RXD \
2095 IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
2096 #define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
2097 IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
2098 #define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
2099 IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
2100 #define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
2101 IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
2103 #define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
2104 IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
2105 #define _MX6Q_PAD_KEY_ROW1__ENET_COL \
2106 IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
2107 #define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
2108 IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
2109 #define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
2110 IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
2111 #define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
2112 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
2113 #define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
2114 IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
2115 #define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
2116 IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
2117 #define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
2118 IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
2119 #define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
2120 IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
2122 #define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
2123 IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
2124 #define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
2125 IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
2126 #define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
2127 IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
2128 #define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
2129 IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
2130 #define _MX6Q_PAD_KEY_COL2__ENET_MDC \
2131 IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
2132 #define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
2133 IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
2134 #define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
2135 IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
2136 #define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
2137 IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
2139 #define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
2140 IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
2141 #define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
2142 IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
2143 #define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
2144 IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
2145 #define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
2146 IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
2147 #define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
2148 IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
2149 #define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
2150 IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
2151 #define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
2152 IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
2153 #define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
2154 IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
2156 #define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
2157 IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
2158 #define _MX6Q_PAD_KEY_COL3__ENET_CRS \
2159 IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
2160 #define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
2161 IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
2162 #define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
2163 IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
2164 #define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
2165 IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
2166 #define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
2167 IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
2168 #define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
2169 IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
2170 #define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
2171 IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
2173 #define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
2174 IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
2175 #define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
2176 IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
2177 #define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
2178 IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
2179 #define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
2180 IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
2181 #define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
2182 IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
2183 #define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
2184 IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
2185 #define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
2186 IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
2187 #define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
2188 IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
2190 #define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
2191 IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
2192 #define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
2193 IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
2194 #define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
2195 IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
2196 #define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
2197 IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
2198 #define _MX6Q_PAD_KEY_COL4__UART5_CTS \
2199 IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
2200 #define _MX6Q_PAD_KEY_COL4__UART5_RTS \
2201 IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
2202 #define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
2203 IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
2204 #define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
2205 IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
2206 #define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
2207 IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
2209 #define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
2210 IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
2211 #define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
2212 IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
2213 #define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
2214 IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
2215 #define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
2216 IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
2217 #define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
2218 IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 1, 0)
2219 #define _MX6Q_PAD_KEY_ROW4__UART5_RTS \
2220 IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
2221 #define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
2222 IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
2223 #define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
2224 IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
2225 #define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
2226 IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
2228 #define _MX6Q_PAD_GPIO_0__CCM_CLKO \
2229 IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
2230 #define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
2231 IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
2232 #define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
2233 IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
2234 #define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
2235 IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
2236 #define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
2237 IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
2238 #define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
2239 IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
2240 #define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
2241 IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
2243 #define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
2244 IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
2245 #define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
2246 IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
2247 #define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
2248 IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
2249 #define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
2250 IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
2251 #define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
2252 IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
2253 #define _MX6Q_PAD_GPIO_1__USDHC1_CD \
2254 IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
2255 #define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
2256 IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
2258 #define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
2259 IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
2260 #define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
2261 IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
2262 #define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
2263 IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
2264 #define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
2265 IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
2266 #define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
2267 IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
2268 #define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
2269 IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
2270 #define _MX6Q_PAD_GPIO_9__USDHC1_WP \
2271 IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
2272 #define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
2273 IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
2275 #define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
2276 IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
2277 #define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
2278 IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
2279 #define _MX6Q_PAD_GPIO_3__I2C3_SCL \
2280 IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
2281 #define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
2282 IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
2283 #define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
2284 IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
2285 #define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
2286 IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
2287 #define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
2288 IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
2289 #define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
2290 IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
2292 #define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
2293 IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
2294 #define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
2295 IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
2296 #define _MX6Q_PAD_GPIO_6__I2C3_SDA \
2297 IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
2298 #define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
2299 IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
2300 #define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
2301 IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
2302 #define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
2303 IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
2304 #define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
2305 IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
2306 #define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
2307 IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
2309 #define _MX6Q_PAD_GPIO_2__ESAI1_FST \
2310 IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
2311 #define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
2312 IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
2313 #define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
2314 IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
2315 #define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
2316 IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
2317 #define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
2318 IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
2319 #define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
2320 IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
2321 #define _MX6Q_PAD_GPIO_2__USDHC2_WP \
2322 IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
2323 #define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
2324 IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
2326 #define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
2327 IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
2328 #define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
2329 IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
2330 #define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
2331 IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
2332 #define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
2333 IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
2334 #define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
2335 IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
2336 #define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
2337 IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
2338 #define _MX6Q_PAD_GPIO_4__USDHC2_CD \
2339 IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
2340 #define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
2341 IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
2343 #define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
2344 IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
2345 #define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
2346 IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
2347 #define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
2348 IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
2349 #define _MX6Q_PAD_GPIO_5__CCM_CLKO \
2350 IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
2351 #define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
2352 IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
2353 #define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
2354 IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
2355 #define _MX6Q_PAD_GPIO_5__I2C3_SCL \
2356 IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
2357 #define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
2358 IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
2360 #define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
2361 IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
2362 #define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
2363 IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
2364 #define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
2365 IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
2366 #define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
2367 IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
2368 #define _MX6Q_PAD_GPIO_7__UART2_TXD \
2369 IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
2370 #define _MX6Q_PAD_GPIO_7__UART2_RXD \
2371 IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
2372 #define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
2373 IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
2374 #define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
2375 IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
2376 #define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
2377 IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
2379 #define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
2380 IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
2381 #define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
2382 IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
2383 #define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
2384 IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
2385 #define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
2386 IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
2387 #define _MX6Q_PAD_GPIO_8__UART2_TXD \
2388 IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
2389 #define _MX6Q_PAD_GPIO_8__UART2_RXD \
2390 IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
2391 #define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
2392 IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
2393 #define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
2394 IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
2395 #define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
2396 IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
2398 #define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
2399 IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
2400 #define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
2401 IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
2402 #define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
2403 IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
2404 #define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
2405 IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
2406 #define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
2407 IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
2408 #define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
2409 IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
2410 #define _MX6Q_PAD_GPIO_16__I2C3_SDA \
2411 IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
2412 #define _MX6Q_PAD_GPIO_16__SJC_DE_B \
2413 IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
2415 #define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
2416 IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
2417 #define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
2418 IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
2419 #define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
2420 IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
2421 #define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
2422 IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
2423 #define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
2424 IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
2425 #define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
2426 IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
2427 #define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
2428 IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
2430 #define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
2431 IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
2432 #define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
2433 IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
2434 #define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
2435 IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
2436 #define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
2437 IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
2438 #define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
2439 IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
2440 #define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
2441 IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
2442 #define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
2443 IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
2444 #define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
2445 IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
2447 #define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
2448 IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
2449 #define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
2450 IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
2451 #define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
2452 IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
2453 #define _MX6Q_PAD_GPIO_19__CCM_CLKO \
2454 IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
2455 #define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
2456 IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
2457 #define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
2458 IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
2459 #define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
2460 IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
2461 #define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
2462 IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
2464 #define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
2465 IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
2466 #define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
2467 IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
2468 #define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
2469 IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
2470 #define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
2471 IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
2472 #define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
2473 IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
2474 #define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
2475 IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
2477 #define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
2478 IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
2479 #define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
2480 IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
2481 #define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
2482 IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
2483 #define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
2484 IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
2485 #define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
2486 IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
2487 #define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
2488 IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
2489 #define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
2490 IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
2492 #define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
2493 IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
2494 #define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
2495 IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
2496 #define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
2497 IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
2498 #define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
2499 IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
2500 #define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
2501 IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
2502 #define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
2503 IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
2504 #define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
2505 IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
2507 #define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
2508 IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
2509 #define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
2510 IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
2511 #define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
2512 IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
2513 #define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
2514 IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
2515 #define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
2516 IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
2517 #define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
2518 IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
2519 #define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
2520 IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
2522 #define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
2523 IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
2524 #define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
2525 IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
2526 #define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
2527 IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
2528 #define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
2529 IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
2530 #define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
2531 IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
2532 #define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
2533 IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
2534 #define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
2535 IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
2536 #define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
2537 IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
2539 #define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
2540 IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
2541 #define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
2542 IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
2543 #define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
2544 IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
2545 #define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
2546 IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
2547 #define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
2548 IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
2549 #define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
2550 IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
2551 #define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
2552 IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
2553 #define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
2554 IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
2556 #define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
2557 IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
2558 #define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
2559 IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
2560 #define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
2561 IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
2562 #define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
2563 IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
2564 #define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
2565 IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
2566 #define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
2567 IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
2568 #define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
2569 IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
2570 #define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
2571 IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
2573 #define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
2574 IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
2575 #define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
2576 IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
2577 #define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
2578 IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
2579 #define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
2580 IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
2581 #define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
2582 IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
2583 #define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
2584 IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
2585 #define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
2586 IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
2587 #define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
2588 IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
2590 #define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
2591 IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
2592 #define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
2593 IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
2594 #define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
2595 IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
2596 #define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
2597 IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
2598 #define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
2599 IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
2600 #define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
2601 IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
2602 #define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
2603 IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
2604 #define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
2605 IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
2607 #define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
2608 IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
2609 #define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
2610 IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
2611 #define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
2612 IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
2613 #define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
2614 IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
2615 #define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
2616 IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
2617 #define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
2618 IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
2619 #define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
2620 IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
2621 #define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
2622 IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
2624 #define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
2625 IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
2626 #define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
2627 IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
2628 #define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
2629 IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
2630 #define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
2631 IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
2632 #define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
2633 IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
2634 #define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
2635 IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
2636 #define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
2637 IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
2638 #define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
2639 IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
2640 #define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
2641 IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
2643 #define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
2644 IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
2645 #define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
2646 IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
2647 #define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
2648 IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
2649 #define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
2650 IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
2651 #define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
2652 IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
2653 #define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
2654 IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
2655 #define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
2656 IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
2657 #define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
2658 IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
2659 #define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
2660 IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
2662 #define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
2663 IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
2664 #define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
2665 IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
2666 #define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
2667 IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
2668 #define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
2669 IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
2670 #define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
2671 IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
2672 #define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
2673 IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
2674 #define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
2675 IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
2676 #define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
2677 IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
2678 #define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
2679 IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
2681 #define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
2682 IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
2683 #define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
2684 IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
2685 #define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
2686 IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
2687 #define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
2688 IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
2689 #define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
2690 IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
2691 #define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
2692 IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
2693 #define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
2694 IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
2695 #define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
2696 IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
2697 #define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
2698 IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
2700 #define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
2701 IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
2702 #define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
2703 IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
2704 #define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
2705 IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
2706 #define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
2707 IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
2708 #define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
2709 IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
2710 #define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
2711 IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
2712 #define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
2713 IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
2714 #define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
2715 IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
2716 #define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
2717 IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
2719 #define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
2720 IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
2721 #define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
2722 IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
2723 #define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
2724 IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
2725 #define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
2726 IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
2727 #define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
2728 IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
2729 #define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
2730 IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
2731 #define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
2732 IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
2733 #define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
2734 IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
2735 #define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
2736 IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
2738 #define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
2739 IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
2740 #define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
2741 IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
2742 #define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
2743 IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
2744 #define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
2745 IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
2746 #define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
2747 IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
2748 #define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
2749 IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
2750 #define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
2751 IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
2752 #define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
2753 IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
2754 #define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
2755 IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
2757 #define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
2758 IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
2759 #define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
2760 IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
2761 #define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
2762 IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
2763 #define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
2764 IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 1, 0)
2765 #define _MX6Q_PAD_CSI0_DAT17__UART4_RTS \
2766 IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
2767 #define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
2768 IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
2769 #define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
2770 IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
2771 #define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
2772 IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
2773 #define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
2774 IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
2776 #define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
2777 IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
2778 #define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
2779 IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
2780 #define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
2781 IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
2782 #define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
2783 IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
2784 #define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
2785 IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
2786 #define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
2787 IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
2788 #define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
2789 IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
2790 #define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
2791 IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
2792 #define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
2793 IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
2795 #define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
2796 IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
2797 #define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
2798 IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
2799 #define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
2800 IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
2801 #define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
2802 IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 3, 0)
2803 #define _MX6Q_PAD_CSI0_DAT19__UART5_RTS \
2804 IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
2805 #define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
2806 IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
2807 #define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
2808 IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
2809 #define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
2810 IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
2811 #define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
2812 IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
2814 #define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
2815 IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
2817 #define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
2818 IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
2820 #define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
2821 IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
2823 #define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
2824 IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
2826 #define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
2827 IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
2829 #define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
2830 IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
2832 #define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
2833 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2835 #define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
2836 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2838 #define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
2839 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2841 #define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
2842 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2844 #define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
2845 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2847 #define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
2848 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2850 #define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
2851 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2853 #define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
2854 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2856 #define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
2857 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2859 #define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
2860 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2862 #define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
2863 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2865 #define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
2866 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2868 #define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
2869 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2871 #define _MX6Q_PAD_POR_B__SRC_POR_B \
2872 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2874 #define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
2875 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2877 #define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
2878 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2880 #define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
2881 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2883 #define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
2884 IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
2886 #define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
2887 IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
2888 #define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
2889 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
2890 #define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
2891 IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
2892 #define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
2893 IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
2894 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
2895 IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
2896 #define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
2897 IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
2898 #define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
2899 IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
2900 #define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
2901 IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
2902 #define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
2903 IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
2905 #define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
2906 IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
2907 #define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
2908 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
2909 #define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
2910 IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
2911 #define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
2912 IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
2913 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
2914 IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
2915 #define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
2916 IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
2917 #define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
2918 IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
2919 #define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
2920 IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
2921 #define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
2922 IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
2924 #define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
2925 IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
2926 #define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
2927 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
2928 #define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
2929 IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
2930 #define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
2931 IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
2932 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
2933 IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
2934 #define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
2935 IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
2936 #define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
2937 IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
2938 #define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
2939 IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
2940 #define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
2941 IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
2943 #define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
2944 IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
2945 #define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
2946 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
2947 #define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
2948 IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
2949 #define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
2950 IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
2951 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
2952 IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
2953 #define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
2954 IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
2955 #define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
2956 IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
2957 #define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
2958 IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
2959 #define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
2960 IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
2962 #define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
2963 IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
2964 #define _MX6Q_PAD_SD3_CMD__UART2_CTS \
2965 IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 2, 0)
2966 #define _MX6Q_PAD_SD3_CMD__UART2_RTS \
2967 IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
2968 #define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
2969 IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
2970 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
2971 IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
2972 #define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
2973 IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
2974 #define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
2975 IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
2976 #define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
2977 IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
2978 #define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
2979 IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
2981 #define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
2982 IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
2983 #define _MX6Q_PAD_SD3_CLK__UART2_CTS \
2984 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
2985 #define _MX6Q_PAD_SD3_CLK__UART2_RTS \
2986 IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
2987 #define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
2988 IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
2989 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
2990 IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
2991 #define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
2992 IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
2993 #define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
2994 IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
2995 #define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
2996 IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
2997 #define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
2998 IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
3000 #define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
3001 IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
3002 #define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
3003 IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0)
3004 #define _MX6Q_PAD_SD3_DAT0__UART1_RTS \
3005 IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
3006 #define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
3007 IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
3008 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
3009 IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
3010 #define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
3011 IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
3012 #define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
3013 IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
3014 #define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
3015 IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
3016 #define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
3017 IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
3019 #define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
3020 IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
3021 #define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
3022 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
3023 #define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
3024 IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
3025 #define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
3026 IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
3027 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
3028 IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
3029 #define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
3030 IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
3031 #define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
3032 IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
3033 #define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
3034 IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
3035 #define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
3036 IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
3038 #define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
3039 IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
3040 #define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
3041 IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
3042 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
3043 IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
3044 #define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
3045 IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
3046 #define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
3047 IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
3048 #define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
3049 IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
3050 #define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
3051 IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
3053 #define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
3054 IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
3055 #define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
3056 IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 4, 0)
3057 #define _MX6Q_PAD_SD3_DAT3__UART3_RTS \
3058 IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
3059 #define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
3060 IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
3061 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
3062 IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
3063 #define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
3064 IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
3065 #define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
3066 IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
3067 #define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
3068 IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
3069 #define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
3070 IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
3072 #define _MX6Q_PAD_SD3_RST__USDHC3_RST \
3073 IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
3074 #define _MX6Q_PAD_SD3_RST__UART3_CTS \
3075 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
3076 #define _MX6Q_PAD_SD3_RST__UART3_RTS \
3077 IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
3078 #define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
3079 IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
3080 #define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
3081 IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
3082 #define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
3083 IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
3084 #define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
3085 IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
3086 #define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
3087 IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
3088 #define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
3089 IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
3091 #define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
3092 IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
3093 #define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
3094 IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
3095 #define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
3096 IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
3097 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
3098 IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
3099 #define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
3100 IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
3101 #define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
3102 IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
3103 #define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
3104 IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
3105 #define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
3106 IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
3108 #define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
3109 IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
3110 #define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
3111 IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
3112 #define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
3113 IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
3114 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
3115 IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
3116 #define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
3117 IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
3118 #define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
3119 IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
3120 #define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
3121 IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
3122 #define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
3123 IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
3125 #define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
3126 IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
3127 #define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
3128 IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
3129 #define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
3130 IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
3131 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
3132 IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
3133 #define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
3134 IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
3135 #define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
3136 IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
3137 #define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
3138 IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
3139 #define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
3140 IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
3142 #define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
3143 IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
3144 #define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
3145 IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
3146 #define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
3147 IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
3148 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
3149 IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
3150 #define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
3151 IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
3152 #define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
3153 IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
3154 #define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
3155 IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
3156 #define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
3157 IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
3159 #define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
3160 IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
3161 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
3162 IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
3163 #define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
3164 IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
3165 #define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
3166 IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
3167 #define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
3168 IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
3170 #define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
3171 IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
3172 #define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
3173 IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
3174 #define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
3175 IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
3176 #define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
3177 IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
3178 #define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
3179 IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
3180 #define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
3181 IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
3183 #define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
3184 IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
3185 #define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
3186 IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
3187 #define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
3188 IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
3189 #define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
3190 IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
3191 #define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
3192 IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
3193 #define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
3194 IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
3195 #define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
3196 IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
3198 #define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
3199 IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
3200 #define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
3201 IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
3202 #define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
3203 IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
3204 #define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
3205 IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
3206 #define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
3207 IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
3208 #define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
3209 IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
3210 #define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
3211 IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
3212 #define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
3213 IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
3215 #define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
3216 IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3217 #define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
3218 IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
3219 #define _MX6Q_PAD_SD4_CMD__UART3_TXD \
3220 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
3221 #define _MX6Q_PAD_SD4_CMD__UART3_RXD \
3222 IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
3223 #define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
3224 IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
3225 #define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
3226 IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
3227 #define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
3228 IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
3230 #define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
3231 IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
3232 #define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
3233 IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
3234 #define _MX6Q_PAD_SD4_CLK__UART3_TXD \
3235 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
3236 #define _MX6Q_PAD_SD4_CLK__UART3_RXD \
3237 IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
3238 #define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
3239 IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
3240 #define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
3241 IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
3243 #define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
3244 IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
3245 #define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
3246 IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
3247 #define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
3248 IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
3249 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
3250 IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
3251 #define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
3252 IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
3253 #define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
3254 IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
3255 #define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
3256 IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
3257 #define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
3258 IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
3260 #define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
3261 IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
3262 #define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
3263 IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
3264 #define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
3265 IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
3266 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
3267 IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
3268 #define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
3269 IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
3270 #define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
3271 IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
3272 #define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
3273 IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
3274 #define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
3275 IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
3277 #define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
3278 IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
3279 #define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
3280 IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
3281 #define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
3282 IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
3283 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
3284 IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
3285 #define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
3286 IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
3287 #define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
3288 IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
3289 #define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
3290 IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
3291 #define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
3292 IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
3294 #define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
3295 IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
3296 #define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
3297 IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
3298 #define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
3299 IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
3300 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
3301 IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
3302 #define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
3303 IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
3304 #define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
3305 IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
3306 #define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
3307 IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
3308 #define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
3309 IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
3311 #define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
3312 IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
3313 #define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
3314 IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
3315 #define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
3316 IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
3317 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
3318 IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
3319 #define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
3320 IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
3321 #define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
3322 IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
3323 #define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
3324 IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
3325 #define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
3326 IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
3328 #define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
3329 IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
3330 #define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
3331 IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
3332 #define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
3333 IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
3334 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
3335 IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
3336 #define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
3337 IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
3338 #define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
3339 IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
3340 #define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
3341 IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
3342 #define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
3343 IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
3345 #define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
3346 IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
3347 #define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
3348 IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
3349 #define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
3350 IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
3351 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
3352 IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
3353 #define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
3354 IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
3355 #define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
3356 IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
3357 #define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
3358 IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
3359 #define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
3360 IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
3362 #define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
3363 IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
3364 #define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
3365 IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
3366 #define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
3367 IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
3368 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
3369 IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
3370 #define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
3371 IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
3372 #define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
3373 IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
3374 #define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
3375 IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
3376 #define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
3377 IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
3379 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
3380 IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
3381 #define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
3382 IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
3383 #define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
3384 IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
3385 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
3386 IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
3387 #define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
3388 IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
3389 #define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
3390 IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
3391 #define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
3392 IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
3393 #define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
3394 IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
3396 #define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
3397 IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
3398 #define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
3399 IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
3400 #define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
3401 IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
3402 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
3403 IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
3404 #define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
3405 IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
3406 #define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
3407 IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
3408 #define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
3409 IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
3410 #define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
3411 IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
3413 #define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
3414 IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
3415 #define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
3416 IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
3417 #define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
3418 IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
3419 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
3420 IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
3421 #define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
3422 IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
3423 #define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
3424 IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
3425 #define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
3426 IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
3427 #define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
3428 IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
3430 #define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
3431 IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
3432 #define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
3433 IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
3434 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
3435 IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
3436 #define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
3437 IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
3438 #define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
3439 IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
3440 #define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
3441 IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
3442 #define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
3443 IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
3445 #define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
3446 IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
3447 #define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
3448 IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
3449 #define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
3450 IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
3451 #define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
3452 IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
3453 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
3454 IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
3455 #define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
3456 IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
3457 #define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
3458 IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
3459 #define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
3460 IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
3461 #define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
3462 IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
3464 #define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
3465 IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
3466 #define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
3467 IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
3468 #define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
3469 IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
3470 #define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
3471 IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
3472 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
3473 IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
3474 #define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
3475 IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
3476 #define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
3477 IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
3478 #define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
3479 IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
3480 #define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
3481 IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
3483 #define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
3484 IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
3485 #define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
3486 IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
3487 #define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
3488 IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 5, 0)
3489 #define _MX6Q_PAD_SD4_DAT6__UART2_RTS \
3490 IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
3491 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
3492 IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
3493 #define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
3494 IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
3495 #define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
3496 IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
3497 #define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
3498 IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
3499 #define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
3500 IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
3502 #define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
3503 IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
3504 #define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
3505 IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
3506 #define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
3507 IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
3508 #define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
3509 IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
3510 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
3511 IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
3512 #define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
3513 IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
3514 #define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
3515 IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
3516 #define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
3517 IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
3518 #define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
3519 IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
3521 #define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
3522 IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
3523 #define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
3524 IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
3525 #define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
3526 IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
3527 #define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
3528 IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
3529 #define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
3530 IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
3531 #define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
3532 IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
3533 #define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
3534 IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
3535 #define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
3536 IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
3538 #define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
3539 IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
3540 #define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
3541 IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
3542 #define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
3543 IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
3544 #define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
3545 IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
3546 #define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
3547 IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
3548 #define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
3549 IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
3550 #define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
3551 IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
3552 #define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
3553 IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
3555 #define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
3556 IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
3557 #define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
3558 IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
3559 #define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
3560 IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
3561 #define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
3562 IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
3563 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
3564 IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
3565 #define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
3566 IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
3567 #define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
3568 IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
3569 #define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
3570 IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
3572 #define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
3573 IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3574 #define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
3575 IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
3576 #define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
3577 IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
3578 #define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
3579 IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
3580 #define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
3581 IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
3582 #define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
3583 IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
3585 #define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
3586 IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
3587 #define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
3588 IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
3589 #define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
3590 IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
3591 #define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
3592 IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
3593 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
3594 IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
3595 #define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
3596 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
3597 #define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
3598 IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
3599 #define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
3600 IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
3602 #define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
3603 IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
3604 #define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
3605 IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
3606 #define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
3607 IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
3608 #define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
3609 IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
3610 #define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
3611 IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
3612 #define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
3613 IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
3614 #define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
3615 IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
3617 #define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
3618 IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
3619 #define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
3620 IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
3621 #define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
3622 IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
3623 #define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
3624 IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
3625 #define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
3626 IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
3627 #define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
3628 IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
3629 #define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
3630 IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
3631 #define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
3632 IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
3634 #define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
3635 IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
3636 #define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
3637 IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
3638 #define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
3639 IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
3640 #define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
3641 IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
3642 #define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
3643 IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
3644 #define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
3645 IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
3647 #define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
3648 IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
3649 #define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
3650 IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
3651 #define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
3652 IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
3653 #define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
3654 IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
3655 #define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
3656 IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
3657 #define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
3658 IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
3659 #define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
3660 IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
3661 #define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
3662 IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
3664 #define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3665 #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0)
3666 #define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2)
3667 #define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS)
3668 #define MX6Q_PAD_SD2_DAT1__KPP_COL_7 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7)
3669 #define MX6Q_PAD_SD2_DAT1__GPIO_1_14 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14)
3670 #define MX6Q_PAD_SD2_DAT1__CCM_WAIT (_MX6Q_PAD_SD2_DAT1__CCM_WAIT)
3671 #define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0)
3673 #define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3674 #define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1)
3675 #define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3)
3676 #define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD)
3677 #define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6)
3678 #define MX6Q_PAD_SD2_DAT2__GPIO_1_13 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13)
3679 #define MX6Q_PAD_SD2_DAT2__CCM_STOP (_MX6Q_PAD_SD2_DAT2__CCM_STOP)
3680 #define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1)
3682 #define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
3683 #define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO)
3684 #define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD)
3685 #define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7)
3686 #define MX6Q_PAD_SD2_DAT0__GPIO_1_15 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15)
3687 #define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT)
3688 #define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2)
3690 #define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA)
3691 #define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3692 #define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK)
3693 #define MX6Q_PAD_RGMII_TXC__GPIO_6_19 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19)
3694 #define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0)
3695 #define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT)
3697 #define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY)
3698 #define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3699 #define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20)
3700 #define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1)
3702 #define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG)
3703 #define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3704 #define MX6Q_PAD_RGMII_TD1__GPIO_6_21 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21)
3705 #define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2)
3706 #define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP)
3708 #define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA)
3709 #define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3710 #define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22)
3711 #define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3)
3712 #define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP)
3714 #define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE)
3715 #define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3716 #define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23)
3717 #define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4)
3719 #define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA)
3720 #define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3721 #define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24)
3722 #define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5)
3724 #define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY)
3725 #define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3726 #define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25)
3727 #define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6)
3729 #define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE)
3730 #define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3731 #define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26)
3732 #define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7)
3733 #define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT)
3735 #define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG)
3736 #define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3737 #define MX6Q_PAD_RGMII_RD1__GPIO_6_27 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27)
3738 #define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8)
3739 #define MX6Q_PAD_RGMII_RD1__SJC_FAIL (_MX6Q_PAD_RGMII_RD1__SJC_FAIL)
3741 #define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA)
3742 #define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3743 #define MX6Q_PAD_RGMII_RD2__GPIO_6_28 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28)
3744 #define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9)
3746 #define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE)
3747 #define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3748 #define MX6Q_PAD_RGMII_RD3__GPIO_6_29 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29)
3749 #define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10)
3751 #define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE)
3752 #define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
3753 #define MX6Q_PAD_RGMII_RXC__GPIO_6_30 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30)
3754 #define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11)
3756 #define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25)
3757 #define MX6Q_PAD_EIM_A25__ECSPI4_SS1 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1)
3758 #define MX6Q_PAD_EIM_A25__ECSPI2_RDY (_MX6Q_PAD_EIM_A25__ECSPI2_RDY)
3759 #define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12)
3760 #define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS)
3761 #define MX6Q_PAD_EIM_A25__GPIO_5_2 (_MX6Q_PAD_EIM_A25__GPIO_5_2)
3762 #define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE)
3763 #define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0)
3765 #define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2)
3766 #define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3767 #define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK)
3768 #define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19)
3769 #define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL)
3770 #define MX6Q_PAD_EIM_EB2__GPIO_2_30 (_MX6Q_PAD_EIM_EB2__GPIO_2_30)
3771 #define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3772 #define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30)
3774 #define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16)
3775 #define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3776 #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5)
3777 #define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18)
3778 #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA)
3779 #define MX6Q_PAD_EIM_D16__GPIO_3_16 (_MX6Q_PAD_EIM_D16__GPIO_3_16)
3780 #define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3782 #define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17)
3783 #define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3784 #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6)
3785 #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK)
3786 #define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT)
3787 #define MX6Q_PAD_EIM_D17__GPIO_3_17 (_MX6Q_PAD_EIM_D17__GPIO_3_17)
3788 #define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3789 #define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1)
3791 #define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18)
3792 #define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3793 #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7)
3794 #define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17)
3795 #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS)
3796 #define MX6Q_PAD_EIM_D18__GPIO_3_18 (_MX6Q_PAD_EIM_D18__GPIO_3_18)
3797 #define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3798 #define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2)
3800 #define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19)
3801 #define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
3802 #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8)
3803 #define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16)
3804 #define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3805 #define MX6Q_PAD_EIM_D19__GPIO_3_19 (_MX6Q_PAD_EIM_D19__GPIO_3_19)
3806 #define MX6Q_PAD_EIM_D19__EPIT1_EPITO (_MX6Q_PAD_EIM_D19__EPIT1_EPITO)
3807 #define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP)
3809 #define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20)
3810 #define MX6Q_PAD_EIM_D20__ECSPI4_SS0 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0)
3811 #define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16)
3812 #define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15)
3813 #define MX6Q_PAD_EIM_D20__UART1_CTS (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3814 #define MX6Q_PAD_EIM_D20__UART1_RTS (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3815 #define MX6Q_PAD_EIM_D20__GPIO_3_20 (_MX6Q_PAD_EIM_D20__GPIO_3_20)
3816 #define MX6Q_PAD_EIM_D20__EPIT2_EPITO (_MX6Q_PAD_EIM_D20__EPIT2_EPITO)
3818 #define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21)
3819 #define MX6Q_PAD_EIM_D21__ECSPI4_SCLK (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK)
3820 #define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17)
3821 #define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11)
3822 #define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC)
3823 #define MX6Q_PAD_EIM_D21__GPIO_3_21 (_MX6Q_PAD_EIM_D21__GPIO_3_21)
3824 #define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3825 #define MX6Q_PAD_EIM_D21__SPDIF_IN1 (_MX6Q_PAD_EIM_D21__SPDIF_IN1)
3827 #define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22)
3828 #define MX6Q_PAD_EIM_D22__ECSPI4_MISO (_MX6Q_PAD_EIM_D22__ECSPI4_MISO)
3829 #define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1)
3830 #define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10)
3831 #define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR)
3832 #define MX6Q_PAD_EIM_D22__GPIO_3_22 (_MX6Q_PAD_EIM_D22__GPIO_3_22)
3833 #define MX6Q_PAD_EIM_D22__SPDIF_OUT1 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1)
3834 #define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE)
3836 #define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23)
3837 #define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS)
3838 #define MX6Q_PAD_EIM_D23__UART3_CTS (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3839 #define MX6Q_PAD_EIM_D23__UART1_DCD (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3840 #define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN)
3841 #define MX6Q_PAD_EIM_D23__GPIO_3_23 (_MX6Q_PAD_EIM_D23__GPIO_3_23)
3842 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2)
3843 #define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14)
3845 #define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3)
3846 #define MX6Q_PAD_EIM_EB3__ECSPI4_RDY (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY)
3847 #define MX6Q_PAD_EIM_EB3__UART3_CTS (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3848 #define MX6Q_PAD_EIM_EB3__UART3_RTS (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3849 #define MX6Q_PAD_EIM_EB3__UART1_RI (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3850 #define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC)
3851 #define MX6Q_PAD_EIM_EB3__GPIO_2_31 (_MX6Q_PAD_EIM_EB3__GPIO_2_31)
3852 #define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3)
3853 #define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31)
3855 #define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24)
3856 #define MX6Q_PAD_EIM_D24__ECSPI4_SS2 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2)
3857 #define MX6Q_PAD_EIM_D24__UART3_TXD (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3858 #define MX6Q_PAD_EIM_D24__UART3_RXD (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3859 #define MX6Q_PAD_EIM_D24__ECSPI1_SS2 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2)
3860 #define MX6Q_PAD_EIM_D24__ECSPI2_SS2 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2)
3861 #define MX6Q_PAD_EIM_D24__GPIO_3_24 (_MX6Q_PAD_EIM_D24__GPIO_3_24)
3862 #define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS)
3863 #define MX6Q_PAD_EIM_D24__UART1_DTR (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3865 #define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25)
3866 #define MX6Q_PAD_EIM_D25__ECSPI4_SS3 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3)
3867 #define MX6Q_PAD_EIM_D25__UART3_TXD (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3868 #define MX6Q_PAD_EIM_D25__UART3_RXD (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3869 #define MX6Q_PAD_EIM_D25__ECSPI1_SS3 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3)
3870 #define MX6Q_PAD_EIM_D25__ECSPI2_SS3 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3)
3871 #define MX6Q_PAD_EIM_D25__GPIO_3_25 (_MX6Q_PAD_EIM_D25__GPIO_3_25)
3872 #define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC)
3873 #define MX6Q_PAD_EIM_D25__UART1_DSR (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3875 #define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26)
3876 #define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11)
3877 #define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1)
3878 #define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14)
3879 #define MX6Q_PAD_EIM_D26__UART2_TXD (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3880 #define MX6Q_PAD_EIM_D26__UART2_RXD (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3881 #define MX6Q_PAD_EIM_D26__GPIO_3_26 (_MX6Q_PAD_EIM_D26__GPIO_3_26)
3882 #define MX6Q_PAD_EIM_D26__IPU1_SISG_2 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2)
3883 #define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22)
3885 #define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27)
3886 #define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13)
3887 #define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0)
3888 #define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13)
3889 #define MX6Q_PAD_EIM_D27__UART2_TXD (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3890 #define MX6Q_PAD_EIM_D27__UART2_RXD (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3891 #define MX6Q_PAD_EIM_D27__GPIO_3_27 (_MX6Q_PAD_EIM_D27__GPIO_3_27)
3892 #define MX6Q_PAD_EIM_D27__IPU1_SISG_3 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3)
3893 #define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23)
3895 #define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28)
3896 #define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
3897 #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI)
3898 #define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12)
3899 #define MX6Q_PAD_EIM_D28__UART2_CTS (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3900 #define MX6Q_PAD_EIM_D28__GPIO_3_28 (_MX6Q_PAD_EIM_D28__GPIO_3_28)
3901 #define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG)
3902 #define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13)
3904 #define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29)
3905 #define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15)
3906 #define MX6Q_PAD_EIM_D29__ECSPI4_SS0 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0)
3907 #define MX6Q_PAD_EIM_D29__UART2_CTS (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3908 #define MX6Q_PAD_EIM_D29__UART2_RTS (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3909 #define MX6Q_PAD_EIM_D29__GPIO_3_29 (_MX6Q_PAD_EIM_D29__GPIO_3_29)
3910 #define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC)
3911 #define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14)
3913 #define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30)
3914 #define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21)
3915 #define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11)
3916 #define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3)
3917 #define MX6Q_PAD_EIM_D30__UART3_CTS (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3918 #define MX6Q_PAD_EIM_D30__GPIO_3_30 (_MX6Q_PAD_EIM_D30__GPIO_3_30)
3919 #define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC)
3920 #define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0)
3922 #define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31)
3923 #define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20)
3924 #define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12)
3925 #define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2)
3926 #define MX6Q_PAD_EIM_D31__UART3_CTS (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3927 #define MX6Q_PAD_EIM_D31__UART3_RTS (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
3928 #define MX6Q_PAD_EIM_D31__GPIO_3_31 (_MX6Q_PAD_EIM_D31__GPIO_3_31)
3929 #define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR)
3930 #define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1)
3932 #define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24)
3933 #define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19)
3934 #define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19)
3935 #define MX6Q_PAD_EIM_A24__IPU2_SISG_2 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2)
3936 #define MX6Q_PAD_EIM_A24__IPU1_SISG_2 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2)
3937 #define MX6Q_PAD_EIM_A24__GPIO_5_4 (_MX6Q_PAD_EIM_A24__GPIO_5_4)
3938 #define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2)
3939 #define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24)
3941 #define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23)
3942 #define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18)
3943 #define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18)
3944 #define MX6Q_PAD_EIM_A23__IPU2_SISG_3 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3)
3945 #define MX6Q_PAD_EIM_A23__IPU1_SISG_3 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3)
3946 #define MX6Q_PAD_EIM_A23__GPIO_6_6 (_MX6Q_PAD_EIM_A23__GPIO_6_6)
3947 #define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3)
3948 #define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23)
3950 #define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22)
3951 #define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17)
3952 #define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17)
3953 #define MX6Q_PAD_EIM_A22__GPIO_2_16 (_MX6Q_PAD_EIM_A22__GPIO_2_16)
3954 #define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0)
3955 #define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22)
3957 #define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21)
3958 #define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16)
3959 #define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16)
3960 #define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18)
3961 #define MX6Q_PAD_EIM_A21__GPIO_2_17 (_MX6Q_PAD_EIM_A21__GPIO_2_17)
3962 #define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1)
3963 #define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21)
3965 #define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20)
3966 #define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15)
3967 #define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15)
3968 #define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19)
3969 #define MX6Q_PAD_EIM_A20__GPIO_2_18 (_MX6Q_PAD_EIM_A20__GPIO_2_18)
3970 #define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2)
3971 #define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20)
3973 #define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19)
3974 #define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14)
3975 #define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14)
3976 #define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20)
3977 #define MX6Q_PAD_EIM_A19__GPIO_2_19 (_MX6Q_PAD_EIM_A19__GPIO_2_19)
3978 #define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3)
3979 #define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19)
3981 #define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18)
3982 #define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13)
3983 #define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13)
3984 #define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21)
3985 #define MX6Q_PAD_EIM_A18__GPIO_2_20 (_MX6Q_PAD_EIM_A18__GPIO_2_20)
3986 #define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4)
3987 #define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18)
3989 #define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17)
3990 #define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12)
3991 #define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12)
3992 #define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22)
3993 #define MX6Q_PAD_EIM_A17__GPIO_2_21 (_MX6Q_PAD_EIM_A17__GPIO_2_21)
3994 #define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5)
3995 #define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17)
3997 #define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16)
3998 #define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK)
3999 #define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK)
4000 #define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23)
4001 #define MX6Q_PAD_EIM_A16__GPIO_2_22 (_MX6Q_PAD_EIM_A16__GPIO_2_22)
4002 #define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6)
4003 #define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16)
4005 #define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0)
4006 #define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5)
4007 #define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK)
4008 #define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24)
4009 #define MX6Q_PAD_EIM_CS0__GPIO_2_23 (_MX6Q_PAD_EIM_CS0__GPIO_2_23)
4010 #define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7)
4012 #define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1)
4013 #define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6)
4014 #define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI)
4015 #define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25)
4016 #define MX6Q_PAD_EIM_CS1__GPIO_2_24 (_MX6Q_PAD_EIM_CS1__GPIO_2_24)
4017 #define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8)
4019 #define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE)
4020 #define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7)
4021 #define MX6Q_PAD_EIM_OE__ECSPI2_MISO (_MX6Q_PAD_EIM_OE__ECSPI2_MISO)
4022 #define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26)
4023 #define MX6Q_PAD_EIM_OE__GPIO_2_25 (_MX6Q_PAD_EIM_OE__GPIO_2_25)
4024 #define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9)
4026 #define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW)
4027 #define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8)
4028 #define MX6Q_PAD_EIM_RW__ECSPI2_SS0 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0)
4029 #define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27)
4030 #define MX6Q_PAD_EIM_RW__GPIO_2_26 (_MX6Q_PAD_EIM_RW__GPIO_2_26)
4031 #define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10)
4032 #define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29)
4034 #define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA)
4035 #define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17)
4036 #define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1)
4037 #define MX6Q_PAD_EIM_LBA__GPIO_2_27 (_MX6Q_PAD_EIM_LBA__GPIO_2_27)
4038 #define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11)
4039 #define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26)
4041 #define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0)
4042 #define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11)
4043 #define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11)
4044 #define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0)
4045 #define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY)
4046 #define MX6Q_PAD_EIM_EB0__GPIO_2_28 (_MX6Q_PAD_EIM_EB0__GPIO_2_28)
4047 #define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12)
4048 #define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27)
4050 #define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1)
4051 #define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10)
4052 #define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10)
4053 #define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1)
4054 #define MX6Q_PAD_EIM_EB1__GPIO_2_29 (_MX6Q_PAD_EIM_EB1__GPIO_2_29)
4055 #define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13)
4056 #define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28)
4058 #define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0)
4059 #define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9)
4060 #define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9)
4061 #define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2)
4062 #define MX6Q_PAD_EIM_DA0__GPIO_3_0 (_MX6Q_PAD_EIM_DA0__GPIO_3_0)
4063 #define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14)
4064 #define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0)
4066 #define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1)
4067 #define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8)
4068 #define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8)
4069 #define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3)
4070 #define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE)
4071 #define MX6Q_PAD_EIM_DA1__GPIO_3_1 (_MX6Q_PAD_EIM_DA1__GPIO_3_1)
4072 #define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15)
4073 #define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1)
4075 #define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2)
4076 #define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7)
4077 #define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7)
4078 #define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4)
4079 #define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE)
4080 #define MX6Q_PAD_EIM_DA2__GPIO_3_2 (_MX6Q_PAD_EIM_DA2__GPIO_3_2)
4081 #define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16)
4082 #define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2)
4084 #define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3)
4085 #define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6)
4086 #define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6)
4087 #define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5)
4088 #define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ)
4089 #define MX6Q_PAD_EIM_DA3__GPIO_3_3 (_MX6Q_PAD_EIM_DA3__GPIO_3_3)
4090 #define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17)
4091 #define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3)
4093 #define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4)
4094 #define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5)
4095 #define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5)
4096 #define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6)
4097 #define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN)
4098 #define MX6Q_PAD_EIM_DA4__GPIO_3_4 (_MX6Q_PAD_EIM_DA4__GPIO_3_4)
4099 #define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18)
4100 #define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4)
4102 #define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5)
4103 #define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4)
4104 #define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4)
4105 #define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7)
4106 #define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP)
4107 #define MX6Q_PAD_EIM_DA5__GPIO_3_5 (_MX6Q_PAD_EIM_DA5__GPIO_3_5)
4108 #define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19)
4109 #define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5)
4111 #define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6)
4112 #define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3)
4113 #define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3)
4114 #define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8)
4115 #define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN)
4116 #define MX6Q_PAD_EIM_DA6__GPIO_3_6 (_MX6Q_PAD_EIM_DA6__GPIO_3_6)
4117 #define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20)
4118 #define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6)
4120 #define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7)
4121 #define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2)
4122 #define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2)
4123 #define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9)
4124 #define MX6Q_PAD_EIM_DA7__GPIO_3_7 (_MX6Q_PAD_EIM_DA7__GPIO_3_7)
4125 #define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21)
4126 #define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7)
4128 #define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8)
4129 #define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1)
4130 #define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1)
4131 #define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10)
4132 #define MX6Q_PAD_EIM_DA8__GPIO_3_8 (_MX6Q_PAD_EIM_DA8__GPIO_3_8)
4133 #define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22)
4134 #define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8)
4136 #define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9)
4137 #define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0)
4138 #define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0)
4139 #define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11)
4140 #define MX6Q_PAD_EIM_DA9__GPIO_3_9 (_MX6Q_PAD_EIM_DA9__GPIO_3_9)
4141 #define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23)
4142 #define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9)
4144 #define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10)
4145 #define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15)
4146 #define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN)
4147 #define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12)
4148 #define MX6Q_PAD_EIM_DA10__GPIO_3_10 (_MX6Q_PAD_EIM_DA10__GPIO_3_10)
4149 #define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24)
4150 #define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10)
4152 #define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11)
4153 #define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2)
4154 #define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC)
4155 #define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13)
4156 #define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6)
4157 #define MX6Q_PAD_EIM_DA11__GPIO_3_11 (_MX6Q_PAD_EIM_DA11__GPIO_3_11)
4158 #define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25)
4159 #define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11)
4161 #define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12)
4162 #define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3)
4163 #define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC)
4164 #define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14)
4165 #define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3)
4166 #define MX6Q_PAD_EIM_DA12__GPIO_3_12 (_MX6Q_PAD_EIM_DA12__GPIO_3_12)
4167 #define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26)
4168 #define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12)
4170 #define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13)
4171 #define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS)
4172 #define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK)
4173 #define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15)
4174 #define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4)
4175 #define MX6Q_PAD_EIM_DA13__GPIO_3_13 (_MX6Q_PAD_EIM_DA13__GPIO_3_13)
4176 #define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27)
4177 #define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13)
4179 #define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14)
4180 #define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS)
4181 #define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK)
4182 #define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16)
4183 #define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5)
4184 #define MX6Q_PAD_EIM_DA14__GPIO_3_14 (_MX6Q_PAD_EIM_DA14__GPIO_3_14)
4185 #define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28)
4186 #define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14)
4188 #define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15)
4189 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1)
4190 #define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4)
4191 #define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17)
4192 #define MX6Q_PAD_EIM_DA15__GPIO_3_15 (_MX6Q_PAD_EIM_DA15__GPIO_3_15)
4193 #define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29)
4194 #define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15)
4196 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT)
4197 #define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B)
4198 #define MX6Q_PAD_EIM_WAIT__GPIO_5_0 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0)
4199 #define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30)
4200 #define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25)
4202 #define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK)
4203 #define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16)
4204 #define MX6Q_PAD_EIM_BCLK__GPIO_6_31 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31)
4205 #define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31)
4207 #define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK)
4208 #define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK)
4209 #define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28)
4210 #define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0)
4211 #define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16)
4212 #define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0)
4214 #define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15)
4215 #define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15)
4216 #define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC)
4217 #define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29)
4218 #define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1)
4219 #define MX6Q_PAD_DI0_PIN15__GPIO_4_17 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17)
4220 #define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1)
4222 #define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2)
4223 #define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2)
4224 #define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD)
4225 #define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30)
4226 #define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2)
4227 #define MX6Q_PAD_DI0_PIN2__GPIO_4_18 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18)
4228 #define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2)
4229 #define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9)
4231 #define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3)
4232 #define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3)
4233 #define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS)
4234 #define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31)
4235 #define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3)
4236 #define MX6Q_PAD_DI0_PIN3__GPIO_4_19 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19)
4237 #define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3)
4238 #define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10)
4240 #define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4)
4241 #define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4)
4242 #define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD)
4243 #define MX6Q_PAD_DI0_PIN4__USDHC1_WP (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4244 #define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD)
4245 #define MX6Q_PAD_DI0_PIN4__GPIO_4_20 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20)
4246 #define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4)
4247 #define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11)
4249 #define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0)
4250 #define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0)
4251 #define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK)
4252 #define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4253 #define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN)
4254 #define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21)
4255 #define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5)
4257 #define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1)
4258 #define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1)
4259 #define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI)
4260 #define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4261 #define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL)
4262 #define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22)
4263 #define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6)
4264 #define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12)
4266 #define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2)
4267 #define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2)
4268 #define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO)
4269 #define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4270 #define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE)
4271 #define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23)
4272 #define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7)
4273 #define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13)
4275 #define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3)
4276 #define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3)
4277 #define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0)
4278 #define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4279 #define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR)
4280 #define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24)
4281 #define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8)
4282 #define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14)
4284 #define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4)
4285 #define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4)
4286 #define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1)
4287 #define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4288 #define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB)
4289 #define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25)
4290 #define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9)
4291 #define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15)
4293 #define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5)
4294 #define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5)
4295 #define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2)
4296 #define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS)
4297 #define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS)
4298 #define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26)
4299 #define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10)
4300 #define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16)
4302 #define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6)
4303 #define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6)
4304 #define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3)
4305 #define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC)
4306 #define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE)
4307 #define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27)
4308 #define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11)
4309 #define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17)
4311 #define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7)
4312 #define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7)
4313 #define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY)
4314 #define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4315 #define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0)
4316 #define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28)
4317 #define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12)
4318 #define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18)
4320 #define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8)
4321 #define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8)
4322 #define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO)
4323 #define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B)
4324 #define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1)
4325 #define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29)
4326 #define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13)
4327 #define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19)
4329 #define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9)
4330 #define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9)
4331 #define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO)
4332 #define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B)
4333 #define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2)
4334 #define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30)
4335 #define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14)
4336 #define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20)
4338 #define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10)
4339 #define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10)
4340 #define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4341 #define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3)
4342 #define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31)
4343 #define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15)
4344 #define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21)
4346 #define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11)
4347 #define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11)
4348 #define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4349 #define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4)
4350 #define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5)
4351 #define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16)
4352 #define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22)
4354 #define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12)
4355 #define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12)
4356 #define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5)
4357 #define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6)
4358 #define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17)
4359 #define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23)
4361 #define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13)
4362 #define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13)
4363 #define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS)
4364 #define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0)
4365 #define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7)
4366 #define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18)
4367 #define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24)
4369 #define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14)
4370 #define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14)
4371 #define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC)
4372 #define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1)
4373 #define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8)
4374 #define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19)
4376 #define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15)
4377 #define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15)
4378 #define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1)
4379 #define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1)
4380 #define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2)
4381 #define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9)
4382 #define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20)
4383 #define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25)
4385 #define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16)
4386 #define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16)
4387 #define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI)
4388 #define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC)
4389 #define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0)
4390 #define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10)
4391 #define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21)
4392 #define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26)
4394 #define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17)
4395 #define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17)
4396 #define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO)
4397 #define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD)
4398 #define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1)
4399 #define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11)
4400 #define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22)
4401 #define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27)
4403 #define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18)
4404 #define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18)
4405 #define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0)
4406 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS)
4407 #define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS)
4408 #define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12)
4409 #define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23)
4410 #define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2)
4412 #define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19)
4413 #define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19)
4414 #define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK)
4415 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD)
4416 #define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC)
4417 #define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13)
4418 #define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24)
4419 #define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3)
4421 #define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20)
4422 #define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20)
4423 #define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK)
4424 #define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC)
4425 #define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7)
4426 #define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14)
4427 #define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25)
4428 #define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28)
4430 #define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21)
4431 #define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21)
4432 #define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI)
4433 #define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD)
4434 #define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0)
4435 #define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15)
4436 #define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26)
4437 #define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29)
4439 #define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22)
4440 #define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22)
4441 #define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO)
4442 #define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS)
4443 #define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1)
4444 #define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16)
4445 #define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27)
4446 #define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30)
4448 #define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23)
4449 #define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23)
4450 #define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0)
4451 #define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD)
4452 #define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2)
4453 #define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17)
4454 #define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28)
4455 #define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31)
4457 #define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4458 #define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR)
4459 #define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3)
4460 #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT)
4461 #define MX6Q_PAD_ENET_MDIO__GPIO_1_22 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22)
4462 #define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK)
4464 #define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4465 #define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR)
4466 #define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4)
4467 #define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23)
4468 #define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK)
4469 #define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH)
4471 #define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4472 #define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR)
4473 #define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1)
4474 #define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT)
4475 #define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24)
4476 #define MX6Q_PAD_ENET_RX_ER__PHY_TDI (_MX6Q_PAD_ENET_RX_ER__PHY_TDI)
4477 #define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD)
4479 #define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4480 #define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT)
4481 #define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK)
4482 #define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25)
4483 #define MX6Q_PAD_ENET_CRS_DV__PHY_TDO (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO)
4484 #define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD)
4486 #define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG)
4487 #define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4488 #define MX6Q_PAD_ENET_RXD1__ESAI1_FST (_MX6Q_PAD_ENET_RXD1__ESAI1_FST)
4489 #define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT)
4490 #define MX6Q_PAD_ENET_RXD1__GPIO_1_26 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26)
4491 #define MX6Q_PAD_ENET_RXD1__PHY_TCK (_MX6Q_PAD_ENET_RXD1__PHY_TCK)
4492 #define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET)
4494 #define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT)
4495 #define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4496 #define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT)
4497 #define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1)
4498 #define MX6Q_PAD_ENET_RXD0__GPIO_1_27 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27)
4499 #define MX6Q_PAD_ENET_RXD0__PHY_TMS (_MX6Q_PAD_ENET_RXD0__PHY_TMS)
4500 #define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV)
4502 #define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4503 #define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2)
4504 #define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28)
4505 #define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI)
4506 #define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH)
4508 #define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK)
4509 #define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4510 #define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3)
4511 #define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN)
4512 #define MX6Q_PAD_ENET_TXD1__GPIO_1_29 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29)
4513 #define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO)
4514 #define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD)
4516 #define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4517 #define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1)
4518 #define MX6Q_PAD_ENET_TXD0__GPIO_1_30 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30)
4519 #define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK)
4520 #define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD)
4522 #define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT)
4523 #define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4524 #define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0)
4525 #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN)
4526 #define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31)
4527 #define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS)
4528 #define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET)
4530 #define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40)
4531 #define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41)
4532 #define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42)
4533 #define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43)
4534 #define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44)
4535 #define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45)
4536 #define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46)
4537 #define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47)
4539 #define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5)
4540 #define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5)
4542 #define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32)
4543 #define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33)
4544 #define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34)
4545 #define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35)
4546 #define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36)
4547 #define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37)
4548 #define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38)
4549 #define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39)
4550 #define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4)
4551 #define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4)
4552 #define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24)
4553 #define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25)
4554 #define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26)
4555 #define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27)
4556 #define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28)
4557 #define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29)
4558 #define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3)
4559 #define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30)
4560 #define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31)
4561 #define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3)
4562 #define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16)
4563 #define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17)
4564 #define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18)
4565 #define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19)
4566 #define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20)
4567 #define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21)
4568 #define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22)
4569 #define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2)
4570 #define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23)
4571 #define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2)
4572 #define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0)
4573 #define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1)
4574 #define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2)
4575 #define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3)
4576 #define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4)
4577 #define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5)
4578 #define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6)
4579 #define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7)
4580 #define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8)
4581 #define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9)
4582 #define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10)
4583 #define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11)
4584 #define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12)
4585 #define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13)
4586 #define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14)
4587 #define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15)
4588 #define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS)
4589 #define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0)
4590 #define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1)
4591 #define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS)
4592 #define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET)
4593 #define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0)
4594 #define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1)
4595 #define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0)
4596 #define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2)
4597 #define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0)
4598 #define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1)
4599 #define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1)
4600 #define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0)
4601 #define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1)
4602 #define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE)
4603 #define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0)
4604 #define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1)
4605 #define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2)
4606 #define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3)
4607 #define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4)
4608 #define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5)
4609 #define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0)
4610 #define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6)
4611 #define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7)
4612 #define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0)
4613 #define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8)
4614 #define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9)
4615 #define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10)
4616 #define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11)
4617 #define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12)
4618 #define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13)
4619 #define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14)
4620 #define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1)
4621 #define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15)
4622 #define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1)
4623 #define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48)
4624 #define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49)
4625 #define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50)
4626 #define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51)
4627 #define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52)
4628 #define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53)
4629 #define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54)
4630 #define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55)
4631 #define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6)
4632 #define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6)
4633 #define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56)
4634 #define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7)
4635 #define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57)
4636 #define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58)
4637 #define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59)
4638 #define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60)
4639 #define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7)
4640 #define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61)
4641 #define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62)
4642 #define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63)
4644 #define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK)
4645 #define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4646 #define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC)
4647 #define MX6Q_PAD_KEY_COL0__KPP_COL_0 (_MX6Q_PAD_KEY_COL0__KPP_COL_0)
4648 #define MX6Q_PAD_KEY_COL0__UART4_TXD (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4649 #define MX6Q_PAD_KEY_COL0__UART4_RXD (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4650 #define MX6Q_PAD_KEY_COL0__GPIO_4_6 (_MX6Q_PAD_KEY_COL0__GPIO_4_6)
4651 #define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT)
4652 #define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST)
4654 #define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI)
4655 #define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4656 #define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD)
4657 #define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0)
4658 #define MX6Q_PAD_KEY_ROW0__UART4_TXD (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4659 #define MX6Q_PAD_KEY_ROW0__UART4_RXD (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4660 #define MX6Q_PAD_KEY_ROW0__GPIO_4_7 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7)
4661 #define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT)
4662 #define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0)
4664 #define MX6Q_PAD_KEY_COL1__ECSPI1_MISO (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO)
4665 #define MX6Q_PAD_KEY_COL1__ENET_MDIO (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4666 #define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS)
4667 #define MX6Q_PAD_KEY_COL1__KPP_COL_1 (_MX6Q_PAD_KEY_COL1__KPP_COL_1)
4668 #define MX6Q_PAD_KEY_COL1__UART5_TXD (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4669 #define MX6Q_PAD_KEY_COL1__UART5_RXD (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4670 #define MX6Q_PAD_KEY_COL1__GPIO_4_8 (_MX6Q_PAD_KEY_COL1__GPIO_4_8)
4671 #define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4672 #define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1)
4674 #define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0)
4675 #define MX6Q_PAD_KEY_ROW1__ENET_COL (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4676 #define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD)
4677 #define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1)
4678 #define MX6Q_PAD_KEY_ROW1__UART5_TXD (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4679 #define MX6Q_PAD_KEY_ROW1__UART5_RXD (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4680 #define MX6Q_PAD_KEY_ROW1__GPIO_4_9 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9)
4681 #define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4682 #define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2)
4684 #define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1)
4685 #define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4686 #define MX6Q_PAD_KEY_COL2__CAN1_TXCAN (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN)
4687 #define MX6Q_PAD_KEY_COL2__KPP_COL_2 (_MX6Q_PAD_KEY_COL2__KPP_COL_2)
4688 #define MX6Q_PAD_KEY_COL2__ENET_MDC (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4689 #define MX6Q_PAD_KEY_COL2__GPIO_4_10 (_MX6Q_PAD_KEY_COL2__GPIO_4_10)
4690 #define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP)
4691 #define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3)
4693 #define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2)
4694 #define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4695 #define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN)
4696 #define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2)
4697 #define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4698 #define MX6Q_PAD_KEY_ROW2__GPIO_4_11 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11)
4699 #define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE)
4700 #define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4)
4702 #define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3)
4703 #define MX6Q_PAD_KEY_COL3__ENET_CRS (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4704 #define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL)
4705 #define MX6Q_PAD_KEY_COL3__KPP_COL_3 (_MX6Q_PAD_KEY_COL3__KPP_COL_3)
4706 #define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4707 #define MX6Q_PAD_KEY_COL3__GPIO_4_12 (_MX6Q_PAD_KEY_COL3__GPIO_4_12)
4708 #define MX6Q_PAD_KEY_COL3__SPDIF_IN1 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1)
4709 #define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5)
4711 #define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT)
4712 #define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK)
4713 #define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA)
4714 #define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3)
4715 #define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4716 #define MX6Q_PAD_KEY_ROW3__GPIO_4_13 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13)
4717 #define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4718 #define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6)
4720 #define MX6Q_PAD_KEY_COL4__CAN2_TXCAN (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN)
4721 #define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4)
4722 #define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC)
4723 #define MX6Q_PAD_KEY_COL4__KPP_COL_4 (_MX6Q_PAD_KEY_COL4__KPP_COL_4)
4724 #define MX6Q_PAD_KEY_COL4__UART5_CTS (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4725 #define MX6Q_PAD_KEY_COL4__UART5_RTS (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4726 #define MX6Q_PAD_KEY_COL4__GPIO_4_14 (_MX6Q_PAD_KEY_COL4__GPIO_4_14)
4727 #define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49)
4728 #define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7)
4730 #define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN)
4731 #define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5)
4732 #define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR)
4733 #define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4)
4734 #define MX6Q_PAD_KEY_ROW4__UART5_CTS (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4735 #define MX6Q_PAD_KEY_ROW4__GPIO_4_15 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15)
4736 #define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50)
4737 #define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8)
4739 #define MX6Q_PAD_GPIO_0__CCM_CLKO (_MX6Q_PAD_GPIO_0__CCM_CLKO)
4740 #define MX6Q_PAD_GPIO_0__KPP_COL_5 (_MX6Q_PAD_GPIO_0__KPP_COL_5)
4741 #define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK)
4742 #define MX6Q_PAD_GPIO_0__EPIT1_EPITO (_MX6Q_PAD_GPIO_0__EPIT1_EPITO)
4743 #define MX6Q_PAD_GPIO_0__GPIO_1_0 (_MX6Q_PAD_GPIO_0__GPIO_1_0)
4744 #define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR)
4745 #define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5)
4747 #define MX6Q_PAD_GPIO_1__ESAI1_SCKR (_MX6Q_PAD_GPIO_1__ESAI1_SCKR)
4748 #define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B)
4749 #define MX6Q_PAD_GPIO_1__KPP_ROW_5 (_MX6Q_PAD_GPIO_1__KPP_ROW_5)
4750 #define MX6Q_PAD_GPIO_1__PWM2_PWMO (_MX6Q_PAD_GPIO_1__PWM2_PWMO)
4751 #define MX6Q_PAD_GPIO_1__GPIO_1_1 (_MX6Q_PAD_GPIO_1__GPIO_1_1)
4752 #define MX6Q_PAD_GPIO_1__USDHC1_CD (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4753 #define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK)
4755 #define MX6Q_PAD_GPIO_9__ESAI1_FSR (_MX6Q_PAD_GPIO_9__ESAI1_FSR)
4756 #define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B)
4757 #define MX6Q_PAD_GPIO_9__KPP_COL_6 (_MX6Q_PAD_GPIO_9__KPP_COL_6)
4758 #define MX6Q_PAD_GPIO_9__CCM_REF_EN_B (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B)
4759 #define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL))
4760 #define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
4761 #define MX6Q_PAD_GPIO_9__USDHC1_WP (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4762 #define MX6Q_PAD_GPIO_9__SRC_EARLY_RST (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST)
4764 #define MX6Q_PAD_GPIO_3__ESAI1_HCKR (_MX6Q_PAD_GPIO_3__ESAI1_HCKR)
4765 #define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0)
4766 #define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4767 #define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT)
4768 #define MX6Q_PAD_GPIO_3__CCM_CLKO2 (_MX6Q_PAD_GPIO_3__CCM_CLKO2)
4769 #define MX6Q_PAD_GPIO_3__GPIO_1_3 (_MX6Q_PAD_GPIO_3__GPIO_1_3)
4770 #define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC)
4771 #define MX6Q_PAD_GPIO_3__MLB_MLBCLK (_MX6Q_PAD_GPIO_3__MLB_MLBCLK)
4773 #define MX6Q_PAD_GPIO_6__ESAI1_SCKT (_MX6Q_PAD_GPIO_6__ESAI1_SCKT)
4774 #define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1)
4775 #define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4776 #define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0)
4777 #define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB)
4778 #define MX6Q_PAD_GPIO_6__GPIO_1_6 (_MX6Q_PAD_GPIO_6__GPIO_1_6)
4779 #define MX6Q_PAD_GPIO_6__USDHC2_LCTL (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4780 #define MX6Q_PAD_GPIO_6__MLB_MLBSIG (_MX6Q_PAD_GPIO_6__MLB_MLBSIG)
4782 #define MX6Q_PAD_GPIO_2__ESAI1_FST (_MX6Q_PAD_GPIO_2__ESAI1_FST)
4783 #define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2)
4784 #define MX6Q_PAD_GPIO_2__KPP_ROW_6 (_MX6Q_PAD_GPIO_2__KPP_ROW_6)
4785 #define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1)
4786 #define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0)
4787 #define MX6Q_PAD_GPIO_2__GPIO_1_2 (_MX6Q_PAD_GPIO_2__GPIO_1_2)
4788 #define MX6Q_PAD_GPIO_2__USDHC2_WP (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4789 #define MX6Q_PAD_GPIO_2__MLB_MLBDAT (_MX6Q_PAD_GPIO_2__MLB_MLBDAT)
4791 #define MX6Q_PAD_GPIO_4__ESAI1_HCKT (_MX6Q_PAD_GPIO_4__ESAI1_HCKT)
4792 #define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3)
4793 #define MX6Q_PAD_GPIO_4__KPP_COL_7 (_MX6Q_PAD_GPIO_4__KPP_COL_7)
4794 #define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2)
4795 #define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1)
4796 #define MX6Q_PAD_GPIO_4__GPIO_1_4 (_MX6Q_PAD_GPIO_4__GPIO_1_4)
4797 #define MX6Q_PAD_GPIO_4__USDHC2_CD (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4798 #define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED)
4800 #define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3)
4801 #define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4)
4802 #define MX6Q_PAD_GPIO_5__KPP_ROW_7 (_MX6Q_PAD_GPIO_5__KPP_ROW_7)
4803 #define MX6Q_PAD_GPIO_5__CCM_CLKO (_MX6Q_PAD_GPIO_5__CCM_CLKO)
4804 #define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2)
4805 #define MX6Q_PAD_GPIO_5__GPIO_1_5 (_MX6Q_PAD_GPIO_5__GPIO_1_5)
4806 #define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4807 #define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI)
4809 #define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1)
4810 #define MX6Q_PAD_GPIO_7__ECSPI5_RDY (_MX6Q_PAD_GPIO_7__ECSPI5_RDY)
4811 #define MX6Q_PAD_GPIO_7__EPIT1_EPITO (_MX6Q_PAD_GPIO_7__EPIT1_EPITO)
4812 #define MX6Q_PAD_GPIO_7__CAN1_TXCAN (_MX6Q_PAD_GPIO_7__CAN1_TXCAN)
4813 #define MX6Q_PAD_GPIO_7__UART2_TXD (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4814 #define MX6Q_PAD_GPIO_7__UART2_RXD (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4815 #define MX6Q_PAD_GPIO_7__GPIO_1_7 (_MX6Q_PAD_GPIO_7__GPIO_1_7)
4816 #define MX6Q_PAD_GPIO_7__SPDIF_PLOCK (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK)
4817 #define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE)
4819 #define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0)
4820 #define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT)
4821 #define MX6Q_PAD_GPIO_8__EPIT2_EPITO (_MX6Q_PAD_GPIO_8__EPIT2_EPITO)
4822 #define MX6Q_PAD_GPIO_8__CAN1_RXCAN (_MX6Q_PAD_GPIO_8__CAN1_RXCAN)
4823 #define MX6Q_PAD_GPIO_8__UART2_TXD (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4824 #define MX6Q_PAD_GPIO_8__UART2_RXD (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4825 #define MX6Q_PAD_GPIO_8__GPIO_1_8 (_MX6Q_PAD_GPIO_8__GPIO_1_8)
4826 #define MX6Q_PAD_GPIO_8__SPDIF_SRCLK (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK)
4827 #define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP)
4829 #define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2)
4830 #define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN)
4831 #define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT)
4832 #define MX6Q_PAD_GPIO_16__USDHC1_LCTL (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4833 #define MX6Q_PAD_GPIO_16__SPDIF_IN1 (_MX6Q_PAD_GPIO_16__SPDIF_IN1)
4834 #define MX6Q_PAD_GPIO_16__GPIO_7_11 (_MX6Q_PAD_GPIO_16__GPIO_7_11)
4835 #define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4836 #define MX6Q_PAD_GPIO_16__SJC_DE_B (_MX6Q_PAD_GPIO_16__SJC_DE_B)
4838 #define MX6Q_PAD_GPIO_17__ESAI1_TX0 (_MX6Q_PAD_GPIO_17__ESAI1_TX0)
4839 #define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN)
4840 #define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY)
4841 #define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0)
4842 #define MX6Q_PAD_GPIO_17__SPDIF_OUT1 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1)
4843 #define MX6Q_PAD_GPIO_17__GPIO_7_12 (_MX6Q_PAD_GPIO_17__GPIO_7_12)
4844 #define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT)
4846 #define MX6Q_PAD_GPIO_18__ESAI1_TX1 (_MX6Q_PAD_GPIO_18__ESAI1_TX1)
4847 #define MX6Q_PAD_GPIO_18__ENET_RX_CLK (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4848 #define MX6Q_PAD_GPIO_18__USDHC3_VSELECT (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
4849 #define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1)
4850 #define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK)
4851 #define MX6Q_PAD_GPIO_18__GPIO_7_13 (_MX6Q_PAD_GPIO_18__GPIO_7_13)
4852 #define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL)
4853 #define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST)
4855 #define MX6Q_PAD_GPIO_19__KPP_COL_5 (_MX6Q_PAD_GPIO_19__KPP_COL_5)
4856 #define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT)
4857 #define MX6Q_PAD_GPIO_19__SPDIF_OUT1 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1)
4858 #define MX6Q_PAD_GPIO_19__CCM_CLKO (_MX6Q_PAD_GPIO_19__CCM_CLKO)
4859 #define MX6Q_PAD_GPIO_19__ECSPI1_RDY (_MX6Q_PAD_GPIO_19__ECSPI1_RDY)
4860 #define MX6Q_PAD_GPIO_19__GPIO_4_5 (_MX6Q_PAD_GPIO_19__GPIO_4_5)
4861 #define MX6Q_PAD_GPIO_19__ENET_TX_ER (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
4862 #define MX6Q_PAD_GPIO_19__SRC_INT_BOOT (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT)
4864 #define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK)
4865 #define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12)
4866 #define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0)
4867 #define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18)
4868 #define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29)
4869 #define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO)
4871 #define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC)
4872 #define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13)
4873 #define MX6Q_PAD_CSI0_MCLK__CCM_CLKO (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO)
4874 #define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1)
4875 #define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19)
4876 #define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30)
4877 #define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL)
4879 #define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN)
4880 #define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0)
4881 #define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14)
4882 #define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2)
4883 #define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20)
4884 #define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31)
4885 #define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK)
4887 #define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC)
4888 #define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1)
4889 #define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15)
4890 #define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3)
4891 #define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21)
4892 #define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32)
4893 #define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0)
4895 #define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4)
4896 #define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2)
4897 #define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK)
4898 #define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5)
4899 #define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC)
4900 #define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22)
4901 #define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43)
4902 #define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1)
4904 #define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5)
4905 #define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3)
4906 #define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI)
4907 #define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5)
4908 #define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD)
4909 #define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23)
4910 #define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44)
4911 #define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2)
4913 #define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6)
4914 #define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4)
4915 #define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO)
4916 #define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6)
4917 #define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS)
4918 #define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24)
4919 #define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45)
4920 #define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3)
4922 #define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7)
4923 #define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5)
4924 #define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0)
4925 #define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6)
4926 #define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD)
4927 #define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25)
4928 #define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46)
4929 #define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4)
4931 #define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8)
4932 #define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6)
4933 #define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK)
4934 #define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7)
4935 #define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4936 #define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26)
4937 #define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47)
4938 #define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5)
4940 #define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9)
4941 #define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7)
4942 #define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI)
4943 #define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7)
4944 #define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
4945 #define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27)
4946 #define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48)
4947 #define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6)
4949 #define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10)
4950 #define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC)
4951 #define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO)
4952 #define MX6Q_PAD_CSI0_DAT10__UART1_TXD (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4953 #define MX6Q_PAD_CSI0_DAT10__UART1_RXD (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4954 #define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4)
4955 #define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28)
4956 #define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33)
4957 #define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7)
4959 #define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11)
4960 #define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS)
4961 #define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0)
4962 #define MX6Q_PAD_CSI0_DAT11__UART1_TXD (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4963 #define MX6Q_PAD_CSI0_DAT11__UART1_RXD (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4964 #define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5)
4965 #define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29)
4966 #define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34)
4967 #define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8)
4969 #define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12)
4970 #define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8)
4971 #define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16)
4972 #define MX6Q_PAD_CSI0_DAT12__UART4_TXD (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4973 #define MX6Q_PAD_CSI0_DAT12__UART4_RXD (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4974 #define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6)
4975 #define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30)
4976 #define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35)
4977 #define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9)
4979 #define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13)
4980 #define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9)
4981 #define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17)
4982 #define MX6Q_PAD_CSI0_DAT13__UART4_TXD (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4983 #define MX6Q_PAD_CSI0_DAT13__UART4_RXD (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4984 #define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7)
4985 #define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31)
4986 #define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36)
4987 #define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10)
4989 #define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14)
4990 #define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10)
4991 #define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18)
4992 #define MX6Q_PAD_CSI0_DAT14__UART5_TXD (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4993 #define MX6Q_PAD_CSI0_DAT14__UART5_RXD (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
4994 #define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8)
4995 #define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0)
4996 #define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37)
4997 #define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11)
4999 #define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15)
5000 #define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11)
5001 #define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19)
5002 #define MX6Q_PAD_CSI0_DAT15__UART5_TXD (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5003 #define MX6Q_PAD_CSI0_DAT15__UART5_RXD (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5004 #define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9)
5005 #define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1)
5006 #define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38)
5007 #define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12)
5009 #define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16)
5010 #define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12)
5011 #define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20)
5012 #define MX6Q_PAD_CSI0_DAT16__UART4_CTS (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5013 #define MX6Q_PAD_CSI0_DAT16__UART4_RTS (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5014 #define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10)
5015 #define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2)
5016 #define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39)
5017 #define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13)
5019 #define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17)
5020 #define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13)
5021 #define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21)
5022 #define MX6Q_PAD_CSI0_DAT17__UART4_CTS (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5023 #define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11)
5024 #define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3)
5025 #define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40)
5026 #define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14)
5028 #define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18)
5029 #define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14)
5030 #define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22)
5031 #define MX6Q_PAD_CSI0_DAT18__UART5_CTS (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5032 #define MX6Q_PAD_CSI0_DAT18__UART5_RTS (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5033 #define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12)
5034 #define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4)
5035 #define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41)
5036 #define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15)
5038 #define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19)
5039 #define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15)
5040 #define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23)
5041 #define MX6Q_PAD_CSI0_DAT19__UART5_CTS (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5042 #define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13)
5043 #define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5)
5044 #define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42)
5045 #define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9)
5047 #define MX6Q_PAD_JTAG_TMS__SJC_TMS (_MX6Q_PAD_JTAG_TMS__SJC_TMS)
5049 #define MX6Q_PAD_JTAG_MOD__SJC_MOD (_MX6Q_PAD_JTAG_MOD__SJC_MOD)
5051 #define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB)
5053 #define MX6Q_PAD_JTAG_TDI__SJC_TDI (_MX6Q_PAD_JTAG_TDI__SJC_TDI)
5055 #define MX6Q_PAD_JTAG_TCK__SJC_TCK (_MX6Q_PAD_JTAG_TCK__SJC_TCK)
5057 #define MX6Q_PAD_JTAG_TDO__SJC_TDO (_MX6Q_PAD_JTAG_TDO__SJC_TDO)
5059 #define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3)
5061 #define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2)
5063 #define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK)
5065 #define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1)
5067 #define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0)
5069 #define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3)
5071 #define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK)
5073 #define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2)
5075 #define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1)
5077 #define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0)
5079 #define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1)
5081 #define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM)
5083 #define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ)
5085 #define MX6Q_PAD_POR_B__SRC_POR_B (_MX6Q_PAD_POR_B__SRC_POR_B)
5087 #define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1)
5089 #define MX6Q_PAD_RESET_IN_B__SRC_RESET_B (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B)
5091 #define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0)
5093 #define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE)
5095 #define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5096 #define MX6Q_PAD_SD3_DAT7__UART1_TXD (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5097 #define MX6Q_PAD_SD3_DAT7__UART1_RXD (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5098 #define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24)
5099 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0)
5100 #define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0)
5101 #define MX6Q_PAD_SD3_DAT7__GPIO_6_17 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17)
5102 #define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12)
5103 #define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV)
5105 #define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5106 #define MX6Q_PAD_SD3_DAT6__UART1_TXD (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5107 #define MX6Q_PAD_SD3_DAT6__UART1_RXD (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5108 #define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25)
5109 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1)
5110 #define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1)
5111 #define MX6Q_PAD_SD3_DAT6__GPIO_6_18 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18)
5112 #define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13)
5113 #define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10)
5115 #define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5116 #define MX6Q_PAD_SD3_DAT5__UART2_TXD (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5117 #define MX6Q_PAD_SD3_DAT5__UART2_RXD (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5118 #define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26)
5119 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2)
5120 #define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2)
5121 #define MX6Q_PAD_SD3_DAT5__GPIO_7_0 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0)
5122 #define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14)
5123 #define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11)
5125 #define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5126 #define MX6Q_PAD_SD3_DAT4__UART2_TXD (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5127 #define MX6Q_PAD_SD3_DAT4__UART2_RXD (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5128 #define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27)
5129 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3)
5130 #define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3)
5131 #define MX6Q_PAD_SD3_DAT4__GPIO_7_1 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1)
5132 #define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15)
5133 #define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12)
5135 #define MX6Q_PAD_SD3_CMD__USDHC3_CMD (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5136 #define MX6Q_PAD_SD3_CMD__UART2_CTS (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5137 #define MX6Q_PAD_SD3_CMD__CAN1_TXCAN (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN)
5138 #define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4)
5139 #define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4)
5140 #define MX6Q_PAD_SD3_CMD__GPIO_7_2 (_MX6Q_PAD_SD3_CMD__GPIO_7_2)
5141 #define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16)
5142 #define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13)
5144 #define MX6Q_PAD_SD3_CLK__USDHC3_CLK (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5145 #define MX6Q_PAD_SD3_CLK__UART2_CTS (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5146 #define MX6Q_PAD_SD3_CLK__UART2_RTS (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5147 #define MX6Q_PAD_SD3_CLK__CAN1_RXCAN (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN)
5148 #define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5)
5149 #define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5)
5150 #define MX6Q_PAD_SD3_CLK__GPIO_7_3 (_MX6Q_PAD_SD3_CLK__GPIO_7_3)
5151 #define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17)
5152 #define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14)
5154 #define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5155 #define MX6Q_PAD_SD3_DAT0__UART1_CTS (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5156 #define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN)
5157 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6)
5158 #define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6)
5159 #define MX6Q_PAD_SD3_DAT0__GPIO_7_4 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4)
5160 #define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18)
5161 #define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15)
5163 #define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5164 #define MX6Q_PAD_SD3_DAT1__UART1_CTS (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5165 #define MX6Q_PAD_SD3_DAT1__UART1_RTS (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5166 #define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN)
5167 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7)
5168 #define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7)
5169 #define MX6Q_PAD_SD3_DAT1__GPIO_7_5 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5)
5170 #define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19)
5171 #define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0)
5173 #define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5174 #define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28)
5175 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8)
5176 #define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8)
5177 #define MX6Q_PAD_SD3_DAT2__GPIO_7_6 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6)
5178 #define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20)
5179 #define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1)
5181 #define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5182 #define MX6Q_PAD_SD3_DAT3__UART3_CTS (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5183 #define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29)
5184 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9)
5185 #define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9)
5186 #define MX6Q_PAD_SD3_DAT3__GPIO_7_7 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7)
5187 #define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21)
5188 #define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2)
5190 #define MX6Q_PAD_SD3_RST__USDHC3_RST (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5191 #define MX6Q_PAD_SD3_RST__UART3_CTS (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5192 #define MX6Q_PAD_SD3_RST__UART3_RTS (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5193 #define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30)
5194 #define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10)
5195 #define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10)
5196 #define MX6Q_PAD_SD3_RST__GPIO_7_8 (_MX6Q_PAD_SD3_RST__GPIO_7_8)
5197 #define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22)
5198 #define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3)
5200 #define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE)
5201 #define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4)
5202 #define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31)
5203 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11)
5204 #define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11)
5205 #define MX6Q_PAD_NANDF_CLE__GPIO_6_7 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7)
5206 #define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23)
5207 #define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0)
5209 #define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE)
5210 #define MX6Q_PAD_NANDF_ALE__USDHC4_RST (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5211 #define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0)
5212 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12)
5213 #define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12)
5214 #define MX6Q_PAD_NANDF_ALE__GPIO_6_8 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8)
5215 #define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24)
5216 #define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1)
5218 #define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN)
5219 #define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5)
5220 #define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1)
5221 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13)
5222 #define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13)
5223 #define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9)
5224 #define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32)
5225 #define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0)
5227 #define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0)
5228 #define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1)
5229 #define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2)
5230 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14)
5231 #define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14)
5232 #define MX6Q_PAD_NANDF_RB0__GPIO_6_10 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10)
5233 #define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33)
5234 #define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1)
5236 #define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N)
5237 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15)
5238 #define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15)
5239 #define MX6Q_PAD_NANDF_CS0__GPIO_6_11 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11)
5240 #define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2)
5242 #define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N)
5243 #define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5244 #define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5245 #define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3)
5246 #define MX6Q_PAD_NANDF_CS1__GPIO_6_14 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14)
5247 #define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT)
5249 #define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N)
5250 #define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0)
5251 #define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0)
5252 #define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE)
5253 #define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2)
5254 #define MX6Q_PAD_NANDF_CS2__GPIO_6_15 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15)
5255 #define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0)
5257 #define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N)
5258 #define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1)
5259 #define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1)
5260 #define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26)
5261 #define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4)
5262 #define MX6Q_PAD_NANDF_CS3__GPIO_6_16 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16)
5263 #define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1)
5264 #define MX6Q_PAD_NANDF_CS3__TPSMP_CLK (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK)
5266 #define MX6Q_PAD_SD4_CMD__USDHC4_CMD (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5267 #define MX6Q_PAD_SD4_CMD__RAWNAND_RDN (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN)
5268 #define MX6Q_PAD_SD4_CMD__UART3_TXD (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5269 #define MX6Q_PAD_SD4_CMD__UART3_RXD (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5270 #define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5)
5271 #define MX6Q_PAD_SD4_CMD__GPIO_7_9 (_MX6Q_PAD_SD4_CMD__GPIO_7_9)
5272 #define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR)
5274 #define MX6Q_PAD_SD4_CLK__USDHC4_CLK (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5275 #define MX6Q_PAD_SD4_CLK__RAWNAND_WRN (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN)
5276 #define MX6Q_PAD_SD4_CLK__UART3_TXD (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5277 #define MX6Q_PAD_SD4_CLK__UART3_RXD (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5278 #define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6)
5279 #define MX6Q_PAD_SD4_CLK__GPIO_7_10 (_MX6Q_PAD_SD4_CLK__GPIO_7_10)
5281 #define MX6Q_PAD_NANDF_D0__RAWNAND_D0 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0)
5282 #define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5283 #define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0)
5284 #define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16)
5285 #define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16)
5286 #define MX6Q_PAD_NANDF_D0__GPIO_2_0 (_MX6Q_PAD_NANDF_D0__GPIO_2_0)
5287 #define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0)
5288 #define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0)
5290 #define MX6Q_PAD_NANDF_D1__RAWNAND_D1 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1)
5291 #define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5292 #define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1)
5293 #define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17)
5294 #define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17)
5295 #define MX6Q_PAD_NANDF_D1__GPIO_2_1 (_MX6Q_PAD_NANDF_D1__GPIO_2_1)
5296 #define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1)
5297 #define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1)
5299 #define MX6Q_PAD_NANDF_D2__RAWNAND_D2 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2)
5300 #define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5301 #define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2)
5302 #define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18)
5303 #define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18)
5304 #define MX6Q_PAD_NANDF_D2__GPIO_2_2 (_MX6Q_PAD_NANDF_D2__GPIO_2_2)
5305 #define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2)
5306 #define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2)
5308 #define MX6Q_PAD_NANDF_D3__RAWNAND_D3 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3)
5309 #define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5310 #define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3)
5311 #define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19)
5312 #define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19)
5313 #define MX6Q_PAD_NANDF_D3__GPIO_2_3 (_MX6Q_PAD_NANDF_D3__GPIO_2_3)
5314 #define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3)
5315 #define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3)
5317 #define MX6Q_PAD_NANDF_D4__RAWNAND_D4 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4)
5318 #define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5319 #define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4)
5320 #define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20)
5321 #define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20)
5322 #define MX6Q_PAD_NANDF_D4__GPIO_2_4 (_MX6Q_PAD_NANDF_D4__GPIO_2_4)
5323 #define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4)
5324 #define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4)
5326 #define MX6Q_PAD_NANDF_D5__RAWNAND_D5 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5)
5327 #define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5328 #define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5)
5329 #define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21)
5330 #define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21)
5331 #define MX6Q_PAD_NANDF_D5__GPIO_2_5 (_MX6Q_PAD_NANDF_D5__GPIO_2_5)
5332 #define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5)
5333 #define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5)
5335 #define MX6Q_PAD_NANDF_D6__RAWNAND_D6 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6)
5336 #define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5337 #define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6)
5338 #define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22)
5339 #define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22)
5340 #define MX6Q_PAD_NANDF_D6__GPIO_2_6 (_MX6Q_PAD_NANDF_D6__GPIO_2_6)
5341 #define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6)
5342 #define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6)
5344 #define MX6Q_PAD_NANDF_D7__RAWNAND_D7 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7)
5345 #define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5346 #define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7)
5347 #define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23)
5348 #define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23)
5349 #define MX6Q_PAD_NANDF_D7__GPIO_2_7 (_MX6Q_PAD_NANDF_D7__GPIO_2_7)
5350 #define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7)
5351 #define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7)
5353 #define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8)
5354 #define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5355 #define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS)
5356 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24)
5357 #define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24)
5358 #define MX6Q_PAD_SD4_DAT0__GPIO_2_8 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8)
5359 #define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8)
5360 #define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8)
5362 #define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9)
5363 #define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5364 #define MX6Q_PAD_SD4_DAT1__PWM3_PWMO (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO)
5365 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25)
5366 #define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25)
5367 #define MX6Q_PAD_SD4_DAT1__GPIO_2_9 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9)
5368 #define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9)
5369 #define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9)
5371 #define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10)
5372 #define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5373 #define MX6Q_PAD_SD4_DAT2__PWM4_PWMO (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO)
5374 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26)
5375 #define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26)
5376 #define MX6Q_PAD_SD4_DAT2__GPIO_2_10 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10)
5377 #define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10)
5378 #define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10)
5380 #define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11)
5381 #define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5382 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27)
5383 #define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27)
5384 #define MX6Q_PAD_SD4_DAT3__GPIO_2_11 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11)
5385 #define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11)
5386 #define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11)
5388 #define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12)
5389 #define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5390 #define MX6Q_PAD_SD4_DAT4__UART2_TXD (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5391 #define MX6Q_PAD_SD4_DAT4__UART2_RXD (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5392 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28)
5393 #define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28)
5394 #define MX6Q_PAD_SD4_DAT4__GPIO_2_12 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12)
5395 #define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12)
5396 #define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12)
5398 #define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13)
5399 #define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5400 #define MX6Q_PAD_SD4_DAT5__UART2_CTS (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5401 #define MX6Q_PAD_SD4_DAT5__UART2_RTS (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5402 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29)
5403 #define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29)
5404 #define MX6Q_PAD_SD4_DAT5__GPIO_2_13 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13)
5405 #define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13)
5406 #define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13)
5408 #define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14)
5409 #define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5410 #define MX6Q_PAD_SD4_DAT6__UART2_CTS (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5411 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30)
5412 #define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30)
5413 #define MX6Q_PAD_SD4_DAT6__GPIO_2_14 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14)
5414 #define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14)
5415 #define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14)
5417 #define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15)
5418 #define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5419 #define MX6Q_PAD_SD4_DAT7__UART2_TXD (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5420 #define MX6Q_PAD_SD4_DAT7__UART2_RXD (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
5421 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31)
5422 #define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31)
5423 #define MX6Q_PAD_SD4_DAT7__GPIO_2_15 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15)
5424 #define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15)
5425 #define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15)
5427 #define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5428 #define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0)
5429 #define MX6Q_PAD_SD1_DAT1__PWM3_PWMO (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO)
5430 #define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2)
5431 #define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7)
5432 #define MX6Q_PAD_SD1_DAT1__GPIO_1_17 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17)
5433 #define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0)
5434 #define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8)
5436 #define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5437 #define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO)
5438 #define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS)
5439 #define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1)
5440 #define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8)
5441 #define MX6Q_PAD_SD1_DAT0__GPIO_1_16 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16)
5442 #define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1)
5443 #define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7)
5445 #define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5446 #define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2)
5447 #define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3)
5448 #define MX6Q_PAD_SD1_DAT3__PWM1_PWMO (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO)
5449 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B)
5450 #define MX6Q_PAD_SD1_DAT3__GPIO_1_21 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21)
5451 #define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB)
5452 #define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6)
5454 #define MX6Q_PAD_SD1_CMD__USDHC1_CMD (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5455 #define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI)
5456 #define MX6Q_PAD_SD1_CMD__PWM4_PWMO (_MX6Q_PAD_SD1_CMD__PWM4_PWMO)
5457 #define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1)
5458 #define MX6Q_PAD_SD1_CMD__GPIO_1_18 (_MX6Q_PAD_SD1_CMD__GPIO_1_18)
5459 #define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5)
5461 #define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5462 #define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1)
5463 #define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2)
5464 #define MX6Q_PAD_SD1_DAT2__PWM2_PWMO (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO)
5465 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B)
5466 #define MX6Q_PAD_SD1_DAT2__GPIO_1_19 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19)
5467 #define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB)
5468 #define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4)
5470 #define MX6Q_PAD_SD1_CLK__USDHC1_CLK (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5471 #define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK)
5472 #define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT)
5473 #define MX6Q_PAD_SD1_CLK__GPT_CLKIN (_MX6Q_PAD_SD1_CLK__GPT_CLKIN)
5474 #define MX6Q_PAD_SD1_CLK__GPIO_1_20 (_MX6Q_PAD_SD1_CLK__GPIO_1_20)
5475 #define MX6Q_PAD_SD1_CLK__PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0)
5476 #define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0)
5478 #define MX6Q_PAD_SD2_CLK__USDHC2_CLK (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5479 #define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK)
5480 #define MX6Q_PAD_SD2_CLK__KPP_COL_5 (_MX6Q_PAD_SD2_CLK__KPP_COL_5)
5481 #define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS)
5482 #define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9)
5483 #define MX6Q_PAD_SD2_CLK__GPIO_1_10 (_MX6Q_PAD_SD2_CLK__GPIO_1_10)
5484 #define MX6Q_PAD_SD2_CLK__PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1)
5485 #define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1)
5487 #define MX6Q_PAD_SD2_CMD__USDHC2_CMD (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5488 #define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI)
5489 #define MX6Q_PAD_SD2_CMD__KPP_ROW_5 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5)
5490 #define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC)
5491 #define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10)
5492 #define MX6Q_PAD_SD2_CMD__GPIO_1_11 (_MX6Q_PAD_SD2_CMD__GPIO_1_11)
5494 #define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
5495 #define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3)
5496 #define MX6Q_PAD_SD2_DAT3__KPP_COL_6 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6)
5497 #define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC)
5498 #define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11)
5499 #define MX6Q_PAD_SD2_DAT3__GPIO_1_12 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12)
5500 #define MX6Q_PAD_SD2_DAT3__SJC_DONE (_MX6Q_PAD_SD2_DAT3__SJC_DONE)
5501 #define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3)
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