arch/arm/include/asm/arch-mx6/regs-bch.h

   1 /*
   2  * Freescale i.MX6 BCH Register Definitions
   3  *
   4  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   5  * based on: mx28/regs-bch.h
   6  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   7  * on behalf of DENX Software Engineering GmbH
   8  *
   9  * Based on code from LTIB:
  10  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26  *
  27  */
  28
  29 #ifndef __MX6_REGS_BCH_H__
  30 #define __MX6_REGS_BCH_H__
  31
  32 //#include <asm/arch/regs-common.h>
  33
  34 #define GPMI_BASE_ADDRESS               0x00112000
  35 #define BCH_BASE_ADDRESS                0x00114000
  36
  37 #ifndef __ASSEMBLY__
  38 struct bch_regs {
  39         mx6_reg_32(hw_bch_ctrl);                        /* 0x000 */
  40         mx6_reg_32(hw_bch_status0);                     /* 0x010 */
  41         mx6_reg_32(hw_bch_mode);                        /* 0x020 */
  42         reg_32(hw_bch_encodeptr);                       /* 0x030 */
  43         reg_32(hw_bch_dataptr);                         /* 0x040 */
  44         reg_32(hw_bch_metaptr);                         /* 0x050 */
  45         reg_32(reserved);                               /* 0x060 */
  46         mx6_reg_32(hw_bch_layoutselect);                /* 0x070 */
  47         reg_32(hw_bch_flash0layout0);                   /* 0x080 */
  48         reg_32(hw_bch_flash0layout1);                   /* 0x090 */
  49         reg_32(hw_bch_flash1layout0);                   /* 0x0a0 */
  50         reg_32(hw_bch_flash1layout1);                   /* 0x0b0 */
  51         reg_32(hw_bch_flash2layout0);                   /* 0x0c0 */
  52         reg_32(hw_bch_flash2layout1);                   /* 0x0d0 */
  53         reg_32(hw_bch_flash3layout0);                   /* 0x0e0 */
  54         reg_32(hw_bch_flash3layout1);                   /* 0x0f0 */
  55         reg_32(hw_bch_debug0);                          /* 0x100 */
  56         reg_32(hw_bch_dbgkesread);                      /* 0x110 */
  57         reg_32(hw_bch_dbgcsferead);                     /* 0x120 */
  58         reg_32(hw_bch_dbgsyndegread);                   /* 0x130 */
  59         reg_32(hw_bch_dbgahbmread);                     /* 0x140 */
  60         reg_32(hw_bch_blockname);                       /* 0x150 */
  61         reg_32(hw_bch_version);                         /* 0x160 */
  62 };
  63 #endif
  64
  65 #define BCH_CTRL_SFTRST                                 (1 << 31)
  66 #define BCH_CTRL_CLKGATE                                (1 << 30)
  67 #define BCH_CTRL_DEBUGSYNDROME                          (1 << 22)
  68 #define BCH_CTRL_M2M_LAYOUT_MASK                        (0x3 << 18)
  69 #define BCH_CTRL_M2M_LAYOUT_OFFSET                      18
  70 #define BCH_CTRL_M2M_ENCODE                             (1 << 17)
  71 #define BCH_CTRL_M2M_ENABLE                             (1 << 16)
  72 #define BCH_CTRL_DEBUG_STALL_IRQ_EN                     (1 << 10)
  73 #define BCH_CTRL_COMPLETE_IRQ_EN                        (1 << 8)
  74 #define BCH_CTRL_BM_ERROR_IRQ                           (1 << 3)
  75 #define BCH_CTRL_DEBUG_STALL_IRQ                        (1 << 2)
  76 #define BCH_CTRL_COMPLETE_IRQ                           (1 << 0)
  77
  78 #define BCH_STATUS0_HANDLE_MASK                         (0xfff << 20)
  79 #define BCH_STATUS0_HANDLE_OFFSET                       20
  80 #define BCH_STATUS0_COMPLETED_CE_MASK                   (0xf << 16)
  81 #define BCH_STATUS0_COMPLETED_CE_OFFSET                 16
  82 #define BCH_STATUS0_STATUS_BLK0_MASK                    (0xff << 8)
  83 #define BCH_STATUS0_STATUS_BLK0_OFFSET                  8
  84 #define BCH_STATUS0_STATUS_BLK0_ZERO                    (0x00 << 8)
  85 #define BCH_STATUS0_STATUS_BLK0_ERROR1                  (0x01 << 8)
  86 #define BCH_STATUS0_STATUS_BLK0_ERROR2                  (0x02 << 8)
  87 #define BCH_STATUS0_STATUS_BLK0_ERROR3                  (0x03 << 8)
  88 #define BCH_STATUS0_STATUS_BLK0_ERROR4                  (0x04 << 8)
  89 #define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE           (0xfe << 8)
  90 #define BCH_STATUS0_STATUS_BLK0_ERASED                  (0xff << 8)
  91 #define BCH_STATUS0_ALLONES                             (1 << 4)
  92 #define BCH_STATUS0_CORRECTED                           (1 << 3)
  93 #define BCH_STATUS0_UNCORRECTABLE                       (1 << 2)
  94
  95 #define BCH_MODE_ERASE_THRESHOLD_MASK                   0xff
  96 #define BCH_MODE_ERASE_THRESHOLD_OFFSET                 0
  97
  98 #define BCH_ENCODEPTR_ADDR_MASK                         0xffffffff
  99 #define BCH_ENCODEPTR_ADDR_OFFSET                       0
 100
 101 #define BCH_DATAPTR_ADDR_MASK                           0xffffffff
 102 #define BCH_DATAPTR_ADDR_OFFSET                         0
 103
 104 #define BCH_METAPTR_ADDR_MASK                           0xffffffff
 105 #define BCH_METAPTR_ADDR_OFFSET                         0
 106
 107 #define BCH_LAYOUTSELECT_CS15_SELECT_MASK               (0x3 << BCH_LAYOUTSELECT_CS15_SELECT_OFFSET)
 108 #define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET             30
 109 #define BCH_LAYOUTSELECT_CS14_SELECT_MASK               (0x3 << BCH_LAYOUTSELECT_CS14_SELECT_OFFSET)
 110 #define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET             28
 111 #define BCH_LAYOUTSELECT_CS13_SELECT_MASK               (0x3 << BCH_LAYOUTSELECT_CS13_SELECT_OFFSET)
 112 #define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET             26
 113 #define BCH_LAYOUTSELECT_CS12_SELECT_MASK               (0x3 << BCH_LAYOUTSELECT_CS12_SELECT_OFFSET)
 114 #define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET             24
 115 #define BCH_LAYOUTSELECT_CS11_SELECT_MASK               (0x3 << BCH_LAYOUTSELECT_CS11_SELECT_OFFSET)
 116 #define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET             22
 117 #define BCH_LAYOUTSELECT_CS10_SELECT_MASK               (0x3 << BCH_LAYOUTSELECT_CS10_SELECT_OFFSET)
 118 #define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET             20
 119 #define BCH_LAYOUTSELECT_CS9_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS9_SELECT_OFFSET)
 120 #define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET              18
 121 #define BCH_LAYOUTSELECT_CS8_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS8_SELECT_OFFSET)
 122 #define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET              16
 123 #define BCH_LAYOUTSELECT_CS7_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS7_SELECT_OFFSET)
 124 #define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET              14
 125 #define BCH_LAYOUTSELECT_CS6_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS6_SELECT_OFFSET)
 126 #define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET              12
 127 #define BCH_LAYOUTSELECT_CS5_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS5_SELECT_OFFSET)
 128 #define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET              10
 129 #define BCH_LAYOUTSELECT_CS4_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS4_SELECT_OFFSET)
 130 #define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET              8
 131 #define BCH_LAYOUTSELECT_CS3_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS3_SELECT_OFFSET)
 132 #define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET              6
 133 #define BCH_LAYOUTSELECT_CS2_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS2_SELECT_OFFSET)
 134 #define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET              4
 135 #define BCH_LAYOUTSELECT_CS1_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS1_SELECT_OFFSET)
 136 #define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET              2
 137 #define BCH_LAYOUTSELECT_CS0_SELECT_MASK                (0x3 << BCH_LAYOUTSELECT_CS0_SELECT_OFFSET)
 138 #define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET              0
 139
 140 #define BCH_FLASHLAYOUT0_NBLOCKS_MASK                   (0xff << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET)
 141 #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET                 24
 142 #define BCH_FLASHLAYOUT0_META_SIZE_MASK                 (0xff << BCH_FLASHLAYOUT0_META_SIZE_OFFSET)
 143 #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET               16
 144 #define BCH_FLASHLAYOUT0_ECC0_MASK                      (0x1f << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 145 #define BCH_FLASHLAYOUT0_ECC0_OFFSET                    11
 146 #define BCH_FLASHLAYOUT0_ECC0_NONE                      (0x0 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 147 #define BCH_FLASHLAYOUT0_ECC0_ECC2                      (0x1 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 148 #define BCH_FLASHLAYOUT0_ECC0_ECC4                      (0x2 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 149 #define BCH_FLASHLAYOUT0_ECC0_ECC6                      (0x3 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 150 #define BCH_FLASHLAYOUT0_ECC0_ECC8                      (0x4 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 151 #define BCH_FLASHLAYOUT0_ECC0_ECC10                     (0x5 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 152 #define BCH_FLASHLAYOUT0_ECC0_ECC12                     (0x6 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 153 #define BCH_FLASHLAYOUT0_ECC0_ECC14                     (0x7 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 154 #define BCH_FLASHLAYOUT0_ECC0_ECC16                     (0x8 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 155 #define BCH_FLASHLAYOUT0_ECC0_ECC18                     (0x9 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 156 #define BCH_FLASHLAYOUT0_ECC0_ECC20                     (0xa << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 157 #define BCH_FLASHLAYOUT0_ECC0_ECC22                     (0xb << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 158 #define BCH_FLASHLAYOUT0_ECC0_ECC24                     (0xc << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 159 #define BCH_FLASHLAYOUT0_ECC0_ECC26                     (0xd << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 160 #define BCH_FLASHLAYOUT0_ECC0_ECC28                     (0xe << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 161 #define BCH_FLASHLAYOUT0_ECC0_ECC30                     (0xf << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 162 #define BCH_FLASHLAYOUT0_ECC0_ECC32                     (0x10 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
 163 #define BCH_FLASHLAYOUT0_GF13_0_GF14_1                  (1 << 10)
 164 #define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK                0x3ff
 165 #define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET              0
 166
 167 #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK                 (0xffff << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET)
 168 #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET               16
 169 #define BCH_FLASHLAYOUT1_ECCN_MASK                      (0x1f << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 170 #define BCH_FLASHLAYOUT1_ECCN_OFFSET                    11
 171 #define BCH_FLASHLAYOUT1_ECCN_NONE                      (0x0 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 172 #define BCH_FLASHLAYOUT1_ECCN_ECC2                      (0x1 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 173 #define BCH_FLASHLAYOUT1_ECCN_ECC4                      (0x2 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 174 #define BCH_FLASHLAYOUT1_ECCN_ECC6                      (0x3 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 175 #define BCH_FLASHLAYOUT1_ECCN_ECC8                      (0x4 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 176 #define BCH_FLASHLAYOUT1_ECCN_ECC10                     (0x5 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 177 #define BCH_FLASHLAYOUT1_ECCN_ECC12                     (0x6 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 178 #define BCH_FLASHLAYOUT1_ECCN_ECC14                     (0x7 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 179 #define BCH_FLASHLAYOUT1_ECCN_ECC16                     (0x8 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 180 #define BCH_FLASHLAYOUT1_ECCN_ECC18                     (0x9 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 181 #define BCH_FLASHLAYOUT1_ECCN_ECC20                     (0xa << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 182 #define BCH_FLASHLAYOUT1_ECCN_ECC22                     (0xb << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 183 #define BCH_FLASHLAYOUT1_ECCN_ECC24                     (0xc << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 184 #define BCH_FLASHLAYOUT1_ECCN_ECC26                     (0xd << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 185 #define BCH_FLASHLAYOUT1_ECCN_ECC28                     (0xe << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 186 #define BCH_FLASHLAYOUT1_ECCN_ECC30                     (0xf << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 187 #define BCH_FLASHLAYOUT1_ECCN_ECC32                     (0x10 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
 188 #define BCH_FLASHLAYOUT1_GF13_0_GF14_1                  (1 << 10)
 189 #define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK                0x3ff
 190 #define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET              0
 191
 192 #define BCH_DEBUG0_RSVD1_MASK                           (0x1f << 27)
 193 #define BCH_DEBUG0_RSVD1_OFFSET                         27
 194 #define BCH_DEBUG0_ROM_BIST_ENABLE                      (1 << 26)
 195 #define BCH_DEBUG0_ROM_BIST_COMPLETE                    (1 << 25)
 196 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK       (0x1ff << 16)
 197 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET     16
 198 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL     (0x0 << 16)
 199 #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE  (0x1 << 16)
 200 #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                 (1 << 15)
 201 #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               (1 << 14)
 202 #define BCH_DEBUG0_KES_DEBUG_MODE4K                     (1 << 13)
 203 #define BCH_DEBUG0_KES_DEBUG_KICK                       (1 << 12)
 204 #define BCH_DEBUG0_KES_STANDALONE                       (1 << 11)
 205 #define BCH_DEBUG0_KES_DEBUG_STEP                       (1 << 10)
 206 #define BCH_DEBUG0_KES_DEBUG_STALL                      (1 << 9)
 207 #define BCH_DEBUG0_BM_KES_TEST_BYPASS                   (1 << 8)
 208 #define BCH_DEBUG0_RSVD0_MASK                           (0x3 << 6)
 209 #define BCH_DEBUG0_RSVD0_OFFSET                         6
 210 #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK                0x3f
 211 #define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET              0
 212
 213 #define BCH_DBGKESREAD_VALUES_MASK                      0xffffffff
 214 #define BCH_DBGKESREAD_VALUES_OFFSET                    0
 215
 216 #define BCH_DBGCSFEREAD_VALUES_MASK                     0xffffffff
 217 #define BCH_DBGCSFEREAD_VALUES_OFFSET                   0
 218
 219 #define BCH_DBGSYNDGENREAD_VALUES_MASK                  0xffffffff
 220 #define BCH_DBGSYNDGENREAD_VALUES_OFFSET                0
 221
 222 #define BCH_DBGAHBMREAD_VALUES_MASK                     0xffffffff
 223 #define BCH_DBGAHBMREAD_VALUES_OFFSET                   0
 224
 225 #define BCH_BLOCKNAME_NAME_MASK                         0xffffffff
 226 #define BCH_BLOCKNAME_NAME_OFFSET                       0
 227
 228 #define BCH_VERSION_MAJOR_MASK                          (0xff << 24)
 229 #define BCH_VERSION_MAJOR_OFFSET                        24
 230 #define BCH_VERSION_MINOR_MASK                          (0xff << 16)
 231 #define BCH_VERSION_MINOR_OFFSET                        16
 232 #define BCH_VERSION_STEP_MASK                           0xffff
 233 #define BCH_VERSION_STEP_OFFSET                         0
 234
 235 #endif  /* __MX6_REGS_BCH_H__ */