2 * Freescale i.MX28 Power Controller Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __MX28_REGS_POWER_H__
10 #define __MX28_REGS_POWER_H__
12 #include <asm/imx-common/regs-common.h>
15 struct mxs_power_regs {
16 mxs_reg_32(hw_power_ctrl); /* 0x00 */
17 mxs_reg_32(hw_power_5vctrl); /* 0x10 */
18 mxs_reg_32(hw_power_minpwr); /* 0x20 */
19 mxs_reg_32(hw_power_charge); /* 0x30 */
20 reg_32(hw_power_vdddctrl); /* 0x40 */
21 reg_32(hw_power_vddactrl); /* 0x50 */
22 reg_32(hw_power_vddioctrl); /* 0x60 */
23 reg_32(hw_power_vddmemctrl); /* 0x70 */
24 reg_32(hw_power_dcdc4p2); /* 0x80 */
25 reg_32(hw_power_misc); /* 0x90 */
26 reg_32(hw_power_dclimits); /* 0xa0 */
27 mxs_reg_32(hw_power_loopctrl); /* 0xb0 */
28 reg_32(hw_power_sts); /* 0xc0 */
29 mxs_reg_32(hw_power_speed); /* 0xd0 */
30 reg_32(hw_power_battmonitor); /* 0xe0 */
32 reg_32(reserved); /* 0xf0 */
34 mxs_reg_32(hw_power_reset); /* 0x100 */
35 mxs_reg_32(hw_power_debug); /* 0x110 */
36 mxs_reg_32(hw_power_thermal); /* 0x120 */
37 mxs_reg_32(hw_power_usb1ctrl); /* 0x130 */
38 mxs_reg_32(hw_power_special); /* 0x140 */
39 mxs_reg_32(hw_power_version); /* 0x150 */
40 mxs_reg_32(hw_power_anaclkctrl); /* 0x160 */
41 mxs_reg_32(hw_power_refctrl); /* 0x170 */
45 #define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
46 #define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
47 #define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
48 #define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
49 #define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
50 #define POWER_CTRL_PSWITCH_IRQ (1 << 20)
51 #define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
52 #define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
53 #define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
54 #define POWER_CTRL_POLARITY_DC_OK (1 << 16)
55 #define POWER_CTRL_DC_OK_IRQ (1 << 15)
56 #define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
57 #define POWER_CTRL_BATT_BO_IRQ (1 << 13)
58 #define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
59 #define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
60 #define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
61 #define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
62 #define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
63 #define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
64 #define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
65 #define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
66 #define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
67 #define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
68 #define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
69 #define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
70 #define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
72 #define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
73 #define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
74 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
75 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
76 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
77 #define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
78 #define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
79 #define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
80 #define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
81 #define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
82 #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
83 #define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
84 #define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
85 #define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
86 #define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
87 #define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
88 #define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
89 #define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
90 #define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
91 #define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
92 #define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
93 #define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
94 #define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
95 #define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
96 #define POWER_5VCTRL_DCDC_XFER (1 << 5)
97 #define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
98 #define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
99 #define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
100 #define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
101 #define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
103 #define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
104 #define POWER_MINPWR_PWD_BO (1 << 12)
105 #define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
106 #define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
107 #define POWER_MINPWR_ENABLE_OSC (1 << 9)
108 #define POWER_MINPWR_SELECT_OSC (1 << 8)
109 #define POWER_MINPWR_VBG_OFF (1 << 7)
110 #define POWER_MINPWR_DOUBLE_FETS (1 << 6)
111 #define POWER_MINPWR_HALFFETS (1 << 5)
112 #define POWER_MINPWR_LESSANA_I (1 << 4)
113 #define POWER_MINPWR_PWD_XTAL24 (1 << 3)
114 #define POWER_MINPWR_DC_STOPCLK (1 << 2)
115 #define POWER_MINPWR_EN_DC_PFM (1 << 1)
116 #define POWER_MINPWR_DC_HALFCLK (1 << 0)
118 #define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
119 #define POWER_CHARGE_ADJ_VOLT_OFFSET 24
120 #define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
121 #define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
122 #define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
123 #define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
124 #define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
125 #define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
126 #define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
127 #define POWER_CHARGE_ENABLE_LOAD (1 << 22)
128 #define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
129 #define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
130 #define POWER_CHARGE_LIION_4P1 (1 << 18)
131 #define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
132 #define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
133 #define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
134 #define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
135 #define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
136 #define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
137 #define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
138 #define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
139 #define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
140 #define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
141 #define POWER_CHARGE_BATTCHRG_I_OFFSET 0
142 #define POWER_CHARGE_BATTCHRG_I_10MA 0x01
143 #define POWER_CHARGE_BATTCHRG_I_20MA 0x02
144 #define POWER_CHARGE_BATTCHRG_I_50MA 0x04
145 #define POWER_CHARGE_BATTCHRG_I_100MA 0x08
146 #define POWER_CHARGE_BATTCHRG_I_200MA 0x10
147 #define POWER_CHARGE_BATTCHRG_I_400MA 0x20
149 #define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
150 #define POWER_VDDDCTRL_ADJTN_OFFSET 28
151 #define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
152 #define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
153 #define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
154 #define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
155 #define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
156 #define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
157 #define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
158 #define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
159 #define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
160 #define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
161 #define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
162 #define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
163 #define POWER_VDDDCTRL_TRG_MASK 0x1f
164 #define POWER_VDDDCTRL_TRG_OFFSET 0
166 #define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
167 #define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
168 #define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
169 #define POWER_VDDACTRL_DISABLE_FET (1 << 16)
170 #define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
171 #define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
172 #define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
173 #define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
174 #define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
175 #define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
176 #define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
177 #define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
178 #define POWER_VDDACTRL_TRG_MASK 0x1f
179 #define POWER_VDDACTRL_TRG_OFFSET 0
181 #define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
182 #define POWER_VDDIOCTRL_ADJTN_OFFSET 20
183 #define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
184 #define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
185 #define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
186 #define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
187 #define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
188 #define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
189 #define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
190 #define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
191 #define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
192 #define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
193 #define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
194 #define POWER_VDDIOCTRL_TRG_MASK 0x1f
195 #define POWER_VDDIOCTRL_TRG_OFFSET 0
197 #define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
198 #define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
199 #define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
200 #define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
201 #define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
202 #define POWER_VDDMEMCTRL_TRG_MASK 0x1f
203 #define POWER_VDDMEMCTRL_TRG_OFFSET 0
205 #define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
206 #define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
207 #define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
208 #define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
209 #define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
210 #define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
211 #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
212 #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
213 #define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
214 #define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
215 #define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
216 #define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
217 #define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
218 #define POWER_DCDC4P2_HYST_DIR (1 << 21)
219 #define POWER_DCDC4P2_HYST_THRESH (1 << 20)
220 #define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
221 #define POWER_DCDC4P2_TRG_OFFSET 16
222 #define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
223 #define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
224 #define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
225 #define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
226 #define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
227 #define POWER_DCDC4P2_BO_MASK (0x1f << 8)
228 #define POWER_DCDC4P2_BO_OFFSET 8
229 #define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
230 #define POWER_DCDC4P2_CMPTRIP_OFFSET 0
232 #define POWER_MISC_FREQSEL_MASK (0x7 << 4)
233 #define POWER_MISC_FREQSEL_OFFSET 4
234 #define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
235 #define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
236 #define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
237 #define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
238 #define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
239 #define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
240 #define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
241 #define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
242 #define POWER_MISC_DELAY_TIMING (1 << 2)
243 #define POWER_MISC_TEST (1 << 1)
244 #define POWER_MISC_SEL_PLLCLK (1 << 0)
246 #define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
247 #define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
248 #define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
249 #define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
251 #define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
252 #define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
253 #define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
254 #define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
255 #define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
256 #define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
257 #define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
258 #define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
259 #define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
260 #define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
261 #define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
262 #define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
263 #define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
264 #define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
265 #define POWER_LOOPCTRL_DC_FF_OFFSET 8
266 #define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
267 #define POWER_LOOPCTRL_DC_R_OFFSET 4
268 #define POWER_LOOPCTRL_DC_C_MASK 0x3
269 #define POWER_LOOPCTRL_DC_C_OFFSET 0
270 #define POWER_LOOPCTRL_DC_C_MAX 0x0
271 #define POWER_LOOPCTRL_DC_C_2X 0x1
272 #define POWER_LOOPCTRL_DC_C_4X 0x2
273 #define POWER_LOOPCTRL_DC_C_MIN 0x3
275 #define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
276 #define POWER_STS_PWRUP_SOURCE_OFFSET 24
277 #define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
278 #define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
279 #define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
280 #define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
281 #define POWER_STS_PSWITCH_MASK (0x3 << 20)
282 #define POWER_STS_PSWITCH_OFFSET 20
283 #define POWER_STS_THERMAL_WARNING (1 << 19)
284 #define POWER_STS_VDDMEM_BO (1 << 18)
285 #define POWER_STS_AVALID0_STATUS (1 << 17)
286 #define POWER_STS_BVALID0_STATUS (1 << 16)
287 #define POWER_STS_VBUSVALID0_STATUS (1 << 15)
288 #define POWER_STS_SESSEND0_STATUS (1 << 14)
289 #define POWER_STS_BATT_BO (1 << 13)
290 #define POWER_STS_VDD5V_FAULT (1 << 12)
291 #define POWER_STS_CHRGSTS (1 << 11)
292 #define POWER_STS_DCDC_4P2_BO (1 << 10)
293 #define POWER_STS_DC_OK (1 << 9)
294 #define POWER_STS_VDDIO_BO (1 << 8)
295 #define POWER_STS_VDDA_BO (1 << 7)
296 #define POWER_STS_VDDD_BO (1 << 6)
297 #define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
298 #define POWER_STS_VDD5V_DROOP (1 << 4)
299 #define POWER_STS_AVALID0 (1 << 3)
300 #define POWER_STS_BVALID0 (1 << 2)
301 #define POWER_STS_VBUSVALID0 (1 << 1)
302 #define POWER_STS_SESSEND0 (1 << 0)
304 #define POWER_SPEED_STATUS_MASK (0xffff << 8)
305 #define POWER_SPEED_STATUS_OFFSET 8
306 #define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
307 #define POWER_SPEED_STATUS_SEL_OFFSET 6
308 #define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
309 #define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
310 #define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
311 #define POWER_SPEED_CTRL_MASK 0x3
312 #define POWER_SPEED_CTRL_OFFSET 0
313 #define POWER_SPEED_CTRL_SS_OFF 0x0
314 #define POWER_SPEED_CTRL_SS_ON 0x1
315 #define POWER_SPEED_CTRL_SS_ENABLE 0x3
317 #define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
318 #define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
319 #define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
320 #define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
321 #define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
322 #define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
323 #define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
324 #define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
326 #define POWER_RESET_UNLOCK_MASK (0xffff << 16)
327 #define POWER_RESET_UNLOCK_OFFSET 16
328 #define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
329 #define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
330 #define POWER_RESET_PWD_OFF (1 << 1)
331 #define POWER_RESET_PWD (1 << 0)
333 #define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
334 #define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
335 #define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
336 #define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
338 #define POWER_THERMAL_TEST (1 << 8)
339 #define POWER_THERMAL_PWD (1 << 7)
340 #define POWER_THERMAL_LOW_POWER (1 << 6)
341 #define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
342 #define POWER_THERMAL_OFFSET_ADJ_OFFSET(n) (((n) << 4) & \
343 POWER_THERMAL_OFFSET_ADJ_MASK)
344 #define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
345 #define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
346 #define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
348 #define POWER_USB1CTRL_AVALID1 (1 << 3)
349 #define POWER_USB1CTRL_BVALID1 (1 << 2)
350 #define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
351 #define POWER_USB1CTRL_SESSEND1 (1 << 0)
353 #define POWER_SPECIAL_TEST_MASK 0xffffffff
354 #define POWER_SPECIAL_TEST_OFFSET 0
356 #define POWER_VERSION_MAJOR_MASK (0xff << 24)
357 #define POWER_VERSION_MAJOR_OFFSET 24
358 #define POWER_VERSION_MINOR_MASK (0xff << 16)
359 #define POWER_VERSION_MINOR_OFFSET 16
360 #define POWER_VERSION_STEP_MASK 0xffff
361 #define POWER_VERSION_STEP_OFFSET 0
363 #define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
364 #define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
365 #define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
366 #define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
367 #define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
368 #define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
369 #define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
370 #define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
371 #define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
372 #define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
373 #define POWER_ANACLKCTRL_INDIV_MASK 0x7
374 #define POWER_ANACLKCTRL_INDIV_OFFSET 0
376 #define POWER_REFCTRL_FASTSETTLING (1 << 26)
377 #define POWER_REFCTRL_RAISE_REF (1 << 25)
378 #define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
379 #define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
380 #define POWER_REFCTRL_VBG_ADJ_OFFSET 20
381 #define POWER_REFCTRL_LOW_PWR (1 << 19)
382 #define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
383 #define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
384 #define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
385 #define POWER_REFCTRL_ADJ_ANA (1 << 13)
386 #define POWER_REFCTRL_ADJ_VAG (1 << 12)
387 #define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
388 #define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
389 #define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
390 #define POWER_REFCTRL_VAG_VAL_OFFSET 4
392 #endif /* __MX28_REGS_POWER_H__ */