arch/arm/include/asm/arch-sunxi/clock_sun4i.h

   1 /*
   2  * sun4i, sun5i and sun7i clock register definitions
   3  *
   4  * (C) Copyright 2007-2011
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef _SUNXI_CLOCK_SUN4I_H
  12 #define _SUNXI_CLOCK_SUN4I_H
  13
  14 struct sunxi_ccm_reg {
  15         u32 pll1_cfg;           /* 0x00 pll1 control */
  16         u32 pll1_tun;           /* 0x04 pll1 tuning */
  17         u32 pll2_cfg;           /* 0x08 pll2 control */
  18         u32 pll2_tun;           /* 0x0c pll2 tuning */
  19         u32 pll3_cfg;           /* 0x10 pll3 control */
  20         u8 res0[0x4];
  21         u32 pll4_cfg;           /* 0x18 pll4 control */
  22         u8 res1[0x4];
  23         u32 pll5_cfg;           /* 0x20 pll5 control */
  24         u32 pll5_tun;           /* 0x24 pll5 tuning */
  25         u32 pll6_cfg;           /* 0x28 pll6 control */
  26         u32 pll6_tun;           /* 0x2c pll6 tuning */
  27         u32 pll7_cfg;           /* 0x30 pll7 control */
  28         u32 pll1_tun2;          /* 0x34 pll5 tuning2 */
  29         u8 res2[0x4];
  30         u32 pll5_tun2;          /* 0x3c pll5 tuning2 */
  31         u8 res3[0xc];
  32         u32 pll_lock_dbg;       /* 0x4c pll lock time debug */
  33         u32 osc24m_cfg;         /* 0x50 osc24m control */
  34         u32 cpu_ahb_apb0_cfg;   /* 0x54 cpu,ahb and apb0 divide ratio */
  35         u32 apb1_clk_div_cfg;   /* 0x58 apb1 clock dividor */
  36         u32 axi_gate;           /* 0x5c axi module clock gating */
  37         u32 ahb_gate0;          /* 0x60 ahb module clock gating 0 */
  38         u32 ahb_gate1;          /* 0x64 ahb module clock gating 1 */
  39         u32 apb0_gate;          /* 0x68 apb0 module clock gating */
  40         u32 apb1_gate;          /* 0x6c apb1 module clock gating */
  41         u8 res4[0x10];
  42         u32 nand0_clk_cfg;      /* 0x80 nand sub clock control */
  43         u32 ms_sclk_cfg;        /* 0x84 memory stick sub clock control */
  44         u32 sd0_clk_cfg;        /* 0x88 sd0 clock control */
  45         u32 sd1_clk_cfg;        /* 0x8c sd1 clock control */
  46         u32 sd2_clk_cfg;        /* 0x90 sd2 clock control */
  47         u32 sd3_clk_cfg;        /* 0x94 sd3 clock control */
  48         u32 ts_clk_cfg;         /* 0x98 transport stream clock control */
  49         u32 ss_clk_cfg;         /* 0x9c */
  50         u32 spi0_clk_cfg;       /* 0xa0 */
  51         u32 spi1_clk_cfg;       /* 0xa4 */
  52         u32 spi2_clk_cfg;       /* 0xa8 */
  53         u32 pata_clk_cfg;       /* 0xac */
  54         u32 ir0_clk_cfg;        /* 0xb0 */
  55         u32 ir1_clk_cfg;        /* 0xb4 */
  56         u32 iis_clk_cfg;        /* 0xb8 */
  57         u32 ac97_clk_cfg;       /* 0xbc */
  58         u32 spdif_clk_cfg;      /* 0xc0 */
  59         u32 keypad_clk_cfg;     /* 0xc4 */
  60         u32 sata_clk_cfg;       /* 0xc8 */
  61         u32 usb_clk_cfg;        /* 0xcc */
  62         u32 gps_clk_cfg;        /* 0xd0 */
  63         u32 spi3_clk_cfg;       /* 0xd4 */
  64         u8 res5[0x28];
  65         u32 dram_clk_gate;      /* 0x100 */
  66         u32 be0_clk_cfg;        /* 0x104 */
  67         u32 be1_clk_cfg;        /* 0x108 */
  68         u32 fe0_clk_cfg;        /* 0x10c */
  69         u32 fe1_clk_cfg;        /* 0x110 */
  70         u32 mp_clk_cfg;         /* 0x114 */
  71         u32 lcd0_ch0_clk_cfg;   /* 0x118 */
  72         u32 lcd1_ch0_clk_cfg;   /* 0x11c */
  73         u32 csi_isp_clk_cfg;    /* 0x120 */
  74         u8 res6[0x4];
  75         u32 tvd_clk_reg;        /* 0x128 */
  76         u32 lcd0_ch1_clk_cfg;   /* 0x12c */
  77         u32 lcd1_ch1_clk_cfg;   /* 0x130 */
  78         u32 csi0_clk_cfg;       /* 0x134 */
  79         u32 csi1_clk_cfg;       /* 0x138 */
  80         u32 ve_clk_cfg;         /* 0x13c */
  81         u32 audio_codec_clk_cfg;        /* 0x140 */
  82         u32 avs_clk_cfg;        /* 0x144 */
  83         u32 ace_clk_cfg;        /* 0x148 */
  84         u32 lvds_clk_cfg;       /* 0x14c */
  85         u32 hdmi_clk_cfg;       /* 0x150 */
  86         u32 mali_clk_cfg;       /* 0x154 */
  87         u8 res7[0x4];
  88         u32 mbus_clk_cfg;       /* 0x15c */
  89         u8 res8[0x4];
  90         u32 gmac_clk_cfg;       /* 0x164 */
  91 };
  92
  93 /* apb1 bit field */
  94 #define APB1_CLK_SRC_OSC24M             (0x0 << 24)
  95 #define APB1_CLK_SRC_PLL6               (0x1 << 24)
  96 #define APB1_CLK_SRC_LOSC               (0x2 << 24)
  97 #define APB1_CLK_SRC_MASK               (0x3 << 24)
  98 #define APB1_CLK_RATE_N_1               (0x0 << 16)
  99 #define APB1_CLK_RATE_N_2               (0x1 << 16)
 100 #define APB1_CLK_RATE_N_4               (0x2 << 16)
 101 #define APB1_CLK_RATE_N_8               (0x3 << 16)
 102 #define APB1_CLK_RATE_N_MASK            (3 << 16)
 103 #define APB1_CLK_RATE_M(m)              (((m)-1) << 0)
 104 #define APB1_CLK_RATE_M_MASK            (0x1f << 0)
 105
 106 /* apb1 gate field */
 107 #define APB1_GATE_UART_SHIFT    (16)
 108 #define APB1_GATE_UART_MASK             (0xff << APB1_GATE_UART_SHIFT)
 109 #define APB1_GATE_TWI_SHIFT     (0)
 110 #define APB1_GATE_TWI_MASK              (0xf << APB1_GATE_TWI_SHIFT)
 111
 112 /* clock divide */
 113 #define AXI_DIV_SHIFT           (0)
 114 #define AXI_DIV_1                       0
 115 #define AXI_DIV_2                       1
 116 #define AXI_DIV_3                       2
 117 #define AXI_DIV_4                       3
 118 #define AHB_DIV_SHIFT           (4)
 119 #define AHB_DIV_1                       0
 120 #define AHB_DIV_2                       1
 121 #define AHB_DIV_4                       2
 122 #define AHB_DIV_8                       3
 123 #define APB0_DIV_SHIFT          (8)
 124 #define APB0_DIV_1                      0
 125 #define APB0_DIV_2                      1
 126 #define APB0_DIV_4                      2
 127 #define APB0_DIV_8                      3
 128 #define CPU_CLK_SRC_SHIFT       (16)
 129 #define CPU_CLK_SRC_OSC24M              1
 130 #define CPU_CLK_SRC_PLL1                2
 131
 132 #define CCM_PLL1_CFG_ENABLE_SHIFT               31
 133 #define CCM_PLL1_CFG_VCO_RST_SHIFT              30
 134 #define CCM_PLL1_CFG_VCO_BIAS_SHIFT             26
 135 #define CCM_PLL1_CFG_PLL4_EXCH_SHIFT            25
 136 #define CCM_PLL1_CFG_BIAS_CUR_SHIFT             20
 137 #define CCM_PLL1_CFG_DIVP_SHIFT                 16
 138 #define CCM_PLL1_CFG_LCK_TMR_SHIFT              13
 139 #define CCM_PLL1_CFG_FACTOR_N_SHIFT             8
 140 #define CCM_PLL1_CFG_FACTOR_K_SHIFT             4
 141 #define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT      3
 142 #define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT      2
 143 #define CCM_PLL1_CFG_FACTOR_M_SHIFT             0
 144
 145 #define PLL1_CFG_DEFAULT        0xa1005000
 146
 147 #if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
 148 /*
 149  * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
 150  * halving the mbus frequency, so set it to 300 MHz ourselves and base the
 151  * mbus divider on that.
 152  */
 153 #define PLL6_CFG_DEFAULT        0xa1009900
 154 #else
 155 #define PLL6_CFG_DEFAULT        0xa1009911
 156 #endif
 157
 158 /* nand clock */
 159 #define NAND_CLK_SRC_OSC24              0
 160 #define NAND_CLK_DIV_N                  0
 161 #define NAND_CLK_DIV_M                  0
 162
 163 /* gps clock */
 164 #define GPS_SCLK_GATING_OFF             0
 165 #define GPS_RESET                       0
 166
 167 /* ahb clock gate bit offset */
 168 #define AHB_GATE_OFFSET_GPS             26
 169 #define AHB_GATE_OFFSET_SATA            25
 170 #define AHB_GATE_OFFSET_PATA            24
 171 #define AHB_GATE_OFFSET_SPI3            23
 172 #define AHB_GATE_OFFSET_SPI2            22
 173 #define AHB_GATE_OFFSET_SPI1            21
 174 #define AHB_GATE_OFFSET_SPI0            20
 175 #define AHB_GATE_OFFSET_TS0             18
 176 #define AHB_GATE_OFFSET_EMAC            17
 177 #define AHB_GATE_OFFSET_ACE             16
 178 #define AHB_GATE_OFFSET_DLL             15
 179 #define AHB_GATE_OFFSET_SDRAM           14
 180 #define AHB_GATE_OFFSET_NAND0           13
 181 #define AHB_GATE_OFFSET_MS              12
 182 #define AHB_GATE_OFFSET_MMC3            11
 183 #define AHB_GATE_OFFSET_MMC2            10
 184 #define AHB_GATE_OFFSET_MMC1            9
 185 #define AHB_GATE_OFFSET_MMC0            8
 186 #define AHB_GATE_OFFSET_MMC(n)          (AHB_GATE_OFFSET_MMC0 + (n))
 187 #define AHB_GATE_OFFSET_BIST            7
 188 #define AHB_GATE_OFFSET_DMA             6
 189 #define AHB_GATE_OFFSET_SS              5
 190 #define AHB_GATE_OFFSET_USB_OHCI1       4
 191 #define AHB_GATE_OFFSET_USB_EHCI1       3
 192 #define AHB_GATE_OFFSET_USB_OHCI0       2
 193 #define AHB_GATE_OFFSET_USB_EHCI0       1
 194 #define AHB_GATE_OFFSET_USB0            0
 195
 196 /* ahb clock gate bit offset (second register) */
 197 #define AHB_GATE_OFFSET_GMAC            17
 198 #define AHB_GATE_OFFSET_DE_FE0          14
 199 #define AHB_GATE_OFFSET_DE_BE0          12
 200 #define AHB_GATE_OFFSET_HDMI            11
 201 #define AHB_GATE_OFFSET_LCD1            5
 202 #define AHB_GATE_OFFSET_LCD0            4
 203 #define AHB_GATE_OFFSET_TVE1            3
 204 #define AHB_GATE_OFFSET_TVE0            2
 205
 206 #define CCM_AHB_GATE_GPS (0x1 << 26)
 207 #define CCM_AHB_GATE_SDRAM (0x1 << 14)
 208 #define CCM_AHB_GATE_DLL (0x1 << 15)
 209 #define CCM_AHB_GATE_ACE (0x1 << 16)
 210
 211 #define CCM_PLL3_CTRL_M(n)              (((n) & 0x7f) << 0)
 212 #define CCM_PLL3_CTRL_INTEGER_MODE      (0x1 << 15)
 213 #define CCM_PLL3_CTRL_EN                (0x1 << 31)
 214
 215 #define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
 216 #define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
 217 #define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
 218 #define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
 219 #define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
 220 #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
 221 #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
 222 #define CCM_PLL5_CTRL_K_SHIFT 4
 223 #define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
 224 #define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
 225 #define CCM_PLL5_CTRL_LDO (0x1 << 7)
 226 #define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
 227 #define CCM_PLL5_CTRL_N_SHIFT 8
 228 #define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
 229 #define CCM_PLL5_CTRL_N_X(n) (n)
 230 #define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
 231 #define CCM_PLL5_CTRL_P_SHIFT 16
 232 #define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
 233 #define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
 234 #define CCM_PLL5_CTRL_BW (0x1 << 18)
 235 #define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
 236 #define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
 237 #define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
 238 #define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
 239 #define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
 240 #define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
 241 #define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
 242 #define CCM_PLL5_CTRL_EN (0x1 << 31)
 243
 244 #define CCM_PLL6_CTRL_EN                31
 245 #define CCM_PLL6_CTRL_BYPASS_EN         30
 246 #define CCM_PLL6_CTRL_SATA_EN_SHIFT     14
 247 #define CCM_PLL6_CTRL_N_SHIFT           8
 248 #define CCM_PLL6_CTRL_N_MASK            (0x1f << CCM_PLL6_CTRL_N_SHIFT)
 249 #define CCM_PLL6_CTRL_K_SHIFT           4
 250 #define CCM_PLL6_CTRL_K_MASK            (0x3 << CCM_PLL6_CTRL_K_SHIFT)
 251
 252 #define CCM_GPS_CTRL_RESET (0x1 << 0)
 253 #define CCM_GPS_CTRL_GATE (0x1 << 1)
 254
 255 #define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
 256
 257 #define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
 258 #define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
 259 #define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
 260 #define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
 261 #define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
 262 #define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
 263 #define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
 264 #define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
 265 #define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
 266 #define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
 267 #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
 268 #define CCM_MBUS_CTRL_GATE (0x1 << 31)
 269
 270 #define CCM_NAND_CTRL_ENABLE            (0x1 << 31)
 271
 272 #define CCM_MMC_CTRL_M(x)               ((x) - 1)
 273 #define CCM_MMC_CTRL_OCLK_DLY(x)        ((x) << 8)
 274 #define CCM_MMC_CTRL_N(x)               ((x) << 16)
 275 #define CCM_MMC_CTRL_SCLK_DLY(x)        ((x) << 20)
 276 #define CCM_MMC_CTRL_OSCM24             (0x0 << 24)
 277 #define CCM_MMC_CTRL_PLL6               (0x1 << 24)
 278 #define CCM_MMC_CTRL_PLL5               (0x2 << 24)
 279 #define CCM_MMC_CTRL_ENABLE             (0x1 << 31)
 280
 281 #define CCM_DRAM_GATE_OFFSET_DE_FE1     24 /* Note the order of FE1 and */
 282 #define CCM_DRAM_GATE_OFFSET_DE_FE0     25 /* FE0 is swapped ! */
 283 #define CCM_DRAM_GATE_OFFSET_DE_BE0     26
 284 #define CCM_DRAM_GATE_OFFSET_DE_BE1     27
 285
 286 #define CCM_LCD_CH0_CTRL_PLL3           (0 << 24)
 287 #define CCM_LCD_CH0_CTRL_PLL7           (1 << 24)
 288 #define CCM_LCD_CH0_CTRL_PLL3_2X        (2 << 24)
 289 #define CCM_LCD_CH0_CTRL_PLL7_2X        (3 << 24)
 290 #define CCM_LCD_CH0_CTRL_RST            (0x1 << 30)
 291 #define CCM_LCD_CH0_CTRL_GATE           (0x1 << 31)
 292
 293 #define CCM_LCD_CH1_CTRL_M(n)           ((((n) - 1) & 0xf) << 0)
 294 /* We leave bit 11 set to 0, so sclk1 == sclk2 */
 295 #define CCM_LCD_CH1_CTRL_PLL3           (0 << 24)
 296 #define CCM_LCD_CH1_CTRL_PLL7           (1 << 24)
 297 #define CCM_LCD_CH1_CTRL_PLL3_2X        (2 << 24)
 298 #define CCM_LCD_CH1_CTRL_PLL7_2X        (3 << 24)
 299 /* Enable / disable both ch1 sclk1 and sclk2 at the same time */
 300 #define CCM_LCD_CH1_CTRL_GATE           (0x1 << 31 | 0x1 << 15)
 301
 302 #define CCM_LVDS_CTRL_RST               (1 << 0)
 303
 304 #define CCM_HDMI_CTRL_M(n)              ((((n) - 1) & 0xf) << 0)
 305 #define CCM_HDMI_CTRL_PLL_MASK          (3 << 24)
 306 #define CCM_HDMI_CTRL_PLL3              (0 << 24)
 307 #define CCM_HDMI_CTRL_PLL7              (1 << 24)
 308 #define CCM_HDMI_CTRL_PLL3_2X           (2 << 24)
 309 #define CCM_HDMI_CTRL_PLL7_2X           (3 << 24)
 310 /* No separate ddc gate on sun4i, sun5i and sun7i */
 311 #define CCM_HDMI_CTRL_DDC_GATE          0
 312 #define CCM_HDMI_CTRL_GATE              (0x1 << 31)
 313
 314 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
 315 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
 316 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
 317 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
 318 #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
 319 #define CCM_GMAC_CTRL_RX_CLK_DELAY(x)   ((x) << 5)
 320 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x)   ((x) << 10)
 321
 322 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
 323 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 324 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
 325 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6)
 326 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7)
 327 #define CCM_USB_CTRL_PHYGATE (0x1 << 8)
 328 /* These 3 are sun6i only, define them as 0 on sun4i */
 329 #define CCM_USB_CTRL_PHY0_CLK 0
 330 #define CCM_USB_CTRL_PHY1_CLK 0
 331 #define CCM_USB_CTRL_PHY2_CLK 0
 332
 333 /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
 334 #define CCM_DE_CTRL_M(n)                ((((n) - 1) & 0xf) << 0)
 335 #define CCM_DE_CTRL_PLL_MASK            (3 << 24)
 336 #define CCM_DE_CTRL_PLL3                (0 << 24)
 337 #define CCM_DE_CTRL_PLL7                (1 << 24)
 338 #define CCM_DE_CTRL_PLL5P               (2 << 24)
 339 #define CCM_DE_CTRL_RST                 (1 << 30)
 340 #define CCM_DE_CTRL_GATE                (1 << 31)
 341
 342 #ifndef __ASSEMBLY__
 343 void clock_set_pll1(unsigned int hz);
 344 void clock_set_pll3(unsigned int hz);
 345 unsigned int clock_get_pll5p(void);
 346 unsigned int clock_get_pll6(void);
 347 #endif
 348
 349 #endif /* _SUNXI_CLOCK_SUN4I_H */