arch/arm/include/asm/arch-uniphier/sg-regs.h

   1 /*
   2  * UniPhier SG (SoC Glue) block registers
   3  *
   4  * Copyright (C) 2011-2014 Panasonic Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef ARCH_SG_REGS_H
  10 #define ARCH_SG_REGS_H
  11
  12 /* Base Address */
  13 #define SG_CTRL_BASE                    0x5f800000
  14 #define SG_DBG_BASE                     0x5f900000
  15
  16 /* Revision */
  17 #define SG_REVISION                     (SG_CTRL_BASE | 0x0000)
  18 #define SG_REVISION_TYPE_SHIFT          16
  19 #define SG_REVISION_TYPE_MASK           (0xff << SG_REVISION_TYPE_SHIFT)
  20 #define SG_REVISION_MODEL_SHIFT         8
  21 #define SG_REVISION_MODEL_MASK          (0x3 << SG_REVISION_MODEL_SHIFT)
  22 #define SG_REVISION_REV_SHIFT           0
  23 #define SG_REVISION_REV_MASK            (0x1f << SG_REVISION_REV_SHIFT)
  24
  25 /* Memory Configuration */
  26 #define SG_MEMCONF                      (SG_CTRL_BASE | 0x0400)
  27
  28 #define SG_MEMCONF_CH0_SZ_64M           ((0x0 << 10) | (0x01 << 0))
  29 #define SG_MEMCONF_CH0_SZ_128M          ((0x0 << 10) | (0x02 << 0))
  30 #define SG_MEMCONF_CH0_SZ_256M          ((0x0 << 10) | (0x03 << 0))
  31 #define SG_MEMCONF_CH0_SZ_512M          ((0x1 << 10) | (0x00 << 0))
  32 #define SG_MEMCONF_CH0_SZ_1G            ((0x1 << 10) | (0x01 << 0))
  33 #define SG_MEMCONF_CH0_NUM_1            (0x1 << 8)
  34 #define SG_MEMCONF_CH0_NUM_2            (0x0 << 8)
  35
  36 #define SG_MEMCONF_CH1_SZ_64M           ((0x0 << 11) | (0x01 << 2))
  37 #define SG_MEMCONF_CH1_SZ_128M          ((0x0 << 11) | (0x02 << 2))
  38 #define SG_MEMCONF_CH1_SZ_256M          ((0x0 << 11) | (0x03 << 2))
  39 #define SG_MEMCONF_CH1_SZ_512M          ((0x1 << 11) | (0x00 << 2))
  40 #define SG_MEMCONF_CH1_SZ_1G            ((0x1 << 11) | (0x01 << 2))
  41 #define SG_MEMCONF_CH1_NUM_1            (0x1 << 9)
  42 #define SG_MEMCONF_CH1_NUM_2            (0x0 << 9)
  43
  44 #define SG_MEMCONF_CH2_SZ_64M           ((0x0 << 26) | (0x01 << 16))
  45 #define SG_MEMCONF_CH2_SZ_128M          ((0x0 << 26) | (0x02 << 16))
  46 #define SG_MEMCONF_CH2_SZ_256M          ((0x0 << 26) | (0x03 << 16))
  47 #define SG_MEMCONF_CH2_SZ_512M          ((0x1 << 26) | (0x00 << 16))
  48 #define SG_MEMCONF_CH2_NUM_1            (0x1 << 24)
  49 #define SG_MEMCONF_CH2_NUM_2            (0x0 << 24)
  50
  51 #define SG_MEMCONF_SPARSEMEM            (0x1 << 4)
  52
  53 /* Pin Control */
  54 #define SG_PINCTRL_BASE                 (SG_CTRL_BASE | 0x1000)
  55
  56 #if defined(CONFIG_MACH_PH1_PRO4)
  57 # define SG_PINCTRL(n)                  (SG_PINCTRL_BASE + (n) * 8)
  58 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
  59 # define SG_PINCTRL(n)                  (SG_PINCTRL_BASE + (n) * 4)
  60 #endif
  61
  62 #if defined(CONFIG_MACH_PH1_PRO4)
  63 #define SG_PINSELBITS                   4
  64 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
  65 #define SG_PINSELBITS                   8
  66 #endif
  67
  68 #define SG_PINSEL_ADDR(n)               (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
  69 #define SG_PINSEL_MASK(n)               (~(((1 << (SG_PINSELBITS)) - 1) << \
  70                                                 ((n) * (SG_PINSELBITS) % 32)))
  71 #define SG_PINSEL_MODE(n, mode)         ((mode) << ((n) * (SG_PINSELBITS) % 32))
  72
  73 /* Only for PH1-Pro4 */
  74 #define SG_LOADPINCTRL                  (SG_CTRL_BASE | 0x1700)
  75
  76 /* Input Enable */
  77 #define SG_IECTRL                       (SG_CTRL_BASE | 0x1d00)
  78
  79 /* Pin Monitor */
  80 #define SG_PINMON0                      (SG_DBG_BASE | 0x0100)
  81
  82 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK        (0x3 << 19)
  83 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT     (0x0 << 19)
  84 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A     (0x2 << 19)
  85 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B     (0x3 << 19)
  86
  87 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK         (0x3 << 16)
  88 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ     (0x0 << 16)
  89 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ     (0x1 << 16)
  90 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ      (0x2 << 16)
  91 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ      (0x3 << 16)
  92
  93 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT      (0x0 << 16)
  94 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U   (0x1 << 16)
  95 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ     (0x2 << 16)
  96 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A   (0x3 << 16)
  97
  98 #ifdef __ASSEMBLY__
  99
 100         .macro  set_pinsel, n, value, ra, rd
 101         ldr     \ra, =SG_PINSEL_ADDR(\n)
 102         ldr     \rd, [\ra]
 103         and     \rd, \rd, #SG_PINSEL_MASK(\n)
 104         orr     \rd, \rd, #SG_PINSEL_MODE(\n, \value)
 105         str     \rd, [\ra]
 106         .endm
 107
 108 #else
 109
 110 #include <linux/types.h>
 111 #include <linux/sizes.h>
 112 #include <asm/io.h>
 113
 114 static inline void sg_set_pinsel(int n, int value)
 115 {
 116         writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
 117                | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
 118 }
 119
 120 static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
 121 {
 122         int size_mb = size / num;
 123         u32 ret;
 124
 125         switch (size_mb) {
 126         case SZ_64M:
 127                 ret = SG_MEMCONF_CH0_SZ_64M;
 128                 break;
 129         case SZ_128M:
 130                 ret = SG_MEMCONF_CH0_SZ_128M;
 131                 break;
 132         case SZ_256M:
 133                 ret = SG_MEMCONF_CH0_SZ_256M;
 134                 break;
 135         case SZ_512M:
 136                 ret = SG_MEMCONF_CH0_SZ_512M;
 137                 break;
 138         case SZ_1G:
 139                 ret = SG_MEMCONF_CH0_SZ_1G;
 140                 break;
 141         default:
 142                 BUG();
 143                 break;
 144         }
 145
 146         switch (num) {
 147         case 1:
 148                 ret |= SG_MEMCONF_CH0_NUM_1;
 149                 break;
 150         case 2:
 151                 ret |= SG_MEMCONF_CH0_NUM_2;
 152                 break;
 153         default:
 154                 BUG();
 155                 break;
 156         }
 157         return ret;
 158 }
 159
 160 static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
 161 {
 162         int size_mb = size / num;
 163         u32 ret;
 164
 165         switch (size_mb) {
 166         case SZ_64M:
 167                 ret = SG_MEMCONF_CH1_SZ_64M;
 168                 break;
 169         case SZ_128M:
 170                 ret = SG_MEMCONF_CH1_SZ_128M;
 171                 break;
 172         case SZ_256M:
 173                 ret = SG_MEMCONF_CH1_SZ_256M;
 174                 break;
 175         case SZ_512M:
 176                 ret = SG_MEMCONF_CH1_SZ_512M;
 177                 break;
 178         case SZ_1G:
 179                 ret = SG_MEMCONF_CH1_SZ_1G;
 180                 break;
 181         default:
 182                 BUG();
 183                 break;
 184         }
 185
 186         switch (num) {
 187         case 1:
 188                 ret |= SG_MEMCONF_CH1_NUM_1;
 189                 break;
 190         case 2:
 191                 ret |= SG_MEMCONF_CH1_NUM_2;
 192                 break;
 193         default:
 194                 BUG();
 195                 break;
 196         }
 197         return ret;
 198 }
 199
 200 static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
 201 {
 202         int size_mb = size / num;
 203         u32 ret;
 204
 205         switch (size_mb) {
 206         case SZ_64M:
 207                 ret = SG_MEMCONF_CH2_SZ_64M;
 208                 break;
 209         case SZ_128M:
 210                 ret = SG_MEMCONF_CH2_SZ_128M;
 211                 break;
 212         case SZ_256M:
 213                 ret = SG_MEMCONF_CH2_SZ_256M;
 214                 break;
 215         case SZ_512M:
 216                 ret = SG_MEMCONF_CH2_SZ_512M;
 217                 break;
 218         default:
 219                 BUG();
 220                 break;
 221         }
 222
 223         switch (num) {
 224         case 1:
 225                 ret |= SG_MEMCONF_CH2_NUM_1;
 226                 break;
 227         case 2:
 228                 ret |= SG_MEMCONF_CH2_NUM_2;
 229                 break;
 230         default:
 231                 BUG();
 232                 break;
 233         }
 234         return ret;
 235 }
 236 #endif /* __ASSEMBLY__ */
 237
 238 #endif /* ARCH_SG_REGS_H */