arch/arm/include/asm/ti-common/keystone_net.h

   1 /*
   2  * emac definitions for keystone2 devices
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _KEYSTONE_NET_H_
  11 #define _KEYSTONE_NET_H_
  12
  13 #include <asm/io.h>
  14
  15 /* EMAC */
  16 #ifdef CONFIG_KSNET_NETCP_V1_0
  17
  18 #define GBETH_BASE                      (CONFIG_KSNET_NETCP_BASE + 0x00090000)
  19 #define EMAC_EMACSL_BASE_ADDR           (GBETH_BASE + 0x900)
  20 #define EMAC_MDIO_BASE_ADDR             (GBETH_BASE + 0x300)
  21 #define EMAC_SGMII_BASE_ADDR            (GBETH_BASE + 0x100)
  22 #define DEVICE_EMACSL_BASE(x)           (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
  23
  24 /* Register offsets */
  25 #define CPGMACSL_REG_CTL                0x04
  26 #define CPGMACSL_REG_STATUS             0x08
  27 #define CPGMACSL_REG_RESET              0x0c
  28 #define CPGMACSL_REG_MAXLEN             0x10
  29
  30 #elif defined CONFIG_KSNET_NETCP_V1_5
  31
  32 #define GBETH_BASE                      (CONFIG_KSNET_NETCP_BASE + 0x00200000)
  33 #define CPGMACSL_REG_RX_PRI_MAP         0x020
  34 #define EMAC_EMACSL_BASE_ADDR           (GBETH_BASE + 0x22000)
  35 #define EMAC_MDIO_BASE_ADDR             (GBETH_BASE + 0x00f00)
  36 #define EMAC_SGMII_BASE_ADDR            (GBETH_BASE + 0x00100)
  37 #define DEVICE_EMACSL_BASE(x)           (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
  38
  39 /* Register offsets */
  40 #define CPGMACSL_REG_CTL                0x330
  41 #define CPGMACSL_REG_STATUS             0x334
  42 #define CPGMACSL_REG_RESET              0x338
  43 #define CPGMACSL_REG_MAXLEN             0x024
  44
  45 #endif
  46
  47 #define KEYSTONE2_EMAC_GIG_ENABLE
  48
  49 #define MAC_ID_BASE_ADDR                CONFIG_KSNET_MAC_ID_BASE
  50
  51 /* MDIO module input frequency */
  52 #define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
  53 /* MDIO clock output frequency */
  54 #define EMAC_MDIO_CLOCK_FREQ            2500000 /* 2.5 MHz */
  55
  56 /* MII Status Register */
  57 #define MII_STATUS_REG                  1
  58 #define MII_STATUS_LINK_MASK            0x4
  59
  60 #define MDIO_CONTROL_IDLE               0x80000000
  61 #define MDIO_CONTROL_ENABLE             0x40000000
  62 #define MDIO_CONTROL_FAULT_ENABLE       0x40000
  63 #define MDIO_CONTROL_FAULT              0x80000
  64 #define MDIO_USERACCESS0_GO             0x80000000
  65 #define MDIO_USERACCESS0_WRITE_READ     0x0
  66 #define MDIO_USERACCESS0_WRITE_WRITE    0x40000000
  67 #define MDIO_USERACCESS0_ACK            0x20000000
  68
  69 #define EMAC_MACCONTROL_MIIEN_ENABLE            0x20
  70 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE       0x1
  71 #define EMAC_MACCONTROL_GIGABIT_ENABLE          BIT(7)
  72 #define EMAC_MACCONTROL_GIGFORCE                BIT(17)
  73 #define EMAC_MACCONTROL_RMIISPEED_100           BIT(15)
  74
  75 #define EMAC_MIN_ETHERNET_PKT_SIZE              60
  76
  77 struct mac_sl_cfg {
  78         u_int32_t max_rx_len;   /* Maximum receive packet length. */
  79         u_int32_t ctl;          /* Control bitfield */
  80 };
  81
  82 /**
  83  * Definition: Control bitfields used in the ctl field of mac_sl_cfg
  84  */
  85 #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES     BIT(24)
  86 #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES       BIT(23)
  87 #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES       BIT(22)
  88 #define GMACSL_RX_ENABLE_EXT_CTL                BIT(18)
  89 #define GMACSL_RX_ENABLE_GIG_FORCE              BIT(17)
  90 #define GMACSL_RX_ENABLE_IFCTL_B                BIT(16)
  91 #define GMACSL_RX_ENABLE_IFCTL_A                BIT(15)
  92 #define GMACSL_RX_ENABLE_CMD_IDLE               BIT(11)
  93 #define GMACSL_TX_ENABLE_SHORT_GAP              BIT(10)
  94 #define GMACSL_ENABLE_GIG_MODE                  BIT(7)
  95 #define GMACSL_TX_ENABLE_PACE                   BIT(6)
  96 #define GMACSL_ENABLE                           BIT(5)
  97 #define GMACSL_TX_ENABLE_FLOW_CTL               BIT(4)
  98 #define GMACSL_RX_ENABLE_FLOW_CTL               BIT(3)
  99 #define GMACSL_ENABLE_LOOPBACK                  BIT(1)
 100 #define GMACSL_ENABLE_FULL_DUPLEX               BIT(0)
 101
 102 /* EMAC SL function return values */
 103 #define GMACSL_RET_OK                           0
 104 #define GMACSL_RET_INVALID_PORT                 -1
 105 #define GMACSL_RET_WARN_RESET_INCOMPLETE        -2
 106 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG          -3
 107 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE     -4
 108
 109 /* EMAC SL register definitions */
 110 #define DEVICE_EMACSL_RESET_POLL_COUNT          100
 111
 112 /* Soft reset register values */
 113 #define CPGMAC_REG_RESET_VAL_RESET_MASK         BIT(0)
 114 #define CPGMAC_REG_RESET_VAL_RESET              BIT(0)
 115 #define CPGMAC_REG_MAXLEN_LEN                   0x3fff
 116
 117 /* CPSW */
 118 /* Control bitfields */
 119 #define CPSW_CTL_P2_PASS_PRI_TAGGED             BIT(5)
 120 #define CPSW_CTL_P1_PASS_PRI_TAGGED             BIT(4)
 121 #define CPSW_CTL_P0_PASS_PRI_TAGGED             BIT(3)
 122 #define CPSW_CTL_P0_ENABLE                      BIT(2)
 123 #define CPSW_CTL_VLAN_AWARE                     BIT(1)
 124 #define CPSW_CTL_FIFO_LOOPBACK                  BIT(0)
 125
 126 #define DEVICE_CPSW_NUM_PORTS                   CONFIG_KSNET_CPSW_NUM_PORTS
 127 #define DEVICE_N_GMACSL_PORTS                   (DEVICE_CPSW_NUM_PORTS - 1)
 128
 129 #ifdef CONFIG_KSNET_NETCP_V1_0
 130
 131 #define DEVICE_CPSW_BASE                        (GBETH_BASE + 0x800)
 132 #define CPSW_REG_CTL                            0x004
 133 #define CPSW_REG_STAT_PORT_EN                   0x00c
 134 #define CPSW_REG_MAXLEN                         0x040
 135 #define CPSW_REG_ALE_CONTROL                    0x608
 136 #define CPSW_REG_ALE_PORTCTL(x)                 (0x640 + (x) * 4)
 137 #define CPSW_REG_VAL_STAT_ENABLE_ALL            0xf
 138
 139 #elif defined CONFIG_KSNET_NETCP_V1_5
 140
 141 #define DEVICE_CPSW_BASE                        (GBETH_BASE + 0x20000)
 142 #define CPSW_REG_CTL                            0x00004
 143 #define CPSW_REG_STAT_PORT_EN                   0x00014
 144 #define CPSW_REG_MAXLEN                         0x01024
 145 #define CPSW_REG_ALE_CONTROL                    0x1e008
 146 #define CPSW_REG_ALE_PORTCTL(x)                 (0x1e040 + (x) * 4)
 147 #define CPSW_REG_VAL_STAT_ENABLE_ALL            0x1ff
 148
 149 #endif
 150
 151 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE   ((u_int32_t)0xc0000000)
 152 #define CPSW_REG_VAL_ALE_CTL_BYPASS             ((u_int32_t)0x00000010)
 153 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE       0x3
 154
 155 #define target_get_switch_ctl()                 CPSW_CTL_P0_ENABLE
 156 #define SWITCH_MAX_PKT_SIZE                     9000
 157
 158 /* SGMII */
 159 #define SGMII_REG_STATUS_LOCK                   BIT(4)
 160 #define SGMII_REG_STATUS_LINK                   BIT(0)
 161 #define SGMII_REG_STATUS_AUTONEG                BIT(2)
 162 #define SGMII_REG_CONTROL_AUTONEG               BIT(0)
 163 #define SGMII_REG_CONTROL_MASTER                BIT(5)
 164 #define SGMII_REG_MR_ADV_ENABLE                 BIT(0)
 165 #define SGMII_REG_MR_ADV_LINK                   BIT(15)
 166 #define SGMII_REG_MR_ADV_FULL_DUPLEX            BIT(12)
 167 #define SGMII_REG_MR_ADV_GIG_MODE               BIT(11)
 168
 169 #define SGMII_LINK_MAC_MAC_AUTONEG              0
 170 #define SGMII_LINK_MAC_PHY                      1
 171 #define SGMII_LINK_MAC_MAC_FORCED               2
 172 #define SGMII_LINK_MAC_FIBER                    3
 173 #define SGMII_LINK_MAC_PHY_FORCED               4
 174
 175 #ifdef CONFIG_KSNET_NETCP_V1_0
 176 #define SGMII_OFFSET(x)         ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
 177 #elif defined CONFIG_KSNET_NETCP_V1_5
 178 #define SGMII_OFFSET(x)         ((x) * 0x100)
 179 #endif
 180
 181 #define SGMII_IDVER_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
 182 #define SGMII_SRESET_REG(x)     (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
 183 #define SGMII_CTL_REG(x)        (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
 184 #define SGMII_STATUS_REG(x)     (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
 185 #define SGMII_MRADV_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
 186 #define SGMII_LPADV_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
 187 #define SGMII_TXCFG_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
 188 #define SGMII_RXCFG_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
 189 #define SGMII_AUXCFG_REG(x)     (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
 190
 191 /* PSS */
 192 #ifdef CONFIG_KSNET_NETCP_V1_0
 193
 194 #define DEVICE_PSTREAM_CFG_REG_ADDR     (CONFIG_KSNET_NETCP_BASE + 0x604)
 195 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI       0x06060606
 196 #define hw_config_streaming_switch()\
 197         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
 198
 199 #elif defined CONFIG_KSNET_NETCP_V1_5
 200
 201 #define DEVICE_PSTREAM_CFG_REG_ADDR     (CONFIG_KSNET_NETCP_BASE + 0x500)
 202 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI       0x0
 203
 204 #define hw_config_streaming_switch()\
 205         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 206                DEVICE_PSTREAM_CFG_REG_ADDR);\
 207         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 208                DEVICE_PSTREAM_CFG_REG_ADDR+4);\
 209         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 210                DEVICE_PSTREAM_CFG_REG_ADDR+8);\
 211         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 212                DEVICE_PSTREAM_CFG_REG_ADDR+12);
 213
 214 #endif
 215
 216 /* EMAC MDIO Registers Structure */
 217 struct mdio_regs {
 218         u32 version;
 219         u32 control;
 220         u32 alive;
 221         u32 link;
 222         u32 linkintraw;
 223         u32 linkintmasked;
 224         u32 rsvd0[2];
 225         u32 userintraw;
 226         u32 userintmasked;
 227         u32 userintmaskset;
 228         u32 userintmaskclear;
 229         u32 rsvd1[20];
 230         u32 useraccess0;
 231         u32 userphysel0;
 232         u32 useraccess1;
 233         u32 userphysel1;
 234 };
 235
 236 struct eth_priv_t {
 237         char int_name[32];
 238         int rx_flow;
 239         int phy_addr;
 240         int slave_port;
 241         int sgmii_link_type;
 242         struct phy_device *phy_dev;
 243 };
 244
 245 int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
 246 void sgmii_serdes_setup_156p25mhz(void);
 247 void sgmii_serdes_shutdown(void);
 248
 249 #endif  /* _KEYSTONE_NET_H_ */