3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/system.h>
26 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
28 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
29 #define CACHE_SETUP 0x1a
31 #define CACHE_SETUP 0x1e
34 DECLARE_GLOBAL_DATA_PTR;
36 void __arm_init_before_mmu(void)
39 void arm_init_before_mmu(void)
40 __attribute__((weak, alias("__arm_init_before_mmu")));
42 static inline void dram_bank_mmu_setup(int bank)
44 u32 *page_table = (u32 *)gd->tlb_addr;
48 debug("%s: bank: %d\n", __func__, bank);
49 for (i = bd->bi_dram[bank].start >> 20;
50 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
52 page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
56 /* to activate the MMU we need to set up virtual memory: use 1M areas */
57 static inline void mmu_setup(void)
59 u32 *page_table = (u32 *)gd->tlb_addr;
63 arm_init_before_mmu();
64 /* Set up an identity-mapping for all 4GB, rw for everyone */
65 for (i = 0; i < 4096; i++)
66 page_table[i] = i << 20 | (3 << 10) | 0x12;
68 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
69 dram_bank_mmu_setup(i);
73 /* Copy the page table address to cp15 */
74 "mcr p15, 0, %0, c2, c0, 0\n"
75 /* Set the access control to all-supervisor */
76 "mcr p15, 0, %1, c3, c0, 0\n"
78 : "r"(page_table), "r"(~0)
80 /* and enable the mmu */
81 reg = get_cr(); /* get control reg. */
85 static int mmu_enabled(void)
87 return get_cr() & CR_M;
90 /* cache_bit must be either CR_I or CR_C */
91 static void cache_enable(uint32_t cache_bit)
95 /* The data cache is not active unless the mmu is enabled too */
96 if ((cache_bit == CR_C) && !mmu_enabled())
98 reg = get_cr(); /* get control reg. */
99 set_cr(reg | cache_bit);
102 /* cache_bit must be either CR_I or CR_C */
103 static void cache_disable(uint32_t cache_bit)
107 if (cache_bit == CR_C) {
108 /* if cache isn;t enabled no need to disable */
110 if ((reg & CR_C) != CR_C)
112 /* if disabling data cache, disable mmu too */
117 set_cr(reg & ~cache_bit);
121 #ifdef CONFIG_SYS_ICACHE_OFF
122 void icache_enable (void)
127 void icache_disable (void)
132 int icache_status (void)
134 return 0; /* always off */
137 void icache_enable(void)
142 void icache_disable(void)
147 int icache_status(void)
149 return (get_cr() & CR_I) != 0;
153 #ifdef CONFIG_SYS_DCACHE_OFF
154 void dcache_enable (void)
159 void dcache_disable (void)
164 int dcache_status (void)
166 return 0; /* always off */
169 void dcache_enable(void)
174 void dcache_disable(void)
179 int dcache_status(void)
181 return (get_cr() & CR_C) != 0;