arch/arm/mach-keystone/clock.c

   1 /*
   2  * Keystone2: pll initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/clock_defs.h>
  13
  14 #define MAX_SPEEDS              13
  15
  16 static void wait_for_completion(const struct pll_init_data *data)
  17 {
  18         int i;
  19         for (i = 0; i < 100; i++) {
  20                 sdelay(450);
  21                 if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
  22                         break;
  23         }
  24 }
  25
  26 void init_pll(const struct pll_init_data *data)
  27 {
  28         u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
  29
  30         pllm = data->pll_m - 1;
  31         plld = (data->pll_d - 1) & PLL_DIV_MASK;
  32         pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
  33
  34         if (data->pll == MAIN_PLL) {
  35                 /* The requered delay before main PLL configuration */
  36                 sdelay(210000);
  37
  38                 tmp = pllctl_reg_read(data->pll, secctl);
  39
  40                 if (tmp & (PLLCTL_BYPASS)) {
  41                         setbits_le32(keystone_pll_regs[data->pll].reg1,
  42                                      BIT(MAIN_ENSAT_OFFSET));
  43
  44                         pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
  45                                            PLLCTL_PLLENSRC);
  46                         sdelay(340);
  47
  48                         pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
  49                         pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
  50                         sdelay(21000);
  51
  52                         pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
  53                 } else {
  54                         pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
  55                                            PLLCTL_PLLENSRC);
  56                         sdelay(340);
  57                 }
  58
  59                 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
  60
  61                 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
  62                                 PLLM_MULT_HI_SMASK, (pllm << 6));
  63
  64                 /* Set the BWADJ     (12 bit field)  */
  65                 tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
  66                 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
  67                                 PLL_BWADJ_LO_SMASK,
  68                                 (tmp_ctl << PLL_BWADJ_LO_SHIFT));
  69                 clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
  70                                 PLL_BWADJ_HI_MASK,
  71                                 (tmp_ctl >> 8));
  72
  73                 /*
  74                  * Set the pll divider (6 bit field) *
  75                  * PLLD[5:0] is located in MAINPLLCTL0
  76                  */
  77                 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
  78                                 PLL_DIV_MASK, plld);
  79
  80                 /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
  81                 pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
  82                                (pllod << PLL_CLKOD_SHIFT));
  83                 wait_for_completion(data);
  84
  85                 pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
  86                 pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
  87                 pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
  88                 pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
  89                 pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
  90
  91                 pllctl_reg_setbits(data->pll, alnctl, 0x1f);
  92
  93                 /*
  94                  * Set GOSET bit in PLLCMD to initiate the GO operation
  95                  * to change the divide
  96                  */
  97                 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
  98                 sdelay(1500); /* wait for the phase adj */
  99                 wait_for_completion(data);
 100
 101                 /* Reset PLL */
 102                 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
 103                 sdelay(21000);  /* Wait for a minimum of 7 us*/
 104                 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
 105                 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
 106
 107                 pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
 108
 109                 tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
 110
 111 #ifndef CONFIG_SOC_K2E
 112         } else if (data->pll == TETRIS_PLL) {
 113                 bwadj = pllm >> 1;
 114                 /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
 115                 setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
 116                 /*
 117                  * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 118                  * only applicable for Kepler
 119                  */
 120                 clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 121                 /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
 122                 setbits_le32(keystone_pll_regs[data->pll].reg1 ,
 123                              PLL_PLLRST | PLLCTL_ENSAT);
 124
 125                 /*
 126                  * 3 Program PLLM and PLLD in PLLCTL0 register
 127                  * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
 128                  * PLLCTL1 register. BWADJ value must be set
 129                  * to ((PLLM + 1) >> 1) – 1)
 130                  */
 131                 tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
 132                         (pllm << 6) |
 133                         (plld & PLL_DIV_MASK) |
 134                         (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
 135                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 136
 137                 /* Set BWADJ[11:8] bits */
 138                 tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 139                 tmp &= ~(PLL_BWADJ_HI_MASK);
 140                 tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
 141                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 142                 /*
 143                  * 5 Wait for at least 5 us based on the reference
 144                  * clock (PLL reset time)
 145                  */
 146                 sdelay(21000);  /* Wait for a minimum of 7 us*/
 147
 148                 /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
 149                 clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
 150                 /*
 151                  * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
 152                  * (PLL lock time)
 153                  */
 154                 sdelay(105000);
 155                 /* 8 disable bypass */
 156                 clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 157                 /*
 158                  * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 159                  * only applicable for Kepler
 160                  */
 161                 setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 162 #endif
 163         } else {
 164                 setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
 165                 /*
 166                  * process keeps state of Bypass bit while programming
 167                  * all other DDR PLL settings
 168                  */
 169                 tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
 170                 tmp &= PLLCTL_BYPASS;   /* clear everything except Bypass */
 171
 172                 /*
 173                  * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
 174                  * bypass disabled
 175                  */
 176                 bwadj = pllm >> 1;
 177                 tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
 178                         (pllm << PLL_MULT_SHIFT) |
 179                         (plld & PLL_DIV_MASK) |
 180                         (pllod << PLL_CLKOD_SHIFT);
 181                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 182
 183                 /* Set BWADJ[11:8] bits */
 184                 tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 185                 tmp &= ~(PLL_BWADJ_HI_MASK);
 186                 tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 187
 188                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 189
 190                 /* Reset bit: bit 14 for both DDR3 & PASS PLL */
 191                 tmp = PLL_PLLRST;
 192                 /* Set RESET bit = 1 */
 193                 setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 194                 /* Wait for a minimum of 7 us*/
 195                 sdelay(21000);
 196                 /* Clear RESET bit */
 197                 clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 198                 sdelay(105000);
 199
 200                 /* clear BYPASS (Enable PLL Mode) */
 201                 clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 202                 sdelay(21000);  /* Wait for a minimum of 7 us*/
 203         }
 204
 205         /*
 206          * This is required to provide a delay between multiple
 207          * consequent PPL configurations
 208          */
 209         sdelay(210000);
 210 }
 211
 212 void init_plls(int num_pll, struct pll_init_data *config)
 213 {
 214         int i;
 215
 216         for (i = 0; i < num_pll; i++)
 217                 init_pll(&config[i]);
 218 }
 219
 220 static int get_max_speed(u32 val, int *speeds)
 221 {
 222         int j;
 223
 224         if (!val)
 225                 return speeds[0];
 226
 227         for (j = 1; j < MAX_SPEEDS; j++) {
 228                 if (val == 1)
 229                         return speeds[j];
 230                 val >>= 1;
 231         }
 232
 233         return SPD800;
 234 }
 235
 236 #ifdef CONFIG_SOC_K2HK
 237 static u32 read_efuse_bootrom(void)
 238 {
 239         return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
 240                 __raw_readl(KS2_REV1_DEVSPEED);
 241 }
 242 #else
 243 static inline u32 read_efuse_bootrom(void)
 244 {
 245         return __raw_readl(KS2_EFUSE_BOOTROM);
 246 }
 247 #endif
 248
 249 #ifndef CONFIG_SOC_K2E
 250 inline int get_max_arm_speed(void)
 251 {
 252         return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
 253 }
 254 #endif
 255
 256 inline int get_max_dev_speed(void)
 257 {
 258         return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
 259 }
 260
 261 void pass_pll_pa_clk_enable(void)
 262 {
 263         u32 reg;
 264
 265         reg = readl(keystone_pll_regs[PASS_PLL].reg1);
 266
 267         reg |= PLLCTL_PAPLL;
 268         writel(reg, keystone_pll_regs[PASS_PLL].reg1);
 269
 270         /* wait till clock is enabled */
 271         sdelay(15000);
 272 }