arch/arm/mach-keystone/include/mach/hardware-k2hk.h

   1 /*
   2  * K2HK: SoC definitions
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
  11 #define __ASM_ARCH_HARDWARE_K2HK_H
  12
  13 #define KS2_ARM_PLL_EN                  BIT(13)
  14
  15 /* PA SS Registers */
  16 #define KS2_PASS_BASE                   0x02000000
  17
  18 /* PLL control registers */
  19 #define KS2_DDR3BPLLCTL0                (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
  20 #define KS2_DDR3BPLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
  21
  22 /* Power and Sleep Controller (PSC) Domains */
  23 #define KS2_LPSC_MOD                    0
  24 #define KS2_LPSC_DUMMY1                 1
  25 #define KS2_LPSC_USB                    2
  26 #define KS2_LPSC_EMIF25_SPI             3
  27 #define KS2_LPSC_TSIP                   4
  28 #define KS2_LPSC_DEBUGSS_TRC            5
  29 #define KS2_LPSC_TETB_TRC               6
  30 #define KS2_LPSC_PKTPROC                7
  31 #define KS2_LPSC_PA                     KS2_LPSC_PKTPROC
  32 #define KS2_LPSC_SGMII                  8
  33 #define KS2_LPSC_CPGMAC                 KS2_LPSC_SGMII
  34 #define KS2_LPSC_CRYPTO                 9
  35 #define KS2_LPSC_PCIE                   10
  36 #define KS2_LPSC_SRIO                   11
  37 #define KS2_LPSC_VUSR0                  12
  38 #define KS2_LPSC_CHIP_SRSS              13
  39 #define KS2_LPSC_MSMC                   14
  40 #define KS2_LPSC_GEM_1                  16
  41 #define KS2_LPSC_GEM_2                  17
  42 #define KS2_LPSC_GEM_3                  18
  43 #define KS2_LPSC_GEM_4                  19
  44 #define KS2_LPSC_GEM_5                  20
  45 #define KS2_LPSC_GEM_6                  21
  46 #define KS2_LPSC_GEM_7                  22
  47 #define KS2_LPSC_EMIF4F_DDR3A           23
  48 #define KS2_LPSC_EMIF4F_DDR3B           24
  49 #define KS2_LPSC_TAC                    25
  50 #define KS2_LPSC_RAC                    26
  51 #define KS2_LPSC_RAC_1                  27
  52 #define KS2_LPSC_FFTC_A                 28
  53 #define KS2_LPSC_FFTC_B                 29
  54 #define KS2_LPSC_FFTC_C                 30
  55 #define KS2_LPSC_FFTC_D                 31
  56 #define KS2_LPSC_FFTC_E                 32
  57 #define KS2_LPSC_FFTC_F                 33
  58 #define KS2_LPSC_AI2                    34
  59 #define KS2_LPSC_TCP3D_0                35
  60 #define KS2_LPSC_TCP3D_1                36
  61 #define KS2_LPSC_TCP3D_2                37
  62 #define KS2_LPSC_TCP3D_3                38
  63 #define KS2_LPSC_VCP2X4_A               39
  64 #define KS2_LPSC_CP2X4_B                40
  65 #define KS2_LPSC_VCP2X4_C               41
  66 #define KS2_LPSC_VCP2X4_D               42
  67 #define KS2_LPSC_VCP2X4_E               43
  68 #define KS2_LPSC_VCP2X4_F               44
  69 #define KS2_LPSC_VCP2X4_G               45
  70 #define KS2_LPSC_VCP2X4_H               46
  71 #define KS2_LPSC_BCP                    47
  72 #define KS2_LPSC_DXB                    48
  73 #define KS2_LPSC_VUSR1                  49
  74 #define KS2_LPSC_XGE                    50
  75 #define KS2_LPSC_ARM_SREFLEX            51
  76
  77 /* DDR3B definitions */
  78 #define KS2_DDR3B_EMIF_CTRL_BASE        0x21020000
  79 #define KS2_DDR3B_EMIF_DATA_BASE        0x60000000
  80 #define KS2_DDR3B_DDRPHYC               0x02328000
  81
  82 #define KS2_CIC2_DDR3_ECC_IRQ_NUM       0x0D3 /* DDR3 ECC system irq number */
  83 #define KS2_CIC2_DDR3_ECC_CHAN_NUM      0x01D /* DDR3 ECC int mapped to CIC2
  84                                                  channel 29 */
  85
  86 /* SGMII SerDes */
  87 #define KS2_LANES_PER_SGMII_SERDES      4
  88
  89 /* Number of DSP cores */
  90 #define KS2_NUM_DSPS                    8
  91
  92 /* NETCP pktdma */
  93 #define KS2_NETCP_PDMA_CTRL_BASE        0x02004000
  94 #define KS2_NETCP_PDMA_TX_BASE          0x02004400
  95 #define KS2_NETCP_PDMA_TX_CH_NUM        9
  96 #define KS2_NETCP_PDMA_RX_BASE          0x02004800
  97 #define KS2_NETCP_PDMA_RX_CH_NUM        26
  98 #define KS2_NETCP_PDMA_SCHED_BASE       0x02004c00
  99 #define KS2_NETCP_PDMA_RX_FLOW_BASE     0x02005000
 100 #define KS2_NETCP_PDMA_RX_FLOW_NUM      32
 101 #define KS2_NETCP_PDMA_TX_SND_QUEUE     648
 102
 103 /* NETCP */
 104 #define KS2_NETCP_BASE                  0x02000000
 105
 106 #endif /* __ASM_ARCH_HARDWARE_H */