arch/arm/mach-keystone/include/mach/hardware.h

   1 /*
   2  * Keystone2: Common SoC definitions, structures etc.
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #ifndef __ASM_ARCH_HARDWARE_H
  10 #define __ASM_ARCH_HARDWARE_H
  11
  12 #include <config.h>
  13
  14 #ifndef __ASSEMBLY__
  15
  16 #include <linux/sizes.h>
  17 #include <asm/io.h>
  18
  19 #define REG(addr)        (*(volatile unsigned int *)(addr))
  20 #define REG_P(addr)      ((volatile unsigned int *)(addr))
  21
  22 typedef volatile unsigned int   dv_reg;
  23 typedef volatile unsigned int   *dv_reg_p;
  24
  25 #endif
  26
  27 #define         BIT(x)  (1 << (x))
  28
  29 #define KS2_DDRPHY_PIR_OFFSET           0x04
  30 #define KS2_DDRPHY_PGCR0_OFFSET         0x08
  31 #define KS2_DDRPHY_PGCR1_OFFSET         0x0C
  32 #define KS2_DDRPHY_PGSR0_OFFSET         0x10
  33 #define KS2_DDRPHY_PGSR1_OFFSET         0x14
  34 #define KS2_DDRPHY_PLLCR_OFFSET         0x18
  35 #define KS2_DDRPHY_PTR0_OFFSET          0x1C
  36 #define KS2_DDRPHY_PTR1_OFFSET          0x20
  37 #define KS2_DDRPHY_PTR2_OFFSET          0x24
  38 #define KS2_DDRPHY_PTR3_OFFSET          0x28
  39 #define KS2_DDRPHY_PTR4_OFFSET          0x2C
  40 #define KS2_DDRPHY_DCR_OFFSET           0x44
  41
  42 #define KS2_DDRPHY_DTPR0_OFFSET         0x48
  43 #define KS2_DDRPHY_DTPR1_OFFSET         0x4C
  44 #define KS2_DDRPHY_DTPR2_OFFSET         0x50
  45
  46 #define KS2_DDRPHY_MR0_OFFSET           0x54
  47 #define KS2_DDRPHY_MR1_OFFSET           0x58
  48 #define KS2_DDRPHY_MR2_OFFSET           0x5C
  49 #define KS2_DDRPHY_DTCR_OFFSET          0x68
  50 #define KS2_DDRPHY_PGCR2_OFFSET         0x8C
  51
  52 #define KS2_DDRPHY_ZQ0CR1_OFFSET        0x184
  53 #define KS2_DDRPHY_ZQ1CR1_OFFSET        0x194
  54 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
  55 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
  56
  57 #define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
  58
  59 #define IODDRM_MASK                     0x00000180
  60 #define ZCKSEL_MASK                     0x01800000
  61 #define CL_MASK                         0x00000072
  62 #define WR_MASK                         0x00000E00
  63 #define BL_MASK                         0x00000003
  64 #define RRMODE_MASK                     0x00040000
  65 #define UDIMM_MASK                      0x20000000
  66 #define BYTEMASK_MASK                   0x0003FC00
  67 #define MPRDQ_MASK                      0x00000080
  68 #define PDQ_MASK                        0x00000070
  69 #define NOSRA_MASK                      0x08000000
  70 #define ECC_MASK                        0x00000001
  71
  72 /* DDR3 definitions */
  73 #define KS2_DDR3A_EMIF_CTRL_BASE        0x21010000
  74 #define KS2_DDR3A_EMIF_DATA_BASE        0x80000000
  75 #define KS2_DDR3A_DDRPHYC               0x02329000
  76
  77 #define KS2_DDR3_MIDR_OFFSET            0x00
  78 #define KS2_DDR3_STATUS_OFFSET          0x04
  79 #define KS2_DDR3_SDCFG_OFFSET           0x08
  80 #define KS2_DDR3_SDRFC_OFFSET           0x10
  81 #define KS2_DDR3_SDTIM1_OFFSET          0x18
  82 #define KS2_DDR3_SDTIM2_OFFSET          0x1C
  83 #define KS2_DDR3_SDTIM3_OFFSET          0x20
  84 #define KS2_DDR3_SDTIM4_OFFSET          0x28
  85 #define KS2_DDR3_PMCTL_OFFSET           0x38
  86 #define KS2_DDR3_ZQCFG_OFFSET           0xC8
  87
  88 #define KS2_DDR3_PLLCTRL_PHY_RESET      0x80000000
  89
  90 /* DDR3 ECC */
  91 #define KS2_DDR3_ECC_INT_STATUS_OFFSET                  0x0AC
  92 #define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET          0x0B4
  93 #define KS2_DDR3_ECC_CTRL_OFFSET                        0x110
  94 #define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET                 0x114
  95 #define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET             0x130
  96 #define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET        0x13C
  97
  98 /* DDR3 ECC Interrupt Status register */
  99 #define KS2_DDR3_1B_ECC_ERR_SYS         BIT(5)
 100 #define KS2_DDR3_2B_ECC_ERR_SYS         BIT(4)
 101 #define KS2_DDR3_WR_ECC_ERR_SYS         BIT(3)
 102
 103 /* DDR3 ECC Control register */
 104 #define KS2_DDR3_ECC_EN                 BIT(31)
 105 #define KS2_DDR3_ECC_ADDR_RNG_PROT      BIT(30)
 106 #define KS2_DDR3_ECC_VERIFY_EN          BIT(29)
 107 #define KS2_DDR3_ECC_RMW_EN             BIT(28)
 108 #define KS2_DDR3_ECC_ADDR_RNG_1_EN      BIT(0)
 109
 110 #define KS2_DDR3_ECC_ENABLE             (KS2_DDR3_ECC_EN | \
 111                                         KS2_DDR3_ECC_ADDR_RNG_PROT | \
 112                                         KS2_DDR3_ECC_VERIFY_EN)
 113
 114 /* EDMA */
 115 #define KS2_EDMA0_BASE                  0x02700000
 116
 117 /* EDMA3 register offsets */
 118 #define KS2_EDMA_QCHMAP0                0x0200
 119 #define KS2_EDMA_IPR                    0x1068
 120 #define KS2_EDMA_ICR                    0x1070
 121 #define KS2_EDMA_QEECR                  0x1088
 122 #define KS2_EDMA_QEESR                  0x108c
 123 #define KS2_EDMA_PARAM_1(x)             (0x4020 + (4 * x))
 124
 125 /* NETCP pktdma */
 126 #define KS2_NETCP_PDMA_RX_FREE_QUEUE    4001
 127 #define KS2_NETCP_PDMA_RX_RCV_QUEUE     4002
 128
 129 /* Chip Interrupt Controller */
 130 #define KS2_CIC2_BASE                   0x02608000
 131
 132 /* Chip Interrupt Controller register offsets */
 133 #define KS2_CIC_CTRL                    0x04
 134 #define KS2_CIC_HOST_CTRL               0x0C
 135 #define KS2_CIC_GLOBAL_ENABLE           0x10
 136 #define KS2_CIC_SYS_ENABLE_IDX_SET      0x28
 137 #define KS2_CIC_HOST_ENABLE_IDX_SET     0x34
 138 #define KS2_CIC_CHAN_MAP(n)             (0x0400 + (n << 2))
 139
 140 #define KS2_UART0_BASE                  0x02530c00
 141 #define KS2_UART1_BASE                  0x02531000
 142
 143 /* Boot Config */
 144 #define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
 145 #define KS2_JTAG_ID_REG                 (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 146 #define KS2_DEVSTAT                     (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
 147 #define KS2_DEVCFG                      (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
 148
 149 /* PSC */
 150 #define KS2_PSC_BASE                    0x02350000
 151 #define KS2_LPSC_GEM_0                  15
 152 #define KS2_LPSC_TETRIS                 52
 153 #define KS2_TETRIS_PWR_DOMAIN           31
 154
 155 /* Chip configuration unlock codes and registers */
 156 #define KS2_KICK0                       (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
 157 #define KS2_KICK1                       (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
 158 #define KS2_KICK0_MAGIC                 0x83e70b13
 159 #define KS2_KICK1_MAGIC                 0x95a4f1e0
 160
 161 /* PLL control registers */
 162 #define KS2_MAINPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
 163 #define KS2_MAINPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
 164 #define KS2_PASSPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
 165 #define KS2_PASSPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
 166 #define KS2_DDR3APLLCTL0                (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
 167 #define KS2_DDR3APLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
 168 #define KS2_ARMPLLCTL0                  (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 169 #define KS2_ARMPLLCTL1                  (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
 170
 171 #define KS2_PLL_CNTRL_BASE              0x02310000
 172 #define KS2_CLOCK_BASE                  KS2_PLL_CNTRL_BASE
 173 #define KS2_RSTCTRL_RSTYPE              (KS2_PLL_CNTRL_BASE + 0xe4)
 174 #define KS2_RSTCTRL                     (KS2_PLL_CNTRL_BASE + 0xe8)
 175 #define KS2_RSTCTRL_RSCFG               (KS2_PLL_CNTRL_BASE + 0xec)
 176 #define KS2_RSTCTRL_KEY                 0x5a69
 177 #define KS2_RSTCTRL_MASK                0xffff0000
 178 #define KS2_RSTCTRL_SWRST               0xfffe0000
 179 #define KS2_RSTYPE_PLL_SOFT             BIT(13)
 180
 181 /* SPI */
 182 #define KS2_SPI0_BASE                   0x21000400
 183 #define KS2_SPI1_BASE                   0x21000600
 184 #define KS2_SPI2_BASE                   0x21000800
 185 #define KS2_SPI_BASE                    KS2_SPI0_BASE
 186
 187 /* AEMIF */
 188 #define KS2_AEMIF_CNTRL_BASE            0x21000a00
 189 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
 190
 191 /* Flag from ks2_debug options to check if DSPs need to stay ON */
 192 #define DBG_LEAVE_DSPS_ON               0x1
 193
 194 /* MSMC control */
 195 #define KS2_MSMC_CTRL_BASE              0x0bc00000
 196 #define KS2_MSMC_DATA_BASE              0x0c000000
 197 #define KS2_MSMC_SEGMENT_TETRIS         8
 198 #define KS2_MSMC_SEGMENT_NETCP          9
 199 #define KS2_MSMC_SEGMENT_QM_PDSP        10
 200 #define KS2_MSMC_SEGMENT_PCIE0          11
 201
 202 /* MSMC segment size shift bits */
 203 #define KS2_MSMC_SEG_SIZE_SHIFT         12
 204 #define KS2_MSMC_MAP_SEG_NUM            (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
 205 #define KS2_MSMC_DST_SEG_BASE           (CONFIG_SYS_LPAE_SDRAM_BASE >> \
 206                                         KS2_MSMC_SEG_SIZE_SHIFT)
 207
 208 /* Device speed */
 209 #define KS2_REV1_DEVSPEED               (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
 210 #define KS2_EFUSE_BOOTROM               (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
 211 #define KS2_MISC_CTRL                   (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 212
 213 /* Queue manager */
 214 #define KS2_QM_BASE_ADDRESS             0x23a80000
 215 #define KS2_QM_CONF_BASE                0x02a02000
 216 #define KS2_QM_DESC_SETUP_BASE          0x02a03000
 217 #define KS2_QM_STATUS_RAM_BASE          0x02a06000
 218 #define KS2_QM_INTD_CONF_BASE           0x02a0c000
 219 #define KS2_QM_PDSP1_CMD_BASE           0x02a20000
 220 #define KS2_QM_PDSP1_CTRL_BASE          0x02a0f000
 221 #define KS2_QM_PDSP1_IRAM_BASE          0x02a10000
 222 #define KS2_QM_MANAGER_QUEUES_BASE      0x02a80000
 223 #define KS2_QM_MANAGER_Q_PROXY_BASE     0x02ac0000
 224 #define KS2_QM_QUEUE_STATUS_BASE        0x02a40000
 225 #define KS2_QM_LINK_RAM_BASE            0x00100000
 226 #define KS2_QM_REGION_NUM               64
 227 #define KS2_QM_QPOOL_NUM                4000
 228
 229 /* USB */
 230 #define KS2_USB_SS_BASE                 0x02680000
 231 #define KS2_USB_HOST_XHCI_BASE          (KS2_USB_SS_BASE + 0x10000)
 232 #define KS2_DEV_USB_PHY_BASE            0x02620738
 233 #define KS2_USB_PHY_CFG_BASE            0x02630000
 234
 235 #define KS2_MAC_ID_BASE_ADDR            (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
 236
 237 /* SGMII SerDes */
 238 #define KS2_SGMII_SERDES_BASE           0x0232a000
 239
 240 /* JTAG ID register */
 241 #define JTAGID_VARIANT_SHIFT    28
 242 #define JTAGID_VARIANT_MASK     (0xf << 28)
 243 #define JTAGID_PART_NUM_SHIFT   12
 244 #define JTAGID_PART_NUM_MASK    (0xffff << 12)
 245
 246 /* PART NUMBER definitions */
 247 #define CPU_66AK2Hx     0xb981
 248 #define CPU_66AK2Ex     0xb9a6
 249 #define CPU_66AK2Lx     0xb9a7
 250
 251 #ifdef CONFIG_SOC_K2HK
 252 #include <asm/arch/hardware-k2hk.h>
 253 #endif
 254
 255 #ifdef CONFIG_SOC_K2E
 256 #include <asm/arch/hardware-k2e.h>
 257 #endif
 258
 259 #ifdef CONFIG_SOC_K2L
 260 #include <asm/arch/hardware-k2l.h>
 261 #endif
 262
 263 #ifndef __ASSEMBLY__
 264
 265 static inline u16 get_part_number(void)
 266 {
 267         u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
 268
 269         return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
 270 }
 271
 272 static inline u8 cpu_is_k2hk(void)
 273 {
 274         return get_part_number() == CPU_66AK2Hx;
 275 }
 276
 277 static inline u8 cpu_is_k2e(void)
 278 {
 279         return get_part_number() == CPU_66AK2Ex;
 280 }
 281
 282 static inline u8 cpu_is_k2l(void)
 283 {
 284         return get_part_number() == CPU_66AK2Lx;
 285 }
 286
 287 static inline u8 cpu_revision(void)
 288 {
 289         u32 jtag_id     = __raw_readl(KS2_JTAG_ID_REG);
 290         u8 rev  = (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
 291
 292         return rev;
 293 }
 294
 295 int cpu_to_bus(u32 *ptr, u32 length);
 296 void sdelay(unsigned long);
 297
 298 #endif
 299
 300 #endif /* __ASM_ARCH_HARDWARE_H */