2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
11 unsigned long sdram_calculate_size(void);
12 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
13 int sdram_calibration_full(void);
15 extern int sdram_calibration(void);
17 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
19 struct socfpga_sdr_ctrl {
24 u32 dram_timing4; /* 0x10 */
28 u32 dram_addrw; /* 0x2c */
29 u32 dram_if_width; /* 0x30 */
33 u32 sbe_count; /* 0x40 */
37 u32 drop_addr; /* 0x50 */
41 u32 ctrl_width; /* 0x60 */
45 u32 rfifo_cmap; /* 0x70 */
49 u32 fpgaport_rst; /* 0x80 */
53 u32 prot_rule_addr; /* 0x90 */
58 u32 mp_priority; /* 0xac */
59 u32 mp_weight0; /* 0xb0 */
63 u32 mp_pacing0; /* 0xc0 */
67 u32 mp_threshold0; /* 0xd0 */
71 u32 phy_ctrl0; /* 0x150 */
76 /* SDRAM configuration structure for the SPL. */
77 struct socfpga_sdram_config {
116 const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
118 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
119 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
120 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
121 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
122 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
123 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
124 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
125 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
126 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
127 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
128 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
129 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
130 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
131 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
132 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
133 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
134 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
135 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
136 /* Register template: sdr::ctrlgrp::dramtiming1 */
137 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
138 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
139 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
140 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
141 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
142 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
143 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
144 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
145 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
146 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
147 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
148 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
149 /* Register template: sdr::ctrlgrp::dramtiming2 */
150 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
151 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
152 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
153 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
154 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
155 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
156 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
157 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
158 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
159 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
160 /* Register template: sdr::ctrlgrp::dramtiming3 */
161 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
162 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
163 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
164 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
165 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
166 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
167 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
168 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
169 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
170 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
171 /* Register template: sdr::ctrlgrp::dramtiming4 */
172 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
173 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
174 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
175 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
176 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
177 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
178 /* Register template: sdr::ctrlgrp::lowpwrtiming */
179 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
180 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
181 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
182 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
183 /* Register template: sdr::ctrlgrp::dramaddrw */
184 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
185 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
186 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
187 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
188 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
189 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
190 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
191 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
192 /* Register template: sdr::ctrlgrp::dramifwidth */
193 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
194 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
195 /* Register template: sdr::ctrlgrp::dramdevwidth */
196 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
197 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
198 /* Register template: sdr::ctrlgrp::dramintr */
199 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
200 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
201 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
202 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
203 /* Register template: sdr::ctrlgrp::staticcfg */
204 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
205 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
206 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
207 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
208 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
209 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
210 /* Register template: sdr::ctrlgrp::ctrlwidth */
211 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
212 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
213 /* Register template: sdr::ctrlgrp::cportwidth */
214 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
215 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
216 /* Register template: sdr::ctrlgrp::cportwmap */
217 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
218 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
219 /* Register template: sdr::ctrlgrp::cportrmap */
220 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
221 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
222 /* Register template: sdr::ctrlgrp::rfifocmap */
223 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
224 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
225 /* Register template: sdr::ctrlgrp::wfifocmap */
226 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
227 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
228 /* Register template: sdr::ctrlgrp::cportrdwr */
229 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
230 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
231 /* Register template: sdr::ctrlgrp::portcfg */
232 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
233 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
234 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
235 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
236 /* Register template: sdr::ctrlgrp::fifocfg */
237 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
238 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
239 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
240 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
241 /* Register template: sdr::ctrlgrp::mppriority */
242 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
243 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
244 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
245 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
246 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
247 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
248 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
249 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
250 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
251 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
252 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
253 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
254 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
255 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
256 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
257 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
258 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
259 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
260 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
261 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
262 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
263 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
264 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
265 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
266 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
267 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
268 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
269 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
270 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
271 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
272 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
274 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
276 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
278 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
280 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
282 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
284 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
286 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
288 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
290 /* Register template: sdr::ctrlgrp::remappriority */
291 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
292 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
293 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
294 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
295 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
296 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
297 (((x) << 12) & 0xfffff000)
298 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
299 (((x) << 10) & 0x00000c00)
300 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
301 (((x) << 6) & 0x000000c0)
302 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
303 (((x) << 8) & 0x00000100)
304 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
305 (((x) << 9) & 0x00000200)
306 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
307 (((x) << 4) & 0x00000030)
308 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
309 (((x) << 2) & 0x0000000c)
310 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
311 (((x) << 0) & 0x00000003)
312 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
313 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
314 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
315 (((x) << 12) & 0xfffff000)
316 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
317 (((x) << 0) & 0x00000fff)
318 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
319 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
320 (((x) << 0) & 0x00000fff)
321 /* Register template: sdr::ctrlgrp::dramodt */
322 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4
323 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
324 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
325 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
326 /* Field instance: sdr::ctrlgrp::dramsts */
327 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
328 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
330 /* SDRAM width macro for configuration with ECC */
331 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
332 #define SDRAM_WIDTH_16BIT_WITH_ECC 24
335 #endif /* _SDRAM_H_ */