2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
11 unsigned long sdram_calculate_size(void);
12 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
13 int sdram_calibration_full(void);
15 extern int sdram_calibration(void);
17 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
19 struct socfpga_sdr_ctrl {
24 u32 dram_timing4; /* 0x10 */
28 u32 dram_addrw; /* 0x2c */
29 u32 dram_if_width; /* 0x30 */
33 u32 sbe_count; /* 0x40 */
37 u32 drop_addr; /* 0x50 */
41 u32 ctrl_width; /* 0x60 */
45 u32 rfifo_cmap; /* 0x70 */
49 u32 fpgaport_rst; /* 0x80 */
53 u32 prot_rule_addr; /* 0x90 */
58 u32 mp_priority; /* 0xac */
59 u32 mp_weight0; /* 0xb0 */
63 u32 mp_pacing0; /* 0xc0 */
67 u32 mp_threshold0; /* 0xd0 */
71 u32 phy_ctrl0; /* 0x150 */
76 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
77 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
78 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
79 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
80 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
81 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
82 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
83 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
84 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
85 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
86 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
87 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
88 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
89 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
90 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
91 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
92 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
93 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
94 /* Register template: sdr::ctrlgrp::dramtiming1 */
95 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
96 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
97 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
98 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
99 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
100 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
101 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
102 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
103 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
104 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
105 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
106 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
107 /* Register template: sdr::ctrlgrp::dramtiming2 */
108 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
109 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
110 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
111 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
112 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
113 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
114 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
115 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
116 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
117 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
118 /* Register template: sdr::ctrlgrp::dramtiming3 */
119 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
120 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
121 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
122 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
123 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
124 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
125 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
126 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
127 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
128 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
129 /* Register template: sdr::ctrlgrp::dramtiming4 */
130 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
131 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
132 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
133 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
134 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
135 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
136 /* Register template: sdr::ctrlgrp::lowpwrtiming */
137 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
138 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
139 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
140 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
141 /* Register template: sdr::ctrlgrp::dramaddrw */
142 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
143 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
144 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
145 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
146 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
147 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
148 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
149 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
150 /* Register template: sdr::ctrlgrp::dramifwidth */
151 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
152 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
153 /* Register template: sdr::ctrlgrp::dramdevwidth */
154 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
155 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
156 /* Register template: sdr::ctrlgrp::dramintr */
157 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
158 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
159 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
160 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
161 /* Register template: sdr::ctrlgrp::staticcfg */
162 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
163 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
164 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
165 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
166 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
167 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
168 /* Register template: sdr::ctrlgrp::ctrlwidth */
169 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
170 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
171 /* Register template: sdr::ctrlgrp::cportwidth */
172 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
173 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
174 /* Register template: sdr::ctrlgrp::cportwmap */
175 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
176 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
177 /* Register template: sdr::ctrlgrp::cportrmap */
178 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
179 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
180 /* Register template: sdr::ctrlgrp::rfifocmap */
181 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
182 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
183 /* Register template: sdr::ctrlgrp::wfifocmap */
184 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
185 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
186 /* Register template: sdr::ctrlgrp::cportrdwr */
187 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
188 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
189 /* Register template: sdr::ctrlgrp::portcfg */
190 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
191 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
192 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
193 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
194 /* Register template: sdr::ctrlgrp::fifocfg */
195 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
196 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
197 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
198 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
199 /* Register template: sdr::ctrlgrp::mppriority */
200 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
201 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
202 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
203 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
204 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
205 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
206 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
207 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
208 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
209 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
210 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
211 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
212 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
213 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
214 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
215 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
216 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
217 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
218 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
219 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
220 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
221 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
222 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
223 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
224 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
225 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
226 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
227 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
228 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
229 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
230 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
232 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
234 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
236 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
238 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
240 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
242 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
244 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
246 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
248 /* Register template: sdr::ctrlgrp::remappriority */
249 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
250 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
251 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
252 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
253 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
254 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
255 (((x) << 12) & 0xfffff000)
256 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
257 (((x) << 10) & 0x00000c00)
258 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
259 (((x) << 6) & 0x000000c0)
260 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
261 (((x) << 8) & 0x00000100)
262 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
263 (((x) << 9) & 0x00000200)
264 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
265 (((x) << 4) & 0x00000030)
266 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
267 (((x) << 2) & 0x0000000c)
268 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
269 (((x) << 0) & 0x00000003)
270 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
271 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
272 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
273 (((x) << 12) & 0xfffff000)
274 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
275 (((x) << 0) & 0x00000fff)
276 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
277 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
278 (((x) << 0) & 0x00000fff)
279 /* Register template: sdr::ctrlgrp::dramodt */
280 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4
281 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
282 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
283 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
284 /* Field instance: sdr::ctrlgrp::dramsts */
285 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
286 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
288 /* SDRAM width macro for configuration with ECC */
289 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
290 #define SDRAM_WIDTH_16BIT_WITH_ECC 24
293 #endif /* _SDRAM_H_ */