arch/arm/mach-socfpga/include/mach/sdram.h

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _SDRAM_H_
   7 #define _SDRAM_H_
   8
   9 #ifndef __ASSEMBLY__
  10
  11 unsigned long sdram_calculate_size(void);
  12 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
  13 int sdram_calibration_full(void);
  14
  15 const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
  16
  17 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
  18 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
  19
  20 #define SDR_CTRLGRP_ADDRESS     (SOCFPGA_SDR_ADDRESS | 0x5000)
  21
  22 struct socfpga_sdr_ctrl {
  23         u32     ctrl_cfg;
  24         u32     dram_timing1;
  25         u32     dram_timing2;
  26         u32     dram_timing3;
  27         u32     dram_timing4;   /* 0x10 */
  28         u32     lowpwr_timing;
  29         u32     dram_odt;
  30         u32     __padding0[4];
  31         u32     dram_addrw;     /* 0x2c */
  32         u32     dram_if_width;  /* 0x30 */
  33         u32     dram_dev_width;
  34         u32     dram_sts;
  35         u32     dram_intr;
  36         u32     sbe_count;      /* 0x40 */
  37         u32     dbe_count;
  38         u32     err_addr;
  39         u32     drop_count;
  40         u32     drop_addr;      /* 0x50 */
  41         u32     lowpwr_eq;
  42         u32     lowpwr_ack;
  43         u32     static_cfg;
  44         u32     ctrl_width;     /* 0x60 */
  45         u32     cport_width;
  46         u32     cport_wmap;
  47         u32     cport_rmap;
  48         u32     rfifo_cmap;     /* 0x70 */
  49         u32     wfifo_cmap;
  50         u32     cport_rdwr;
  51         u32     port_cfg;
  52         u32     fpgaport_rst;   /* 0x80 */
  53         u32     __padding1;
  54         u32     fifo_cfg;
  55         u32     protport_default;
  56         u32     prot_rule_addr; /* 0x90 */
  57         u32     prot_rule_id;
  58         u32     prot_rule_data;
  59         u32     prot_rule_rdwr;
  60         u32     __padding2[3];
  61         u32     mp_priority;    /* 0xac */
  62         u32     mp_weight0;     /* 0xb0 */
  63         u32     mp_weight1;
  64         u32     mp_weight2;
  65         u32     mp_weight3;
  66         u32     mp_pacing0;     /* 0xc0 */
  67         u32     mp_pacing1;
  68         u32     mp_pacing2;
  69         u32     mp_pacing3;
  70         u32     mp_threshold0;  /* 0xd0 */
  71         u32     mp_threshold1;
  72         u32     mp_threshold2;
  73         u32     __padding3[29];
  74         u32     phy_ctrl0;      /* 0x150 */
  75         u32     phy_ctrl1;
  76         u32     phy_ctrl2;
  77 };
  78
  79 /* SDRAM configuration structure for the SPL. */
  80 struct socfpga_sdram_config {
  81         u32     ctrl_cfg;
  82         u32     dram_timing1;
  83         u32     dram_timing2;
  84         u32     dram_timing3;
  85         u32     dram_timing4;
  86         u32     lowpwr_timing;
  87         u32     dram_odt;
  88         u32     dram_addrw;
  89         u32     dram_if_width;
  90         u32     dram_dev_width;
  91         u32     dram_intr;
  92         u32     lowpwr_eq;
  93         u32     static_cfg;
  94         u32     ctrl_width;
  95         u32     cport_width;
  96         u32     cport_wmap;
  97         u32     cport_rmap;
  98         u32     rfifo_cmap;
  99         u32     wfifo_cmap;
 100         u32     cport_rdwr;
 101         u32     port_cfg;
 102         u32     fpgaport_rst;
 103         u32     fifo_cfg;
 104         u32     mp_priority;
 105         u32     mp_weight0;
 106         u32     mp_weight1;
 107         u32     mp_weight2;
 108         u32     mp_weight3;
 109         u32     mp_pacing0;
 110         u32     mp_pacing1;
 111         u32     mp_pacing2;
 112         u32     mp_pacing3;
 113         u32     mp_threshold0;
 114         u32     mp_threshold1;
 115         u32     mp_threshold2;
 116         u32     phy_ctrl0;
 117 };
 118
 119 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
 120 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
 121 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
 122 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
 123 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
 124 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
 125 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
 126 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
 127 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
 128 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
 129 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
 130 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
 131 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
 132 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
 133 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
 134 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
 135 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
 136 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
 137 /* Register template: sdr::ctrlgrp::dramtiming1                            */
 138 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
 139 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
 140 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
 141 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
 142 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
 143 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
 144 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
 145 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
 146 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
 147 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
 148 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
 149 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
 150 /* Register template: sdr::ctrlgrp::dramtiming2                            */
 151 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
 152 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
 153 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
 154 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
 155 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
 156 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
 157 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
 158 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
 159 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
 160 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
 161 /* Register template: sdr::ctrlgrp::dramtiming3                            */
 162 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
 163 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
 164 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
 165 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
 166 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
 167 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
 168 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
 169 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
 170 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
 171 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
 172 /* Register template: sdr::ctrlgrp::dramtiming4                            */
 173 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
 174 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
 175 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
 176 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
 177 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
 178 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
 179 /* Register template: sdr::ctrlgrp::lowpwrtiming                           */
 180 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
 181 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
 182 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
 183 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
 184 /* Register template: sdr::ctrlgrp::dramaddrw                              */
 185 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
 186 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
 187 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
 188 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
 189 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
 190 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
 191 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
 192 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
 193 /* Register template: sdr::ctrlgrp::dramifwidth                            */
 194 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
 195 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
 196 /* Register template: sdr::ctrlgrp::dramdevwidth                           */
 197 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
 198 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
 199 /* Register template: sdr::ctrlgrp::dramintr                               */
 200 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
 201 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
 202 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
 203 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
 204 /* Register template: sdr::ctrlgrp::staticcfg                              */
 205 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
 206 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
 207 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
 208 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
 209 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
 210 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
 211 /* Register template: sdr::ctrlgrp::ctrlwidth                              */
 212 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
 213 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
 214 /* Register template: sdr::ctrlgrp::cportwidth                             */
 215 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
 216 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
 217 /* Register template: sdr::ctrlgrp::cportwmap                              */
 218 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
 219 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
 220 /* Register template: sdr::ctrlgrp::cportrmap                              */
 221 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
 222 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
 223 /* Register template: sdr::ctrlgrp::rfifocmap                              */
 224 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
 225 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
 226 /* Register template: sdr::ctrlgrp::wfifocmap                              */
 227 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
 228 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
 229 /* Register template: sdr::ctrlgrp::cportrdwr                              */
 230 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
 231 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
 232 /* Register template: sdr::ctrlgrp::portcfg                                */
 233 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
 234 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
 235 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
 236 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
 237 /* Register template: sdr::ctrlgrp::fifocfg                                */
 238 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
 239 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
 240 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
 241 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
 242 /* Register template: sdr::ctrlgrp::mppriority                             */
 243 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
 244 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
 245 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
 246 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
 247 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
 248 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
 249 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
 250 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
 251 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
 252 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
 253 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
 254 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
 255 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
 256 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
 257 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
 258 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
 259 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
 260 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
 261 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
 262 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
 263 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
 264 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
 265 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
 266 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
 267 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
 268 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
 269 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
 270 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
 271 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
 272 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
 273 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
 274 #define \
 275 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
 276 #define  \
 277 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
 278 0xffffffff
 279 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
 280 #define \
 281 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
 282 #define \
 283 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
 284 0xffffffff
 285 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
 286 #define \
 287 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
 288 #define \
 289 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 290 0x0000ffff
 291 /* Register template: sdr::ctrlgrp::remappriority                          */
 292 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
 293 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
 294 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
 295 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
 296 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
 297 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
 298  (((x) << 12) & 0xfffff000)
 299 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
 300  (((x) << 10) & 0x00000c00)
 301 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
 302  (((x) << 6) & 0x000000c0)
 303 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
 304  (((x) << 8) & 0x00000100)
 305 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
 306  (((x) << 9) & 0x00000200)
 307 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
 308  (((x) << 4) & 0x00000030)
 309 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
 310  (((x) << 2) & 0x0000000c)
 311 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
 312  (((x) << 0) & 0x00000003)
 313 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
 314 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
 315 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
 316  (((x) << 12) & 0xfffff000)
 317 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
 318  (((x) << 0) & 0x00000fff)
 319 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
 320 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
 321  (((x) << 0) & 0x00000fff)
 322 /* Register template: sdr::ctrlgrp::dramodt                                */
 323 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4
 324 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
 325 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
 326 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
 327 /* Field instance: sdr::ctrlgrp::dramsts                                   */
 328 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
 329 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
 330
 331 /* SDRAM width macro for configuration with ECC */
 332 #define SDRAM_WIDTH_32BIT_WITH_ECC      40
 333 #define SDRAM_WIDTH_16BIT_WITH_ECC      24
 334
 335 #endif
 336 #endif /* _SDRAM_H_ */