arch/blackfin/cpu/cpu.c

   1 /*
   2  * U-boot - cpu.c CPU specific functions
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #include <common.h>
  13 #include <command.h>
  14 #include <asm/blackfin.h>
  15 #include <asm/cplb.h>
  16 #include <asm/mach-common/bits/core.h>
  17 #include <asm/mach-common/bits/ebiu.h>
  18 #include <asm/mach-common/bits/trace.h>
  19 #include <asm/serial.h>
  20
  21 #include "cpu.h"
  22 #include "initcode.h"
  23
  24 ulong bfin_poweron_retx;
  25
  26 #if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
  27 void bfin_core1_start(void)
  28 {
  29 #ifdef BF561_FAMILY
  30         /* Enable core 1 */
  31         bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
  32 #else
  33         /* Enable core 1 */
  34         bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
  35         bfin_write32(RCU0_CRCTL, 0);
  36
  37         bfin_write32(RCU0_CRCTL, 0x2);
  38
  39         /* Check if core 1 starts */
  40         while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
  41                 continue;
  42
  43         bfin_write32(RCU0_CRCTL, 0);
  44
  45         /* flag to notify cces core 1 application */
  46         bfin_write32(SDU0_MSG_SET, (1 << 19));
  47 #endif
  48 }
  49 #endif
  50
  51 __attribute__ ((__noreturn__))
  52 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
  53 {
  54 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
  55         /* Build a NOP slide over the LDR jump block.  Whee! */
  56         char nops[0xC];
  57         serial_early_puts("NOP Slide\n");
  58         memset(nops, 0x00, sizeof(nops));
  59         memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
  60 #endif
  61
  62         if (!loaded_from_ldr) {
  63                 /* Relocate sections into L1 if the LDR didn't do it -- don't
  64                  * check length because the linker script does the size
  65                  * checking at build time.
  66                  */
  67                 serial_early_puts("L1 Relocate\n");
  68                 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
  69                 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
  70                 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
  71                 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
  72         }
  73
  74         /*
  75          * Make sure our async settings are committed.  Some bootroms
  76          * (like the BF537) will reset some registers on us after it
  77          * has finished loading the LDR.  Or if we're booting over
  78          * JTAG, the initcode never got a chance to run.  Or if we
  79          * aren't booting from parallel flash, the initcode skipped
  80          * this step completely.
  81          */
  82         program_async_controller(NULL);
  83
  84         /* Save RETX so we can pass it while booting Linux */
  85         bfin_poweron_retx = bootflag;
  86
  87 #ifdef CONFIG_DEBUG_DUMP
  88         /* Turn on hardware trace buffer */
  89         bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
  90 #endif
  91
  92 #ifndef CONFIG_PANIC_HANG
  93         /* Reset upon a double exception rather than just hanging.
  94          * Do not do bfin_read on SWRST as that will reset status bits.
  95          */
  96 # ifdef SWRST
  97         bfin_write_SWRST(DOUBLE_FAULT);
  98 # endif
  99 #endif
 100
 101 #if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
 102         bfin_core1_start();
 103 #endif
 104
 105         serial_early_puts("Board init flash\n");
 106         board_init_f(bootflag);
 107
 108         /* should not be reached */
 109         while (1);
 110 }
 111
 112 int exception_init(void)
 113 {
 114         bfin_write_EVT3(trap);
 115         return 0;
 116 }
 117
 118 int irq_init(void)
 119 {
 120 #ifdef SIC_IMASK0
 121         bfin_write_SIC_IMASK0(0);
 122         bfin_write_SIC_IMASK1(0);
 123 # ifdef SIC_IMASK2
 124         bfin_write_SIC_IMASK2(0);
 125 # endif
 126 #elif defined(SICA_IMASK0)
 127         bfin_write_SICA_IMASK0(0);
 128         bfin_write_SICA_IMASK1(0);
 129 #elif defined(SIC_IMASK)
 130         bfin_write_SIC_IMASK(0);
 131 #endif
 132         /* Set up a dummy NMI handler if needed.  */
 133         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
 134                 bfin_write_EVT2(evt_nmi);       /* NMI */
 135         bfin_write_EVT5(evt_default);   /* hardware error */
 136         bfin_write_EVT6(evt_default);   /* core timer */
 137         bfin_write_EVT7(evt_default);
 138         bfin_write_EVT8(evt_default);
 139         bfin_write_EVT9(evt_default);
 140         bfin_write_EVT10(evt_default);
 141         bfin_write_EVT11(evt_default);
 142         bfin_write_EVT12(evt_default);
 143         bfin_write_EVT13(evt_default);
 144         bfin_write_EVT14(evt_default);
 145         bfin_write_EVT15(evt_default);
 146         bfin_write_ILAT(0);
 147         CSYNC();
 148         /* enable hardware error irq */
 149         irq_flags = 0x3f;
 150         local_irq_enable();
 151         return 0;
 152 }