arch/openrisc/cpu/start.S

   1 /*
   2  * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
   3  * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
   4  * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <asm-offsets.h>
  11 #include <asm/spr-defs.h>
  12
  13 #define EXCEPTION_STACK_SIZE (128+128)
  14
  15 #define HANDLE_EXCEPTION                        \
  16         l.addi  r1, r1, -EXCEPTION_STACK_SIZE   ;\
  17         l.sw    0x00(r1), r2                    ;\
  18         l.sw    0x1c(r1), r9                    ;\
  19         l.movhi r2,hi(_exception_handler)       ;\
  20         l.ori   r2,r2,lo(_exception_handler)    ;\
  21         l.jalr  r2                              ;\
  22          l.nop                                  ;\
  23         l.lwz   r9, 0x1c(r1)                    ;\
  24         l.addi  r1, r1, EXCEPTION_STACK_SIZE    ;\
  25         l.rfe                                   ;\
  26          l.nop
  27
  28         .section .vectors, "ax"
  29         .global __reset
  30
  31         /* reset */
  32         .org    0x100
  33 __reset:
  34         /* there is no guarantee r0 is hardwired to zero, clear it here */
  35         l.andi  r0, r0, 0
  36         /* reset stack and frame pointers */
  37         l.andi  r1, r0, 0
  38         l.andi  r2, r0, 0
  39
  40         /* set supervisor mode */
  41         l.ori   r3,r0,SPR_SR_SM
  42         l.mtspr r0,r3,SPR_SR
  43
  44         l.jal   _cur
  45         l.nop
  46 _cur:
  47         l.ori   r8, r9, 0               /* Get _cur current address */
  48
  49         l.movhi r3, hi(_cur)
  50         l.ori   r3, r3, lo(_cur)
  51         l.sfeq  r8, r3                  /* If we are running at the linked address */
  52         l.bf    _no_vector_reloc        /* there is not need for relocation */
  53          l.sub  r8, r8, r3
  54
  55         l.mfspr r4, r0, SPR_CPUCFGR
  56         l.andi  r4, r4, SPR_CPUCFGR_EVBARP      /* Exception Vector Base Address Register present ? */
  57         l.sfnei r4,0
  58         l.bnf   _reloc_vectors
  59         l.movhi r5, 0                   /* Destination */
  60
  61         l.mfspr r4, r0, SPR_EVBAR
  62         l.add   r5, r5, r4
  63
  64 _reloc_vectors:
  65         /* Relocate vectors*/
  66         l.movhi r5, 0                   /* Destination */
  67         l.movhi r6, hi(__start)         /* Length */
  68         l.ori   r6, r6, lo(__start)
  69         l.ori   r3, r8, 0
  70
  71 .L_relocvectors:
  72         l.lwz   r7, 0(r3)
  73         l.sw    0(r5), r7
  74         l.addi  r5, r5, 4
  75         l.sfeq  r5, r6
  76         l.bnf   .L_relocvectors
  77          l.addi r3, r3, 4
  78
  79 _no_vector_reloc:
  80
  81         /* Relocate u-boot */
  82         l.movhi r3,hi(__start)          /* source start offset */
  83         l.ori   r3,r3,lo(__start)
  84         l.add   r3,r8,r3
  85
  86         l.movhi r4,hi(_stext)           /* dest start address */
  87         l.ori   r4,r4,lo(_stext)
  88         l.movhi r5,hi(__end)            /* dest end address */
  89         l.ori   r5,r5,lo(__end)
  90
  91 .L_reloc:
  92         l.lwz   r6,0(r3)
  93         l.sw    0(r4),r6
  94         l.addi  r3,r3,4
  95         l.sfltu r4,r5
  96         l.bf    .L_reloc
  97          l.addi r4,r4,4                 /* delay slot */
  98
  99         l.movhi r4,hi(_start)
 100         l.ori   r4,r4,lo(_start)
 101         l.jr    r4
 102          l.nop
 103
 104         /* bus error */
 105         .org    0x200
 106         HANDLE_EXCEPTION
 107
 108         /* data page fault */
 109         .org    0x300
 110         HANDLE_EXCEPTION
 111
 112         /* instruction page fault */
 113         .org    0x400
 114         HANDLE_EXCEPTION
 115
 116         /* tick timer */
 117         .org    0x500
 118         HANDLE_EXCEPTION
 119
 120         /* alignment */
 121         .org    0x600
 122         HANDLE_EXCEPTION
 123
 124         /* illegal instruction */
 125         .org    0x700
 126         HANDLE_EXCEPTION
 127
 128         /* external interrupt */
 129         .org    0x800
 130         HANDLE_EXCEPTION
 131
 132         /* D-TLB miss */
 133         .org    0x900
 134         HANDLE_EXCEPTION
 135
 136         /* I-TLB miss */
 137         .org    0xa00
 138         HANDLE_EXCEPTION
 139
 140         /* range */
 141         .org    0xb00
 142         HANDLE_EXCEPTION
 143
 144         /* system call */
 145         .org    0xc00
 146         HANDLE_EXCEPTION
 147
 148         /* floating point */
 149         .org    0xd00
 150         HANDLE_EXCEPTION
 151
 152         /* trap */
 153         .org    0xe00
 154         HANDLE_EXCEPTION
 155
 156         /* reserved */
 157         .org    0xf00
 158         HANDLE_EXCEPTION
 159
 160         /* reserved */
 161         .org    0x1100
 162         HANDLE_EXCEPTION
 163
 164         /* reserved */
 165         .org    0x1200
 166         HANDLE_EXCEPTION
 167
 168         /* reserved */
 169         .org    0x1300
 170         HANDLE_EXCEPTION
 171
 172         /* reserved */
 173         .org    0x1400
 174         HANDLE_EXCEPTION
 175
 176         /* reserved */
 177         .org    0x1500
 178         HANDLE_EXCEPTION
 179
 180         /* reserved */
 181         .org    0x1600
 182         HANDLE_EXCEPTION
 183
 184         /* reserved */
 185         .org    0x1700
 186         HANDLE_EXCEPTION
 187
 188         /* reserved */
 189         .org    0x1800
 190         HANDLE_EXCEPTION
 191
 192         /* reserved */
 193         .org    0x1900
 194         HANDLE_EXCEPTION
 195
 196         /* reserved */
 197         .org    0x1a00
 198         HANDLE_EXCEPTION
 199
 200         /* reserved */
 201         .org    0x1b00
 202         HANDLE_EXCEPTION
 203
 204         /* reserved */
 205         .org    0x1c00
 206         HANDLE_EXCEPTION
 207
 208         /* reserved */
 209         .org    0x1d00
 210         HANDLE_EXCEPTION
 211
 212         /* reserved */
 213         .org    0x1e00
 214         HANDLE_EXCEPTION
 215
 216         /* reserved */
 217         .org    0x1f00
 218         HANDLE_EXCEPTION
 219
 220         /* Startup routine */
 221         .text
 222         .global _start
 223 _start:
 224         /* Init stack and frame pointers */
 225         l.movhi r1, hi(CONFIG_SYS_INIT_SP_ADDR)
 226         l.ori   r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR)
 227         l.or    r2, r0, r1
 228
 229         /* clear BSS segments */
 230         l.movhi r4, hi(_bss_start)
 231         l.ori   r4, r4, lo(_bss_start)
 232         l.movhi r5, hi(_bss_end)
 233         l.ori   r5, r5, lo(_bss_end)
 234 .L_clear_bss:
 235         l.sw    0(r4), r0
 236         l.sfltu r4,r5
 237         l.bf    .L_clear_bss
 238          l.addi r4,r4,4
 239
 240         /* Reset registers before jumping to board_init */
 241         l.andi  r3, r0, 0
 242         l.andi  r4, r0, 0
 243         l.andi  r5, r0, 0
 244         l.andi  r6, r0, 0
 245         l.andi  r7, r0, 0
 246         l.andi  r8, r0, 0
 247         l.andi  r9, r0, 0
 248         l.andi  r10, r0, 0
 249         l.andi  r11, r0, 0
 250         l.andi  r12, r0, 0
 251         l.andi  r13, r0, 0
 252         l.andi  r14, r0, 0
 253         l.andi  r15, r0, 0
 254         l.andi  r17, r0, 0
 255         l.andi  r18, r0, 0
 256         l.andi  r19, r0, 0
 257         l.andi  r20, r0, 0
 258         l.andi  r21, r0, 0
 259         l.andi  r22, r0, 0
 260         l.andi  r23, r0, 0
 261         l.andi  r24, r0, 0
 262         l.andi  r25, r0, 0
 263         l.andi  r26, r0, 0
 264         l.andi  r27, r0, 0
 265         l.andi  r28, r0, 0
 266         l.andi  r29, r0, 0
 267         l.andi  r30, r0, 0
 268         l.andi  r31, r0, 0
 269
 270         l.j     board_init
 271          l.nop
 272
 273         .size   _start, .-_start
 274
 275 /*
 276  * Store state onto stack and call the real exception handler
 277  */
 278         .section .text
 279         .extern exception_handler
 280         .type   _exception_handler,@function
 281
 282 _exception_handler:
 283         /* Store state (r2 and r9 already saved)*/
 284         l.sw    0x04(r1), r3
 285         l.sw    0x08(r1), r4
 286         l.sw    0x0c(r1), r5
 287         l.sw    0x10(r1), r6
 288         l.sw    0x14(r1), r7
 289         l.sw    0x18(r1), r8
 290         l.sw    0x20(r1), r10
 291         l.sw    0x24(r1), r11
 292         l.sw    0x28(r1), r12
 293         l.sw    0x2c(r1), r13
 294         l.sw    0x30(r1), r14
 295         l.sw    0x34(r1), r15
 296         l.sw    0x38(r1), r16
 297         l.sw    0x3c(r1), r17
 298         l.sw    0x40(r1), r18
 299         l.sw    0x44(r1), r19
 300         l.sw    0x48(r1), r20
 301         l.sw    0x4c(r1), r21
 302         l.sw    0x50(r1), r22
 303         l.sw    0x54(r1), r23
 304         l.sw    0x58(r1), r24
 305         l.sw    0x5c(r1), r25
 306         l.sw    0x60(r1), r26
 307         l.sw    0x64(r1), r27
 308         l.sw    0x68(r1), r28
 309         l.sw    0x6c(r1), r29
 310         l.sw    0x70(r1), r30
 311         l.sw    0x74(r1), r31
 312
 313         /* Save return address */
 314         l.or    r14, r0, r9
 315         /* Call exception handler with the link address as argument */
 316         l.jal   exception_handler
 317          l.or   r3, r0, r14
 318         /* Load return address */
 319         l.or    r9, r0, r14
 320
 321         /* Restore state */
 322         l.lwz   r2, 0x00(r1)
 323         l.lwz   r3, 0x04(r1)
 324         l.lwz   r4, 0x08(r1)
 325         l.lwz   r5, 0x0c(r1)
 326         l.lwz   r6, 0x10(r1)
 327         l.lwz   r7, 0x14(r1)
 328         l.lwz   r8, 0x18(r1)
 329         l.lwz   r10, 0x20(r1)
 330         l.lwz   r11, 0x24(r1)
 331         l.lwz   r12, 0x28(r1)
 332         l.lwz   r13, 0x2c(r1)
 333         l.lwz   r14, 0x30(r1)
 334         l.lwz   r15, 0x34(r1)
 335         l.lwz   r16, 0x38(r1)
 336         l.lwz   r17, 0x3c(r1)
 337         l.lwz   r18, 0x40(r1)
 338         l.lwz   r19, 0x44(r1)
 339         l.lwz   r20, 0x48(r1)
 340         l.lwz   r21, 0x4c(r1)
 341         l.lwz   r22, 0x50(r1)
 342         l.lwz   r23, 0x54(r1)
 343         l.lwz   r24, 0x58(r1)
 344         l.lwz   r25, 0x5c(r1)
 345         l.lwz   r26, 0x60(r1)
 346         l.lwz   r27, 0x64(r1)
 347         l.lwz   r28, 0x68(r1)
 348         l.lwz   r29, 0x6c(r1)
 349         l.lwz   r30, 0x70(r1)
 350         l.lwz   r31, 0x74(r1)
 351         l.jr    r9
 352          l.nop