2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 #include <asm/fsl_ifc.h>
37 #include <asm/fsl_law.h>
38 #include <asm/fsl_lbc.h>
40 #include <asm/processor.h>
41 #include <asm/fsl_ddr_sdram.h>
43 DECLARE_GLOBAL_DATA_PTR;
46 * Default board reset function
53 void board_reset(void) __attribute__((weak, alias("__board_reset")));
62 char buf1[32], buf2[32];
63 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
64 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
65 #endif /* CONFIG_FSL_CORENET */
66 #ifdef CONFIG_DDR_CLK_FREQ
67 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
68 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
70 #ifdef CONFIG_FSL_CORENET
71 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
72 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
75 #endif /* CONFIG_FSL_CORENET */
76 #endif /* CONFIG_DDR_CLK_FREQ */
77 unsigned int i, core, nr_cores = cpu_numcores();
78 u32 mask = cpu_mask();
84 if (cpu_numcores() > 1) {
86 puts("Unicore software on multiprocessor system!!\n"
87 "To enable mutlticore build define CONFIG_MP\n");
89 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
90 printf("CPU%d: ", pic->whoami);
98 if (IS_E_PROCESSOR(svr))
101 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
105 major = PVR_MAJ(pvr);
106 minor = PVR_MIN(pvr);
110 case PVR_VER_E500_V1:
111 case PVR_VER_E500_V2:
128 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
130 get_sys_info(&sysinfo);
132 puts("Clock Configuration:");
133 for_each_cpu(i, core, nr_cores, mask) {
136 printf("CPU%d:%-4s MHz, ", core,
137 strmhz(buf1, sysinfo.freqProcessor[core]));
139 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
141 #ifdef CONFIG_FSL_CORENET
143 printf(" DDR:%-4s MHz (%s MT/s data rate) "
145 strmhz(buf1, sysinfo.freqDDRBus/2),
146 strmhz(buf2, sysinfo.freqDDRBus));
148 printf(" DDR:%-4s MHz (%s MT/s data rate) "
150 strmhz(buf1, sysinfo.freqDDRBus/2),
151 strmhz(buf2, sysinfo.freqDDRBus));
156 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
157 strmhz(buf1, sysinfo.freqDDRBus/2),
158 strmhz(buf2, sysinfo.freqDDRBus));
161 printf(" DDR:%-4s MHz (%s MT/s data rate) "
163 strmhz(buf1, sysinfo.freqDDRBus/2),
164 strmhz(buf2, sysinfo.freqDDRBus));
167 printf(" DDR:%-4s MHz (%s MT/s data rate) "
169 strmhz(buf1, sysinfo.freqDDRBus/2),
170 strmhz(buf2, sysinfo.freqDDRBus));
175 #if defined(CONFIG_FSL_LBC)
176 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
177 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
179 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
180 sysinfo.freqLocalBus);
184 #if defined(CONFIG_FSL_IFC)
185 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
189 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
193 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
196 #ifdef CONFIG_SYS_DPAA_FMAN
197 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
198 printf(" FMAN%d: %s MHz\n", i + 1,
199 strmhz(buf1, sysinfo.freqFMan[i]));
203 #ifdef CONFIG_SYS_DPAA_PME
204 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
207 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
213 /* ------------------------------------------------------------------------- */
215 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
217 /* Everything after the first generation of PQ3 parts has RSTCR */
218 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
219 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
220 unsigned long val, msr;
223 * Initiate hard reset in debug control register DBCR0
224 * Make sure MSR[DE] = 1. This only resets the core.
234 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
236 /* Attempt board-specific reset */
239 /* Next try asserting HRESET_REQ */
240 out_be32(&gur->rstcr, 0x2);
249 * Get timebase clock frequency
251 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
252 #define CONFIG_SYS_FSL_TBCLK_DIV 8
254 unsigned long get_tbclk (void)
256 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
258 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
262 #if defined(CONFIG_WATCHDOG)
266 int re_enable = disable_interrupts();
267 reset_85xx_watchdog();
268 if (re_enable) enable_interrupts();
272 reset_85xx_watchdog(void)
275 * Clear TSR(WIS) bit by writing 1
277 mtspr(SPRN_TSR, TSR_WIS);
279 #endif /* CONFIG_WATCHDOG */
282 * Initializes on-chip MMC controllers.
283 * to override, implement board_mmc_init()
285 int cpu_mmc_init(bd_t *bis)
287 #ifdef CONFIG_FSL_ESDHC
288 return fsl_esdhc_mmc_init(bis);
295 * Print out the state of various machine registers.
296 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
297 * parameters for IFC and TLBs
299 void mpc85xx_reginfo(void)
303 #if defined(CONFIG_FSL_LBC)
306 #ifdef CONFIG_FSL_IFC
312 /* Common ddr init for non-corenet fsl 85xx platforms */
313 #ifndef CONFIG_FSL_CORENET
314 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
315 phys_size_t initdram(int board_type)
317 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
318 return fsl_ddr_sdram_size();
320 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
323 #else /* CONFIG_SYS_RAMBOOT */
324 phys_size_t initdram(int board_type)
326 phys_size_t dram_size = 0;
328 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
330 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
335 * Work around to stabilize DDR DLL
337 out_be32(&gur->ddrdllcr, 0x81000000);
338 asm("sync;isync;msync");
340 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
341 setbits_be32(&gur->devdisr, 0x00010000);
342 for (i = 0; i < x; i++)
344 clrbits_be32(&gur->devdisr, 0x00010000);
350 #if defined(CONFIG_SPD_EEPROM) || \
351 defined(CONFIG_DDR_SPD) || \
352 defined(CONFIG_SYS_DDR_RAW_TIMING)
353 dram_size = fsl_ddr_sdram();
355 dram_size = fixed_sdram();
357 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
358 dram_size *= 0x100000;
360 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
362 * Initialize and enable DDR ECC.
364 ddr_enable_ecc(dram_size);
367 #if defined(CONFIG_FSL_LBC)
368 /* Some boards also have sdram on the lbc */
375 #endif /* CONFIG_SYS_RAMBOOT */
378 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
380 /* Board-specific functions defined in each board's ddr.c */
381 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
382 unsigned int ctrl_num);
383 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
386 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
388 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
390 static void dump_spd_ddr_reg(void)
395 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
397 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
399 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
400 fsl_ddr_get_spd(spd[i], i);
402 puts("SPD data of all dimms (zero vaule is omitted)...\n");
405 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
406 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
407 printf("Dimm%d ", k++);
410 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
412 printf("%3d (0x%02x) ", k, k);
413 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
414 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
415 p_8 = (u8 *) &spd[i][j];
417 printf("0x%02x ", p_8[k]);
429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
432 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
434 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
436 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
439 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
441 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
444 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
446 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
450 printf("%s unexpected controller number = %u\n",
455 printf("DDR registers dump for all controllers "
456 "(zero vaule is omitted)...\n");
457 puts("Offset (hex) ");
458 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
459 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
461 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
463 printf("%6d (0x%04x)", k * 4, k * 4);
464 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
465 p_32 = (u32 *) ddr[i];
467 printf(" 0x%08x", p_32[k]);
480 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
481 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
483 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
485 u32 tsize, valid, ptr;
488 clear_ddr_tlbs_phys(p_addr, size>>20);
490 /* Setup new tlb to cover the physical address */
491 setup_ddr_tlbs_phys(p_addr, size>>20);
494 ddr_esel = find_tlb_idx((void *)ptr, 1);
495 if (ddr_esel != -1) {
496 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
498 printf("TLB error in function %s\n", __func__);
506 * slide the testing window up to test another area
507 * for 32_bit system, the maximum testable memory is limited to
508 * CONFIG_MAX_MEM_MAPPED
510 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
512 phys_addr_t test_cap, p_addr;
513 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
515 #if !defined(CONFIG_PHYS_64BIT) || \
516 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
517 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
520 test_cap = gd->ram_size;
522 p_addr = (*vstart) + (*size) + (*phys_offset);
523 if (p_addr < test_cap - 1) {
524 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
525 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
527 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
528 *size = (u32) p_size;
529 printf("Testing 0x%08llx - 0x%08llx\n",
530 (u64)(*vstart) + (*phys_offset),
531 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
538 /* initialization for testing area */
539 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
541 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
543 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
544 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
547 #if !defined(CONFIG_PHYS_64BIT) || \
548 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
549 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
550 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
551 puts("Cannot test more than ");
552 print_size(CONFIG_MAX_MEM_MAPPED,
553 " without proper 36BIT support.\n");
556 printf("Testing 0x%08llx - 0x%08llx\n",
557 (u64)(*vstart) + (*phys_offset),
558 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
563 /* invalid TLBs for DDR and remap as normal after testing */
564 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
567 u32 tsize, valid, ptr;
571 /* disable the TLBs for this testing */
574 while (ptr < (*vstart) + (*size)) {
575 ddr_esel = find_tlb_idx((void *)ptr, 1);
576 if (ddr_esel != -1) {
577 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
578 disable_tlb(ddr_esel);
580 ptr += TSIZE_TO_BYTES(tsize);
584 setup_ddr_tlbs(gd->ram_size>>20);
590 void arch_memory_failure_handle(void)