arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i, bus_width;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24         u32 total_gb_size_per_controller;
  25         int timeout;
  26 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  27         int timeout_save;
  28         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  29         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  30         int csn = -1;
  31 #endif
  32
  33         switch (ctrl_num) {
  34         case 0:
  35                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  36                 break;
  37 #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  38         case 1:
  39                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
  40                 break;
  41 #endif
  42 #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  43         case 2:
  44                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
  45                 break;
  46 #endif
  47 #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  48         case 3:
  49                 ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
  50                 break;
  51 #endif
  52         default:
  53                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  54                 return;
  55         }
  56
  57         if (regs->ddr_eor)
  58                 out_be32(&ddr->eor, regs->ddr_eor);
  59 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  60         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  61         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  62                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  63                 cs_ea = regs->cs[i].bnds & 0xfff;
  64                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  65                         csn = i;
  66                         csn_bnds_backup = regs->cs[i].bnds;
  67                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  68                         if (cs_ea > 0xeff)
  69                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  70                         else
  71                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  72                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  73                                 "change it to 0x%x\n",
  74                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  75                         break;
  76                 }
  77         }
  78 #endif
  79         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  80                 if (i == 0) {
  81                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  82                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  83                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  84
  85                 } else if (i == 1) {
  86                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  87                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  88                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  89
  90                 } else if (i == 2) {
  91                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  92                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  93                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  94
  95                 } else if (i == 3) {
  96                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  97                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  98                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  99                 }
 100         }
 101
 102         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 103         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 104         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 105         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 106         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 107         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 108         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 109         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 110         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 111         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 112         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 113         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 114         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 115         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 116         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 117         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 118         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 119         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 120         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 121
 122         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 123         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 124         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 125         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 126         if (regs->ddr_wrlvl_cntl_2)
 127                 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 128         if (regs->ddr_wrlvl_cntl_3)
 129                 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 130
 131         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 132         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 133         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 134         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 135         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 136         out_be32(&ddr->err_disable, regs->err_disable);
 137         out_be32(&ddr->err_int_en, regs->err_int_en);
 138         for (i = 0; i < 32; i++) {
 139                 if (regs->debug[i]) {
 140                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 141                         out_be32(&ddr->debug[i], regs->debug[i]);
 142                 }
 143         }
 144 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 145         out_be32(&ddr->debug[28], 0x30003000);
 146 #endif
 147
 148 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 149         out_be32(&ddr->debug[12], 0x00000015);
 150         out_be32(&ddr->debug[21], 0x24000000);
 151 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 152
 153         /* Set, but do not enable the memory */
 154         temp_sdram_cfg = regs->ddr_sdram_cfg;
 155         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 156         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 157 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 158         debug("Workaround for ERRATUM_DDR_A003\n");
 159         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 160                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 161                 out_be32(&ddr->debug[2], 0x00000400);
 162                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 163                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 164                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 165                 out_be32(&ddr->mtcr, 0);
 166                 out_be32(&ddr->debug[12], 0x00000015);
 167                 out_be32(&ddr->debug[21], 0x24000000);
 168                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 169                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 170
 171                 asm volatile("sync;isync");
 172                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 173                         ;
 174
 175                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 176                 case 0x00000000:
 177                         out_be32(&ddr->sdram_md_cntl,
 178                                 MD_CNTL_MD_EN           |
 179                                 MD_CNTL_CS_SEL_CS0_CS1  |
 180                                 0x04000000              |
 181                                 MD_CNTL_WRCW            |
 182                                 MD_CNTL_MD_VALUE(0x02));
 183                         break;
 184                 case 0x00100000:
 185                         out_be32(&ddr->sdram_md_cntl,
 186                                 MD_CNTL_MD_EN           |
 187                                 MD_CNTL_CS_SEL_CS0_CS1  |
 188                                 0x04000000              |
 189                                 MD_CNTL_WRCW            |
 190                                 MD_CNTL_MD_VALUE(0x0a));
 191                         break;
 192                 case 0x00200000:
 193                         out_be32(&ddr->sdram_md_cntl,
 194                                 MD_CNTL_MD_EN           |
 195                                 MD_CNTL_CS_SEL_CS0_CS1  |
 196                                 0x04000000              |
 197                                 MD_CNTL_WRCW            |
 198                                 MD_CNTL_MD_VALUE(0x12));
 199                         break;
 200                 case 0x00300000:
 201                         out_be32(&ddr->sdram_md_cntl,
 202                                 MD_CNTL_MD_EN           |
 203                                 MD_CNTL_CS_SEL_CS0_CS1  |
 204                                 0x04000000              |
 205                                 MD_CNTL_WRCW            |
 206                                 MD_CNTL_MD_VALUE(0x1a));
 207                         break;
 208                 default:
 209                         out_be32(&ddr->sdram_md_cntl,
 210                                 MD_CNTL_MD_EN           |
 211                                 MD_CNTL_CS_SEL_CS0_CS1  |
 212                                 0x04000000              |
 213                                 MD_CNTL_WRCW            |
 214                                 MD_CNTL_MD_VALUE(0x02));
 215                         printf("Unsupported RC10\n");
 216                         break;
 217                 }
 218
 219                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 220                         ;
 221                 udelay(6);
 222                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 223                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 224                 out_be32(&ddr->debug[2], 0x0);
 225                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 226                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 227                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 228                 out_be32(&ddr->debug[12], 0x0);
 229                 out_be32(&ddr->debug[21], 0x0);
 230                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 231
 232         }
 233 #endif
 234         /*
 235          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 236          * when operatiing in 32-bit bus mode with 4-beat bursts,
 237          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 238          */
 239 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 240         debug("Workaround for ERRATUM_DDR_115\n");
 241         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 242             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 243                 /* set DEBUG_1[31] */
 244                 setbits_be32(&ddr->debug[0], 1);
 245         }
 246 #endif
 247 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 248         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 249         /*
 250          * This is the combined workaround for DDR111 and DDR134
 251          * following the published errata for MPC8572
 252          */
 253
 254         /* 1. Set EEBACR[3] */
 255         setbits_be32(&ecm->eebacr, 0x10000000);
 256         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 257
 258         /* 2. Set DINIT in SDRAM_CFG_2*/
 259         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 260         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 261                 in_be32(&ddr->sdram_cfg_2));
 262
 263         /* 3. Set DEBUG_3[21] */
 264         setbits_be32(&ddr->debug[2], 0x400);
 265         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 266
 267 #endif  /* part 1 of the workaound */
 268
 269         /*
 270          * 500 painful micro-seconds must elapse between
 271          * the DDR clock setup and the DDR config enable.
 272          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 273          * we choose the max, that is 500 us for all of case.
 274          */
 275         udelay(500);
 276         asm volatile("sync;isync");
 277
 278         /* Let the controller go */
 279         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 280         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 281         asm volatile("sync;isync");
 282
 283         total_gb_size_per_controller = 0;
 284         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 285                 if (!(regs->cs[i].config & 0x80000000))
 286                         continue;
 287                 total_gb_size_per_controller += 1 << (
 288                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 289                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 290                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 291                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 292                         26);                    /* minus 26 (count of 64M) */
 293         }
 294         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 295                 total_gb_size_per_controller *= 3;
 296         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 297                 total_gb_size_per_controller <<= 1;
 298         /*
 299          * total memory / bus width = transactions needed
 300          * transactions needed / data rate = seconds
 301          * to add plenty of buffer, double the time
 302          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 303          * Let's wait for 800ms
 304          */
 305         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 306                         >> SDRAM_CFG_DBW_SHIFT);
 307         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 308                 (get_ddr_freq(0) >> 20)) << 1;
 309 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 310         timeout_save = timeout;
 311 #endif
 312         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 313         debug("total %d GB\n", total_gb_size_per_controller);
 314         debug("Need to wait up to %d * 10ms\n", timeout);
 315
 316         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 317         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 318                 (timeout >= 0)) {
 319                 udelay(10000);          /* throttle polling rate */
 320                 timeout--;
 321         }
 322
 323         if (timeout <= 0)
 324                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 325
 326 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 327         /* continue this workaround */
 328
 329         /* 4. Clear DEBUG3[21] */
 330         clrbits_be32(&ddr->debug[2], 0x400);
 331         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 332
 333         /* DDR134 workaround starts */
 334         /* A: Clear sdram_cfg_2[odt_cfg] */
 335         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 336         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 337                 in_be32(&ddr->sdram_cfg_2));
 338
 339         /* B: Set DEBUG1[15] */
 340         setbits_be32(&ddr->debug[0], 0x10000);
 341         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 342
 343         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 344         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 345         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 346                 in_be32(&ddr->timing_cfg_2));
 347
 348         /* D: Set D6 to 0x9f9f9f9f */
 349         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 350         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 351
 352         /* E: Set D7 to 0x9f9f9f9f */
 353         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 354         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 355
 356         /* F: Set D2[20] */
 357         setbits_be32(&ddr->debug[1], 0x800);
 358         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 359
 360         /* G: Poll on D2[20] until cleared */
 361         while (in_be32(&ddr->debug[1]) & 0x800)
 362                 udelay(10000);          /* throttle polling rate */
 363
 364         /* H: Clear D1[15] */
 365         clrbits_be32(&ddr->debug[0], 0x10000);
 366         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 367
 368         /* I: Set sdram_cfg_2[odt_cfg] */
 369         setbits_be32(&ddr->sdram_cfg_2,
 370                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 371         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 372
 373         /* Continuing with the DDR111 workaround */
 374         /* 5. Set D2[21] */
 375         setbits_be32(&ddr->debug[1], 0x400);
 376         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 377
 378         /* 6. Poll D2[21] until its cleared */
 379         while (in_be32(&ddr->debug[1]) & 0x400)
 380                 udelay(10000);          /* throttle polling rate */
 381
 382         /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
 383         debug("Wait for %d * 10ms\n", timeout_save);
 384         udelay(timeout_save * 10000);
 385
 386         /* 8. Set sdram_cfg_2[dinit] if options requires */
 387         setbits_be32(&ddr->sdram_cfg_2,
 388                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 389         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 390
 391         /* 9. Poll until dinit is cleared */
 392         timeout = timeout_save;
 393         debug("Need to wait up to %d * 10ms\n", timeout);
 394         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 395                 (timeout >= 0)) {
 396                 udelay(10000);          /* throttle polling rate */
 397                 timeout--;
 398         }
 399
 400         if (timeout <= 0)
 401                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 402
 403         /* 10. Clear EEBACR[3] */
 404         clrbits_be32(&ecm->eebacr, 10000000);
 405         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 406
 407         if (csn != -1) {
 408                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 409                 *csn_bnds_t = csn_bnds_backup;
 410                 debug("Change cs%d_bnds back to 0x%08x\n",
 411                         csn, regs->cs[csn].bnds);
 412                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 413                 switch (csn) {
 414                 case 0:
 415                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 416                         break;
 417                 case 1:
 418                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 419                         break;
 420                 case 2:
 421                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 422                         break;
 423                 case 3:
 424                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 425                         break;
 426                 }
 427                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 428         }
 429 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 430 }