arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/fsl_serdes.h>
   9 #include <asm/immap_85xx.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #include <asm/fsl_law.h>
  13 #include <asm/errno.h>
  14 #include <asm/fsl_errata.h>
  15 #include "fsl_corenet2_serdes.h"
  16
  17 #ifdef CONFIG_SYS_FSL_SRDS_1
  18 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  19 #endif
  20 #ifdef CONFIG_SYS_FSL_SRDS_2
  21 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  22 #endif
  23 #ifdef CONFIG_SYS_FSL_SRDS_3
  24 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  25 #endif
  26 #ifdef CONFIG_SYS_FSL_SRDS_4
  27 static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
  28 #endif
  29
  30 #ifdef DEBUG
  31 static const char *serdes_prtcl_str[] = {
  32         [NONE] = "NA",
  33         [PCIE1] = "PCIE1",
  34         [PCIE2] = "PCIE2",
  35         [PCIE3] = "PCIE3",
  36         [PCIE4] = "PCIE4",
  37         [SATA1] = "SATA1",
  38         [SATA2] = "SATA2",
  39         [SRIO1] = "SRIO1",
  40         [SRIO2] = "SRIO2",
  41         [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  42         [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  43         [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  44         [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  45         [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  46         [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
  47         [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  48         [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  49         [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  50         [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  51         [XAUI_FM1] = "XAUI_FM1",
  52         [XAUI_FM2] = "XAUI_FM2",
  53         [AURORA] = "DEBUG",
  54         [CPRI1] = "CPRI1",
  55         [CPRI2] = "CPRI2",
  56         [CPRI3] = "CPRI3",
  57         [CPRI4] = "CPRI4",
  58         [CPRI5] = "CPRI5",
  59         [CPRI6] = "CPRI6",
  60         [CPRI7] = "CPRI7",
  61         [CPRI8] = "CPRI8",
  62         [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
  63         [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
  64         [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
  65         [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
  66         [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
  67         [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
  68         [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
  69         [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
  70         [QSGMII_FM1_A] = "QSGMII_FM1_A",
  71         [QSGMII_FM1_B] = "QSGMII_FM1_B",
  72         [QSGMII_FM2_A] = "QSGMII_FM2_A",
  73         [QSGMII_FM2_B] = "QSGMII_FM2_B",
  74         [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
  75         [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
  76         [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
  77         [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
  78         [INTERLAKEN] = "INTERLAKEN",
  79         [QSGMII_SW1_A] = "QSGMII_SW1_A",
  80         [QSGMII_SW1_B] = "QSGMII_SW1_B",
  81 };
  82 #endif
  83
  84 int is_serdes_configured(enum srds_prtcl device)
  85 {
  86         int ret = 0;
  87
  88 #ifdef CONFIG_SYS_FSL_SRDS_1
  89         ret |= serdes1_prtcl_map[device];
  90 #endif
  91 #ifdef CONFIG_SYS_FSL_SRDS_2
  92         ret |= serdes2_prtcl_map[device];
  93 #endif
  94 #ifdef CONFIG_SYS_FSL_SRDS_3
  95         ret |= serdes3_prtcl_map[device];
  96 #endif
  97 #ifdef CONFIG_SYS_FSL_SRDS_4
  98         ret |= serdes4_prtcl_map[device];
  99 #endif
 100
 101         return !!ret;
 102 }
 103
 104 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 105 {
 106         const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 107         u32 cfg = in_be32(&gur->rcwsr[4]);
 108         int i;
 109
 110         switch (sd) {
 111 #ifdef CONFIG_SYS_FSL_SRDS_1
 112         case FSL_SRDS_1:
 113                 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 114                 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 115                 break;
 116 #endif
 117 #ifdef CONFIG_SYS_FSL_SRDS_2
 118         case FSL_SRDS_2:
 119                 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 120                 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 121                 break;
 122 #endif
 123 #ifdef CONFIG_SYS_FSL_SRDS_3
 124         case FSL_SRDS_3:
 125                 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
 126                 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
 127                 break;
 128 #endif
 129 #ifdef CONFIG_SYS_FSL_SRDS_4
 130         case FSL_SRDS_4:
 131                 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 132                 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
 133                 break;
 134 #endif
 135         default:
 136                 printf("invalid SerDes%d\n", sd);
 137                 break;
 138         }
 139         /* Is serdes enabled at all? */
 140         if (unlikely(cfg == 0))
 141                 return -ENODEV;
 142
 143         for (i = 0; i < SRDS_MAX_LANES; i++) {
 144                 if (serdes_get_prtcl(sd, cfg, i) == device)
 145                         return i;
 146         }
 147
 148         return -ENODEV;
 149 }
 150
 151 #define BC3_SHIFT       9
 152 #define DC3_SHIFT       6
 153 #define FC3_SHIFT       0
 154 #define BC2_SHIFT       19
 155 #define DC2_SHIFT       16
 156 #define FC2_SHIFT       10
 157 #define BC1_SHIFT       29
 158 #define DC1_SHIFT       26
 159 #define FC1_SHIFT       20
 160 #define BC_MASK         0x1
 161 #define DC_MASK         0x7
 162 #define FC_MASK         0x3F
 163
 164 #define FUSE_VAL_MASK           0x00000003
 165 #define FUSE_VAL_SHIFT          30
 166 #define CR0_DCBIAS_SHIFT        5
 167 #define CR1_FCAP_SHIFT          15
 168 #define CR1_BCAP_SHIFT          29
 169 #define FCAP_MASK               0x001F8000
 170 #define BCAP_MASK               0x20000000
 171 #define BCAP_OVD_MASK           0x10000000
 172 #define BYP_CAL_MASK            0x02000000
 173
 174 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 175                 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 176 {
 177         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 178         u32 cfg;
 179         int lane;
 180
 181         memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
 182 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
 183         struct ccsr_sfp_regs  __iomem *sfp_regs =
 184                         (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
 185         u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
 186         u32 bc_status, fc_status, dc_status, pll_sr2;
 187         serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;
 188         u32 sfp_spfr0, sel;
 189 #endif
 190
 191         cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
 192
 193 /* Erratum A-007186
 194  * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
 195  * The workaround requires factory pre-set SerDes calibration values to be
 196  * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
 197  * These values have been shown to work across the
 198  * entire temperature range for all SerDes. These values are then written into
 199  * the SerDes registers to calibrate the SerDes PLL.
 200  *
 201  * This workaround for the protocols and rates that only have the Ring VCO.
 202  */
 203 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
 204         sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
 205         debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
 206
 207         sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
 208
 209         if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
 210                 for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
 211                         pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
 212                         debug("A007186: pll_num=%x pllcr0=%x\n",
 213                               pll_num, pll_status);
 214                         /* STEP 1 */
 215                         /* Read factory pre-set SerDes calibration values
 216                          * from fuse block(SFP scratch register-sfp_spfr0)
 217                          */
 218                         switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
 219                         case SRDS_PLLCR0_FRATE_SEL_3_0:
 220                         case SRDS_PLLCR0_FRATE_SEL_3_072:
 221                                 debug("A007186: 3.0/3.072 protocol rate\n");
 222                                 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
 223                                 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
 224                                 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
 225                                 break;
 226                         case SRDS_PLLCR0_FRATE_SEL_3_125:
 227                                 debug("A007186: 3.125 protocol rate\n");
 228                                 bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
 229                                 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
 230                                 fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
 231                                 break;
 232                         case SRDS_PLLCR0_FRATE_SEL_3_75:
 233                                 debug("A007186: 3.75 protocol rate\n");
 234                                 bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
 235                                 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
 236                                 fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
 237                                 break;
 238                         default:
 239                                 continue;
 240                         }
 241
 242                         /* STEP 2 */
 243                         /* Write SRDSxPLLnCR1[11:16] = FC
 244                          * Write SRDSxPLLnCR1[2] = BC
 245                          */
 246                         pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
 247                         pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
 248                                       ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
 249                         out_be32(&srds_regs->bank[pll_num].pllcr1,
 250                                  (pll_cr_upd | pll_cr1));
 251                         debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
 252                               pll_num, (pll_cr_upd | pll_cr1));
 253                         /* Write SRDSxPLLnCR0[24:26] = DC
 254                          */
 255                         pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
 256                         out_be32(&srds_regs->bank[pll_num].pllcr0,
 257                                  pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
 258                         debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
 259                               pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
 260                         /* Write SRDSxPLLnCR1[3] = 1
 261                          * Write SRDSxPLLnCR1[6] = 1
 262                          */
 263                         pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
 264                         pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
 265                         out_be32(&srds_regs->bank[pll_num].pllcr1,
 266                                  (pll_cr_upd | pll_cr1));
 267                         debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
 268                               pll_num, (pll_cr_upd | pll_cr1));
 269
 270                         /* STEP 3 */
 271                         /* Read the status Registers */
 272                         /* Verify SRDSxPLLnSR2[8] = BC */
 273                         pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
 274                         debug("A007186: pll_num=%x pllsr2=%x\n",
 275                               pll_num, pll_sr2);
 276                         bc_status = (pll_sr2 >> 23) & BC_MASK;
 277                         if (bc_status != bc)
 278                                 debug("BC mismatch\n");
 279                         fc_status = (pll_sr2 >> 16) & FC_MASK;
 280                         if (fc_status != fc)
 281                                 debug("FC mismatch\n");
 282                         pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
 283                         out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
 284                                                                 0x02000000);
 285                         pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
 286                         dc_status = (pll_sr2 >> 17) & DC_MASK;
 287                         if (dc_status != dc)
 288                                 debug("DC mismatch\n");
 289                         pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
 290                         out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
 291                                                                 0xfdffffff);
 292
 293                         /* STEP 4 */
 294                         /* Wait 750us to verify the PLL is locked
 295                          * by checking SRDSxPLLnCR0[8] = 1.
 296                          */
 297                         udelay(750);
 298                         pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
 299                         debug("A007186: pll_num=%x pllcr0=%x\n",
 300                               pll_num, pll_status);
 301
 302                         if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
 303                                 printf("A007186 Serdes PLL not locked\n");
 304                         else
 305                                 debug("A007186 Serdes PLL locked\n");
 306                 }
 307         }
 308 #endif
 309
 310         cfg >>= sd_prctl_shift;
 311         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 312         if (!is_serdes_prtcl_valid(sd, cfg))
 313                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 314
 315         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 316                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 317                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 318                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
 319                 else
 320                         serdes_prtcl_map[lane_prtcl] = 1;
 321         }
 322 }
 323
 324 void fsl_serdes_init(void)
 325 {
 326
 327 #ifdef CONFIG_SYS_FSL_SRDS_1
 328         serdes_init(FSL_SRDS_1,
 329                     CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
 330                     FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
 331                     FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
 332                     serdes1_prtcl_map);
 333 #endif
 334 #ifdef CONFIG_SYS_FSL_SRDS_2
 335         serdes_init(FSL_SRDS_2,
 336                     CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
 337                     FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
 338                     FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
 339                     serdes2_prtcl_map);
 340 #endif
 341 #ifdef CONFIG_SYS_FSL_SRDS_3
 342         serdes_init(FSL_SRDS_3,
 343                     CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
 344                     FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
 345                     FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
 346                     serdes3_prtcl_map);
 347 #endif
 348 #ifdef CONFIG_SYS_FSL_SRDS_4
 349         serdes_init(FSL_SRDS_4,
 350                     CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
 351                     FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
 352                     FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
 353                     serdes4_prtcl_map);
 354 #endif
 355
 356 }
 357
 358 const char *serdes_clock_to_string(u32 clock)
 359 {
 360         switch (clock) {
 361         case SRDS_PLLCR0_RFCK_SEL_100:
 362                 return "100";
 363         case SRDS_PLLCR0_RFCK_SEL_125:
 364                 return "125";
 365         case SRDS_PLLCR0_RFCK_SEL_156_25:
 366                 return "156.25";
 367         case SRDS_PLLCR0_RFCK_SEL_161_13:
 368                 return "161.1328123";
 369         default:
 370 #if defined(CONFIG_T4240QDS)
 371                 return "???";
 372 #else
 373                 return "122.88";
 374 #endif
 375         }
 376 }
 377