arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  */
   9
  10 /*
  11  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  12  * Based on code from spd_sdram.c
  13  * Author: James Yang [at freescale.com]
  14  */
  15
  16 #include <common.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18
  19 #include "ddr.h"
  20
  21 extern unsigned int picos_to_mclk(unsigned int picos);
  22 /*
  23  * Determine Rtt value.
  24  *
  25  * This should likely be either board or controller specific.
  26  *
  27  * Rtt(nominal) - DDR2:
  28  *      0 = Rtt disabled
  29  *      1 = 75 ohm
  30  *      2 = 150 ohm
  31  *      3 = 50 ohm
  32  * Rtt(nominal) - DDR3:
  33  *      0 = Rtt disabled
  34  *      1 = 60 ohm
  35  *      2 = 120 ohm
  36  *      3 = 40 ohm
  37  *      4 = 20 ohm
  38  *      5 = 30 ohm
  39  *
  40  * FIXME: Apparently 8641 needs a value of 2
  41  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  42  *
  43  * FIXME: There was some effort down this line earlier:
  44  *
  45  *      unsigned int i;
  46  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  47  *              if (popts->dimmslot[i].num_valid_cs
  48  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  49  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  50  *                      rtt = 2;
  51  *                      break;
  52  *              }
  53  *      }
  54  */
  55 static inline int fsl_ddr_get_rtt(void)
  56 {
  57         int rtt;
  58
  59 #if defined(CONFIG_FSL_DDR1)
  60         rtt = 0;
  61 #elif defined(CONFIG_FSL_DDR2)
  62         rtt = 3;
  63 #else
  64         rtt = 0;
  65 #endif
  66
  67         return rtt;
  68 }
  69
  70 /*
  71  * compute the CAS write latency according to DDR3 spec
  72  * CWL = 5 if tCK >= 2.5ns
  73  *       6 if 2.5ns > tCK >= 1.875ns
  74  *       7 if 1.875ns > tCK >= 1.5ns
  75  *       8 if 1.5ns > tCK >= 1.25ns
  76  */
  77 static inline unsigned int compute_cas_write_latency(void)
  78 {
  79         unsigned int cwl;
  80         const unsigned int mclk_ps = get_memory_clk_period_ps();
  81
  82         if (mclk_ps >= 2500)
  83                 cwl = 5;
  84         else if (mclk_ps >= 1875)
  85                 cwl = 6;
  86         else if (mclk_ps >= 1500)
  87                 cwl = 7;
  88         else if (mclk_ps >= 1250)
  89                 cwl = 8;
  90         else
  91                 cwl = 8;
  92         return cwl;
  93 }
  94
  95 /* Chip Select Configuration (CSn_CONFIG) */
  96 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
  97                                const memctl_options_t *popts,
  98                                const dimm_params_t *dimm_params)
  99 {
 100         unsigned int cs_n_en = 0; /* Chip Select enable */
 101         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 102         unsigned int intlv_ctl = 0; /* Interleaving control */
 103         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 104         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 105         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 106         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 107         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 108         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 109         int go_config = 0;
 110
 111         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 112         switch (i) {
 113         case 0:
 114                 if (dimm_params[dimm_number].n_ranks > 0) {
 115                         go_config = 1;
 116                         /* These fields only available in CS0_CONFIG */
 117                         intlv_en = popts->memctl_interleaving;
 118                         intlv_ctl = popts->memctl_interleaving_mode;
 119                 }
 120                 break;
 121         case 1:
 122                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 123                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 124                         go_config = 1;
 125                 break;
 126         case 2:
 127                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 128                    (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
 129                         go_config = 1;
 130                 break;
 131         case 3:
 132                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 133                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 134                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 135                         go_config = 1;
 136                 break;
 137         default:
 138                 break;
 139         }
 140         if (go_config) {
 141                 unsigned int n_banks_per_sdram_device;
 142                 cs_n_en = 1;
 143                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 144                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 145                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 146                 n_banks_per_sdram_device
 147                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 148                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 149                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 150                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 151         }
 152         ddr->cs[i].config = (0
 153                 | ((cs_n_en & 0x1) << 31)
 154                 | ((intlv_en & 0x3) << 29)
 155                 | ((intlv_ctl & 0xf) << 24)
 156                 | ((ap_n_en & 0x1) << 23)
 157
 158                 /* XXX: some implementation only have 1 bit starting at left */
 159                 | ((odt_rd_cfg & 0x7) << 20)
 160
 161                 /* XXX: Some implementation only have 1 bit starting at left */
 162                 | ((odt_wr_cfg & 0x7) << 16)
 163
 164                 | ((ba_bits_cs_n & 0x3) << 14)
 165                 | ((row_bits_cs_n & 0x7) << 8)
 166                 | ((col_bits_cs_n & 0x7) << 0)
 167                 );
 168         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 169 }
 170
 171 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 172 /* FIXME: 8572 */
 173 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 174 {
 175         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 176
 177         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 178         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 179 }
 180
 181 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 182
 183 #if !defined(CONFIG_FSL_DDR1)
 184 /*
 185  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 186  *
 187  * Avoid writing for DDR I.  The new PQ38 DDR controller
 188  * dreams up non-zero default values to be backwards compatible.
 189  */
 190 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 191 {
 192         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 193         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 194         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 195         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 196         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 197
 198         /* Active powerdown exit timing (tXARD and tXARDS). */
 199         unsigned char act_pd_exit_mclk;
 200         /* Precharge powerdown exit timing (tXP). */
 201         unsigned char pre_pd_exit_mclk;
 202         /* ODT powerdown exit timing (tAXPD). */
 203         unsigned char taxpd_mclk;
 204         /* Mode register set cycle time (tMRD). */
 205         unsigned char tmrd_mclk;
 206
 207 #if defined(CONFIG_FSL_DDR3)
 208         /*
 209          * (tXARD and tXARDS). Empirical?
 210          * The DDR3 spec has not tXARD,
 211          * we use the tXP instead of it.
 212          * tXP=max(3nCK, 7.5ns) for DDR3.
 213          * spec has not the tAXPD, we use
 214          * tAXPD=1, need design to confirm.
 215          */
 216         int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
 217         act_pd_exit_mclk = picos_to_mclk(tXP);
 218         /* Mode register MR0[A12] is '1' - fast exit */
 219         pre_pd_exit_mclk = act_pd_exit_mclk;
 220         taxpd_mclk = 1;
 221         tmrd_mclk = 4;
 222         /* set the turnaround time */
 223         trwt_mclk = 1;
 224 #else /* CONFIG_FSL_DDR2 */
 225         /*
 226          * (tXARD and tXARDS). Empirical?
 227          * tXARD = 2 for DDR2
 228          * tXP=2
 229          * tAXPD=8
 230          */
 231         act_pd_exit_mclk = 2;
 232         pre_pd_exit_mclk = 2;
 233         taxpd_mclk = 8;
 234         tmrd_mclk = 2;
 235 #endif
 236
 237         ddr->timing_cfg_0 = (0
 238                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 239                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 240                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 241                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 242                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 243                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 244                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 245                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 246                 );
 247         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 248 }
 249 #endif  /* defined(CONFIG_FSL_DDR2) */
 250
 251 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 252 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 253                                const common_timing_params_t *common_dimm,
 254                                unsigned int cas_latency)
 255 {
 256         /* Extended Activate to precharge interval (tRAS) */
 257         unsigned int ext_acttopre = 0;
 258         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 259         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 260         unsigned int cntl_adj = 0; /* Control Adjust */
 261
 262         /* If the tRAS > 19 MCLK, we use the ext mode */
 263         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 264                 ext_acttopre = 1;
 265
 266         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 267
 268         /* If the CAS latency more than 8, use the ext mode */
 269         if (cas_latency > 8)
 270                 ext_caslat = 1;
 271
 272         ddr->timing_cfg_3 = (0
 273                 | ((ext_acttopre & 0x1) << 24)
 274                 | ((ext_refrec & 0xF) << 16)
 275                 | ((ext_caslat & 0x1) << 12)
 276                 | ((cntl_adj & 0x7) << 0)
 277                 );
 278         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 279 }
 280
 281 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 282 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 283                                const memctl_options_t *popts,
 284                                const common_timing_params_t *common_dimm,
 285                                unsigned int cas_latency)
 286 {
 287         /* Precharge-to-activate interval (tRP) */
 288         unsigned char pretoact_mclk;
 289         /* Activate to precharge interval (tRAS) */
 290         unsigned char acttopre_mclk;
 291         /*  Activate to read/write interval (tRCD) */
 292         unsigned char acttorw_mclk;
 293         /* CASLAT */
 294         unsigned char caslat_ctrl;
 295         /*  Refresh recovery time (tRFC) ; trfc_low */
 296         unsigned char refrec_ctrl;
 297         /* Last data to precharge minimum interval (tWR) */
 298         unsigned char wrrec_mclk;
 299         /* Activate-to-activate interval (tRRD) */
 300         unsigned char acttoact_mclk;
 301         /* Last write data pair to read command issue interval (tWTR) */
 302         unsigned char wrtord_mclk;
 303
 304         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 305         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 306         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 307
 308         /*
 309          * Translate CAS Latency to a DDR controller field value:
 310          *
 311          *      CAS Lat DDR I   DDR II  Ctrl
 312          *      Clocks  SPD Bit SPD Bit Value
 313          *      ------- ------- ------- -----
 314          *      1.0     0               0001
 315          *      1.5     1               0010
 316          *      2.0     2       2       0011
 317          *      2.5     3               0100
 318          *      3.0     4       3       0101
 319          *      3.5     5               0110
 320          *      4.0             4       0111
 321          *      4.5                     1000
 322          *      5.0             5       1001
 323          */
 324 #if defined(CONFIG_FSL_DDR1)
 325         caslat_ctrl = (cas_latency + 1) & 0x07;
 326 #elif defined(CONFIG_FSL_DDR2)
 327         caslat_ctrl = 2 * cas_latency - 1;
 328 #else
 329         /*
 330          * if the CAS latency more than 8 cycle,
 331          * we need set extend bit for it at
 332          * TIMING_CFG_3[EXT_CASLAT]
 333          */
 334         if (cas_latency > 8)
 335                 cas_latency -= 8;
 336         caslat_ctrl = 2 * cas_latency - 1;
 337 #endif
 338
 339         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 340         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 341         if (popts->OTF_burst_chop_en)
 342                 wrrec_mclk += 2;
 343
 344         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 345         /*
 346          * JEDEC has min requirement for tRRD
 347          */
 348 #if defined(CONFIG_FSL_DDR3)
 349         if (acttoact_mclk < 4)
 350                 acttoact_mclk = 4;
 351 #endif
 352         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 353         /*
 354          * JEDEC has some min requirements for tWTR
 355          */
 356 #if defined(CONFIG_FSL_DDR2)
 357         if (wrtord_mclk < 2)
 358                 wrtord_mclk = 2;
 359 #elif defined(CONFIG_FSL_DDR3)
 360         if (wrtord_mclk < 4)
 361                 wrtord_mclk = 4;
 362 #endif
 363         if (popts->OTF_burst_chop_en)
 364                 wrtord_mclk += 2;
 365
 366         ddr->timing_cfg_1 = (0
 367                 | ((pretoact_mclk & 0x0F) << 28)
 368                 | ((acttopre_mclk & 0x0F) << 24)
 369                 | ((acttorw_mclk & 0xF) << 20)
 370                 | ((caslat_ctrl & 0xF) << 16)
 371                 | ((refrec_ctrl & 0xF) << 12)
 372                 | ((wrrec_mclk & 0x0F) << 8)
 373                 | ((acttoact_mclk & 0x07) << 4)
 374                 | ((wrtord_mclk & 0x07) << 0)
 375                 );
 376         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 377 }
 378
 379 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 380 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 381                                const memctl_options_t *popts,
 382                                const common_timing_params_t *common_dimm,
 383                                unsigned int cas_latency,
 384                                unsigned int additive_latency)
 385 {
 386         /* Additive latency */
 387         unsigned char add_lat_mclk;
 388         /* CAS-to-preamble override */
 389         unsigned short cpo;
 390         /* Write latency */
 391         unsigned char wr_lat;
 392         /*  Read to precharge (tRTP) */
 393         unsigned char rd_to_pre;
 394         /* Write command to write data strobe timing adjustment */
 395         unsigned char wr_data_delay;
 396         /* Minimum CKE pulse width (tCKE) */
 397         unsigned char cke_pls;
 398         /* Window for four activates (tFAW) */
 399         unsigned short four_act;
 400
 401         /* FIXME add check that this must be less than acttorw_mclk */
 402         add_lat_mclk = additive_latency;
 403         cpo = popts->cpo_override;
 404
 405 #if defined(CONFIG_FSL_DDR1)
 406         /*
 407          * This is a lie.  It should really be 1, but if it is
 408          * set to 1, bits overlap into the old controller's
 409          * otherwise unused ACSM field.  If we leave it 0, then
 410          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 411          */
 412         wr_lat = 0;
 413 #elif defined(CONFIG_FSL_DDR2)
 414         wr_lat = cas_latency - 1;
 415 #else
 416         wr_lat = compute_cas_write_latency();
 417 #endif
 418
 419         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 420         /*
 421          * JEDEC has some min requirements for tRTP
 422          */
 423 #if defined(CONFIG_FSL_DDR2)
 424         if (rd_to_pre  < 2)
 425                 rd_to_pre  = 2;
 426 #elif defined(CONFIG_FSL_DDR3)
 427         if (rd_to_pre < 4)
 428                 rd_to_pre = 4;
 429 #endif
 430         if (additive_latency)
 431                 rd_to_pre += additive_latency;
 432         if (popts->OTF_burst_chop_en)
 433                 rd_to_pre += 2; /* according to UM */
 434
 435         wr_data_delay = popts->write_data_delay;
 436         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 437         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 438
 439         ddr->timing_cfg_2 = (0
 440                 | ((add_lat_mclk & 0xf) << 28)
 441                 | ((cpo & 0x1f) << 23)
 442                 | ((wr_lat & 0xf) << 19)
 443                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 444                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 445                 | ((cke_pls & 0x7) << 6)
 446                 | ((four_act & 0x3f) << 0)
 447                 );
 448         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 449 }
 450
 451 /* DDR SDRAM Register Control Word */
 452 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 453                                const common_timing_params_t *common_dimm)
 454 {
 455         if (common_dimm->all_DIMMs_registered
 456                 && !common_dimm->all_DIMMs_unbuffered) {
 457                 ddr->ddr_sdram_rcw_1 =
 458                         common_dimm->rcw[0] << 28 | \
 459                         common_dimm->rcw[1] << 24 | \
 460                         common_dimm->rcw[2] << 20 | \
 461                         common_dimm->rcw[3] << 16 | \
 462                         common_dimm->rcw[4] << 12 | \
 463                         common_dimm->rcw[5] << 8 | \
 464                         common_dimm->rcw[6] << 4 | \
 465                         common_dimm->rcw[7];
 466                 ddr->ddr_sdram_rcw_2 =
 467                         common_dimm->rcw[8] << 28 | \
 468                         common_dimm->rcw[9] << 24 | \
 469                         common_dimm->rcw[10] << 20 | \
 470                         common_dimm->rcw[11] << 16 | \
 471                         common_dimm->rcw[12] << 12 | \
 472                         common_dimm->rcw[13] << 8 | \
 473                         common_dimm->rcw[14] << 4 | \
 474                         common_dimm->rcw[15];
 475                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 476                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 477         }
 478 }
 479
 480 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 481 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 482                                const memctl_options_t *popts,
 483                                const common_timing_params_t *common_dimm)
 484 {
 485         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 486         unsigned int sren;              /* Self refresh enable (during sleep) */
 487         unsigned int ecc_en;            /* ECC enable. */
 488         unsigned int rd_en;             /* Registered DIMM enable */
 489         unsigned int sdram_type;        /* Type of SDRAM */
 490         unsigned int dyn_pwr;           /* Dynamic power management mode */
 491         unsigned int dbw;               /* DRAM dta bus width */
 492         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 493         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 494         unsigned int threeT_en;         /* Enable 3T timing */
 495         unsigned int twoT_en;           /* Enable 2T timing */
 496         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 497         unsigned int x32_en = 0;        /* x32 enable */
 498         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 499         unsigned int hse;               /* Global half strength override */
 500         unsigned int mem_halt = 0;      /* memory controller halt */
 501         unsigned int bi = 0;            /* Bypass initialization */
 502
 503         mem_en = 1;
 504         sren = popts->self_refresh_in_sleep;
 505         if (common_dimm->all_DIMMs_ECC_capable) {
 506                 /* Allow setting of ECC only if all DIMMs are ECC. */
 507                 ecc_en = popts->ECC_mode;
 508         } else {
 509                 ecc_en = 0;
 510         }
 511
 512         rd_en = (common_dimm->all_DIMMs_registered
 513                  && !common_dimm->all_DIMMs_unbuffered);
 514
 515         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 516
 517         dyn_pwr = popts->dynamic_power;
 518         dbw = popts->data_bus_width;
 519         /* 8-beat burst enable DDR-III case
 520          * we must clear it when use the on-the-fly mode,
 521          * must set it when use the 32-bits bus mode.
 522          */
 523         if (sdram_type == SDRAM_TYPE_DDR3) {
 524                 if (popts->burst_length == DDR_BL8)
 525                         eight_be = 1;
 526                 if (popts->burst_length == DDR_OTF)
 527                         eight_be = 0;
 528                 if (dbw == 0x1)
 529                         eight_be = 1;
 530         }
 531
 532         threeT_en = popts->threeT_en;
 533         twoT_en = popts->twoT_en;
 534         ba_intlv_ctl = popts->ba_intlv_ctl;
 535         hse = popts->half_strength_driver_enable;
 536
 537         ddr->ddr_sdram_cfg = (0
 538                         | ((mem_en & 0x1) << 31)
 539                         | ((sren & 0x1) << 30)
 540                         | ((ecc_en & 0x1) << 29)
 541                         | ((rd_en & 0x1) << 28)
 542                         | ((sdram_type & 0x7) << 24)
 543                         | ((dyn_pwr & 0x1) << 21)
 544                         | ((dbw & 0x3) << 19)
 545                         | ((eight_be & 0x1) << 18)
 546                         | ((ncap & 0x1) << 17)
 547                         | ((threeT_en & 0x1) << 16)
 548                         | ((twoT_en & 0x1) << 15)
 549                         | ((ba_intlv_ctl & 0x7F) << 8)
 550                         | ((x32_en & 0x1) << 5)
 551                         | ((pchb8 & 0x1) << 4)
 552                         | ((hse & 0x1) << 3)
 553                         | ((mem_halt & 0x1) << 1)
 554                         | ((bi & 0x1) << 0)
 555                         );
 556         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 557 }
 558
 559 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 560 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 561                                const memctl_options_t *popts)
 562 {
 563         unsigned int frc_sr = 0;        /* Force self refresh */
 564         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 565         unsigned int dll_rst_dis;       /* DLL reset disable */
 566         unsigned int dqs_cfg;           /* DQS configuration */
 567         unsigned int odt_cfg;           /* ODT configuration */
 568         unsigned int num_pr;            /* Number of posted refreshes */
 569         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 570         unsigned int ap_en;             /* Address Parity Enable */
 571         unsigned int d_init;            /* DRAM data initialization */
 572         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 573         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 574         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 575
 576         dll_rst_dis = 1;        /* Make this configurable */
 577         dqs_cfg = popts->DQS_config;
 578         if (popts->cs_local_opts[0].odt_rd_cfg
 579             || popts->cs_local_opts[0].odt_wr_cfg) {
 580                 /* FIXME */
 581                 odt_cfg = 2;
 582         } else {
 583                 odt_cfg = 0;
 584         }
 585
 586         num_pr = 1;     /* Make this configurable */
 587
 588         /*
 589          * 8572 manual says
 590          *     {TIMING_CFG_1[PRETOACT]
 591          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 592          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 593          *      << DDR_SDRAM_INTERVAL[REFINT]
 594          */
 595 #if defined(CONFIG_FSL_DDR3)
 596         obc_cfg = popts->OTF_burst_chop_en;
 597 #else
 598         obc_cfg = 0;
 599 #endif
 600
 601         ap_en = 0;      /* Make this configurable? */
 602
 603 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 604         /* Use the DDR controller to auto initialize memory. */
 605         d_init = 1;
 606         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 607         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 608 #else
 609         /* Memory will be initialized via DMA, or not at all. */
 610         d_init = 0;
 611 #endif
 612
 613 #if defined(CONFIG_FSL_DDR3)
 614         md_en = popts->mirrored_dimm;
 615 #endif
 616         qd_en = popts->quad_rank_present ? 1 : 0;
 617         ddr->ddr_sdram_cfg_2 = (0
 618                 | ((frc_sr & 0x1) << 31)
 619                 | ((sr_ie & 0x1) << 30)
 620                 | ((dll_rst_dis & 0x1) << 29)
 621                 | ((dqs_cfg & 0x3) << 26)
 622                 | ((odt_cfg & 0x3) << 21)
 623                 | ((num_pr & 0xf) << 12)
 624                 | (qd_en << 9)
 625                 | ((obc_cfg & 0x1) << 6)
 626                 | ((ap_en & 0x1) << 5)
 627                 | ((d_init & 0x1) << 4)
 628                 | ((rcw_en & 0x1) << 2)
 629                 | ((md_en & 0x1) << 0)
 630                 );
 631         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 632 }
 633
 634 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 635 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 636                                 const memctl_options_t *popts)
 637 {
 638         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 639         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 640
 641 #if defined(CONFIG_FSL_DDR3)
 642         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 643         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 644         unsigned int asr = 0;   /* auto self-refresh disable */
 645         unsigned int cwl = compute_cas_write_latency() - 5;
 646         unsigned int pasr = 0;  /* partial array self refresh disable */
 647
 648         if (popts->rtt_override)
 649                 rtt_wr = popts->rtt_wr_override_value;
 650
 651         esdmode2 = (0
 652                 | ((rtt_wr & 0x3) << 9)
 653                 | ((srt & 0x1) << 7)
 654                 | ((asr & 0x1) << 6)
 655                 | ((cwl & 0x7) << 3)
 656                 | ((pasr & 0x7) << 0));
 657 #endif
 658         ddr->ddr_sdram_mode_2 = (0
 659                                  | ((esdmode2 & 0xFFFF) << 16)
 660                                  | ((esdmode3 & 0xFFFF) << 0)
 661                                  );
 662         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 663 }
 664
 665 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 666 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 667                                const memctl_options_t *popts,
 668                                const common_timing_params_t *common_dimm)
 669 {
 670         unsigned int refint;    /* Refresh interval */
 671         unsigned int bstopre;   /* Precharge interval */
 672
 673         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 674
 675         bstopre = popts->bstopre;
 676
 677         /* refint field used 0x3FFF in earlier controllers */
 678         ddr->ddr_sdram_interval = (0
 679                                    | ((refint & 0xFFFF) << 16)
 680                                    | ((bstopre & 0x3FFF) << 0)
 681                                    );
 682         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 683 }
 684
 685 #if defined(CONFIG_FSL_DDR3)
 686 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 687 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 688                                const memctl_options_t *popts,
 689                                const common_timing_params_t *common_dimm,
 690                                unsigned int cas_latency,
 691                                unsigned int additive_latency)
 692 {
 693         unsigned short esdmode;         /* Extended SDRAM mode */
 694         unsigned short sdmode;          /* SDRAM mode */
 695
 696         /* Mode Register - MR1 */
 697         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
 698         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
 699         unsigned int rtt;
 700         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
 701         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
 702         unsigned int dic = 1;           /* Output driver impedance, 34ohm */
 703         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 704                                                        1=Disable (Test/Debug) */
 705
 706         /* Mode Register - MR0 */
 707         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
 708         unsigned int wr;        /* Write Recovery */
 709         unsigned int dll_rst;   /* DLL Reset */
 710         unsigned int mode;      /* Normal=0 or Test=1 */
 711         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
 712         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
 713         unsigned int bt;
 714         unsigned int bl;        /* BL: Burst Length */
 715
 716         unsigned int wr_mclk;
 717
 718         const unsigned int mclk_ps = get_memory_clk_period_ps();
 719
 720         rtt = fsl_ddr_get_rtt();
 721         if (popts->rtt_override)
 722                 rtt = popts->rtt_override_value;
 723
 724         if (additive_latency == (cas_latency - 1))
 725                 al = 1;
 726         if (additive_latency == (cas_latency - 2))
 727                 al = 2;
 728
 729         /*
 730          * The esdmode value will also be used for writing
 731          * MR1 during write leveling for DDR3, although the
 732          * bits specifically related to the write leveling
 733          * scheme will be handled automatically by the DDR
 734          * controller. so we set the wrlvl_en = 0 here.
 735          */
 736         esdmode = (0
 737                 | ((qoff & 0x1) << 12)
 738                 | ((tdqs_en & 0x1) << 11)
 739                 | ((rtt & 0x4) << 7)   /* rtt field is split */
 740                 | ((wrlvl_en & 0x1) << 7)
 741                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 742                 | ((dic & 0x2) << 4)   /* DIC field is split */
 743                 | ((al & 0x3) << 3)
 744                 | ((rtt & 0x1) << 2)  /* rtt field is split */
 745                 | ((dic & 0x1) << 1)   /* DIC field is split */
 746                 | ((dll_en & 0x1) << 0)
 747                 );
 748
 749         /*
 750          * DLL control for precharge PD
 751          * 0=slow exit DLL off (tXPDLL)
 752          * 1=fast exit DLL on (tXP)
 753          */
 754         dll_on = 1;
 755         wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
 756         if (wr_mclk >= 12)
 757                 wr = 6;
 758         else if (wr_mclk >= 9)
 759                 wr = 5;
 760         else
 761                 wr = wr_mclk - 4;
 762         dll_rst = 0;    /* dll no reset */
 763         mode = 0;       /* normal mode */
 764
 765         /* look up table to get the cas latency bits */
 766         if (cas_latency >= 5 && cas_latency <= 11) {
 767                 unsigned char cas_latency_table[7] = {
 768                         0x2,    /* 5 clocks */
 769                         0x4,    /* 6 clocks */
 770                         0x6,    /* 7 clocks */
 771                         0x8,    /* 8 clocks */
 772                         0xa,    /* 9 clocks */
 773                         0xc,    /* 10 clocks */
 774                         0xe     /* 11 clocks */
 775                 };
 776                 caslat = cas_latency_table[cas_latency - 5];
 777         }
 778         bt = 0; /* Nibble sequential */
 779
 780         switch (popts->burst_length) {
 781         case DDR_BL8:
 782                 bl = 0;
 783                 break;
 784         case DDR_OTF:
 785                 bl = 1;
 786                 break;
 787         case DDR_BC4:
 788                 bl = 2;
 789                 break;
 790         default:
 791                 printf("Error: invalid burst length of %u specified. "
 792                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
 793                         popts->burst_length);
 794                 bl = 1;
 795                 break;
 796         }
 797
 798         sdmode = (0
 799                   | ((dll_on & 0x1) << 12)
 800                   | ((wr & 0x7) << 9)
 801                   | ((dll_rst & 0x1) << 8)
 802                   | ((mode & 0x1) << 7)
 803                   | (((caslat >> 1) & 0x7) << 4)
 804                   | ((bt & 0x1) << 3)
 805                   | ((bl & 0x3) << 0)
 806                   );
 807
 808         ddr->ddr_sdram_mode = (0
 809                                | ((esdmode & 0xFFFF) << 16)
 810                                | ((sdmode & 0xFFFF) << 0)
 811                                );
 812
 813         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 814 }
 815
 816 #else /* !CONFIG_FSL_DDR3 */
 817
 818 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 819 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 820                                const memctl_options_t *popts,
 821                                const common_timing_params_t *common_dimm,
 822                                unsigned int cas_latency,
 823                                unsigned int additive_latency)
 824 {
 825         unsigned short esdmode;         /* Extended SDRAM mode */
 826         unsigned short sdmode;          /* SDRAM mode */
 827
 828         /*
 829          * FIXME: This ought to be pre-calculated in a
 830          * technology-specific routine,
 831          * e.g. compute_DDR2_mode_register(), and then the
 832          * sdmode and esdmode passed in as part of common_dimm.
 833          */
 834
 835         /* Extended Mode Register */
 836         unsigned int mrs = 0;           /* Mode Register Set */
 837         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
 838         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
 839         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
 840         unsigned int ocd = 0;           /* 0x0=OCD not supported,
 841                                            0x7=OCD default state */
 842         unsigned int rtt;
 843         unsigned int al;                /* Posted CAS# additive latency (AL) */
 844         unsigned int ods = 0;           /* Output Drive Strength:
 845                                                 0 = Full strength (18ohm)
 846                                                 1 = Reduced strength (4ohm) */
 847         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 848                                                        1=Disable (Test/Debug) */
 849
 850         /* Mode Register (MR) */
 851         unsigned int mr;        /* Mode Register Definition */
 852         unsigned int pd;        /* Power-Down Mode */
 853         unsigned int wr;        /* Write Recovery */
 854         unsigned int dll_res;   /* DLL Reset */
 855         unsigned int mode;      /* Normal=0 or Test=1 */
 856         unsigned int caslat = 0;/* CAS# latency */
 857         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
 858         unsigned int bt;
 859         unsigned int bl;        /* BL: Burst Length */
 860
 861 #if defined(CONFIG_FSL_DDR2)
 862         const unsigned int mclk_ps = get_memory_clk_period_ps();
 863 #endif
 864
 865         rtt = fsl_ddr_get_rtt();
 866
 867         al = additive_latency;
 868
 869         esdmode = (0
 870                 | ((mrs & 0x3) << 14)
 871                 | ((outputs & 0x1) << 12)
 872                 | ((rdqs_en & 0x1) << 11)
 873                 | ((dqs_en & 0x1) << 10)
 874                 | ((ocd & 0x7) << 7)
 875                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 876                 | ((al & 0x7) << 3)
 877                 | ((rtt & 0x1) << 2)   /* rtt field is split */
 878                 | ((ods & 0x1) << 1)
 879                 | ((dll_en & 0x1) << 0)
 880                 );
 881
 882         mr = 0;          /* FIXME: CHECKME */
 883
 884         /*
 885          * 0 = Fast Exit (Normal)
 886          * 1 = Slow Exit (Low Power)
 887          */
 888         pd = 0;
 889
 890 #if defined(CONFIG_FSL_DDR1)
 891         wr = 0;       /* Historical */
 892 #elif defined(CONFIG_FSL_DDR2)
 893         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
 894 #endif
 895         dll_res = 0;
 896         mode = 0;
 897
 898 #if defined(CONFIG_FSL_DDR1)
 899         if (1 <= cas_latency && cas_latency <= 4) {
 900                 unsigned char mode_caslat_table[4] = {
 901                         0x5,    /* 1.5 clocks */
 902                         0x2,    /* 2.0 clocks */
 903                         0x6,    /* 2.5 clocks */
 904                         0x3     /* 3.0 clocks */
 905                 };
 906                 caslat = mode_caslat_table[cas_latency - 1];
 907         } else {
 908                 printf("Warning: unknown cas_latency %d\n", cas_latency);
 909         }
 910 #elif defined(CONFIG_FSL_DDR2)
 911         caslat = cas_latency;
 912 #endif
 913         bt = 0;
 914
 915         switch (popts->burst_length) {
 916         case DDR_BL4:
 917                 bl = 2;
 918                 break;
 919         case DDR_BL8:
 920                 bl = 3;
 921                 break;
 922         default:
 923                 printf("Error: invalid burst length of %u specified. "
 924                         " Defaulting to 4 beats.\n",
 925                         popts->burst_length);
 926                 bl = 2;
 927                 break;
 928         }
 929
 930         sdmode = (0
 931                   | ((mr & 0x3) << 14)
 932                   | ((pd & 0x1) << 12)
 933                   | ((wr & 0x7) << 9)
 934                   | ((dll_res & 0x1) << 8)
 935                   | ((mode & 0x1) << 7)
 936                   | ((caslat & 0x7) << 4)
 937                   | ((bt & 0x1) << 3)
 938                   | ((bl & 0x7) << 0)
 939                   );
 940
 941         ddr->ddr_sdram_mode = (0
 942                                | ((esdmode & 0xFFFF) << 16)
 943                                | ((sdmode & 0xFFFF) << 0)
 944                                );
 945         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 946 }
 947 #endif
 948
 949 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
 950 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 951 {
 952         unsigned int init_value;        /* Initialization value */
 953
 954         init_value = 0xDEADBEEF;
 955         ddr->ddr_data_init = init_value;
 956 }
 957
 958 /*
 959  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
 960  * The old controller on the 8540/60 doesn't have this register.
 961  * Hope it's OK to set it (to 0) anyway.
 962  */
 963 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 964                                          const memctl_options_t *popts)
 965 {
 966         unsigned int clk_adjust;        /* Clock adjust */
 967
 968         clk_adjust = popts->clk_adjust;
 969         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
 970         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 971 }
 972
 973 /* DDR Initialization Address (DDR_INIT_ADDR) */
 974 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
 975 {
 976         unsigned int init_addr = 0;     /* Initialization address */
 977
 978         ddr->ddr_init_addr = init_addr;
 979 }
 980
 981 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
 982 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
 983 {
 984         unsigned int uia = 0;   /* Use initialization address */
 985         unsigned int init_ext_addr = 0; /* Initialization address */
 986
 987         ddr->ddr_init_ext_addr = (0
 988                                   | ((uia & 0x1) << 31)
 989                                   | (init_ext_addr & 0xF)
 990                                   );
 991 }
 992
 993 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
 994 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
 995                                 const memctl_options_t *popts)
 996 {
 997         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
 998         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
 999         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1000         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1001         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1002
1003 #if defined(CONFIG_FSL_DDR3)
1004         if (popts->burst_length == DDR_BL8) {
1005                 /* We set BL/2 for fixed BL8 */
1006                 rrt = 0;        /* BL/2 clocks */
1007                 wwt = 0;        /* BL/2 clocks */
1008         } else {
1009                 /* We need to set BL/2 + 2 to BC4 and OTF */
1010                 rrt = 2;        /* BL/2 + 2 clocks */
1011                 wwt = 2;        /* BL/2 + 2 clocks */
1012         }
1013         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1014 #endif
1015         ddr->timing_cfg_4 = (0
1016                              | ((rwt & 0xf) << 28)
1017                              | ((wrt & 0xf) << 24)
1018                              | ((rrt & 0xf) << 20)
1019                              | ((wwt & 0xf) << 16)
1020                              | (dll_lock & 0x3)
1021                              );
1022         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1023 }
1024
1025 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1026 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
1027 {
1028         unsigned int rodt_on = 0;       /* Read to ODT on */
1029         unsigned int rodt_off = 0;      /* Read to ODT off */
1030         unsigned int wodt_on = 0;       /* Write to ODT on */
1031         unsigned int wodt_off = 0;      /* Write to ODT off */
1032
1033 #if defined(CONFIG_FSL_DDR3)
1034         rodt_on = 2;    /*  2 clocks */
1035         rodt_off = 4;   /*  4 clocks */
1036         wodt_on = 1;    /*  1 clocks */
1037         wodt_off = 4;   /*  4 clocks */
1038 #endif
1039
1040         ddr->timing_cfg_5 = (0
1041                              | ((rodt_on & 0x1f) << 24)
1042                              | ((rodt_off & 0x7) << 20)
1043                              | ((wodt_on & 0x1f) << 12)
1044                              | ((wodt_off & 0x7) << 8)
1045                              );
1046         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1047 }
1048
1049 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1050 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1051 {
1052         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1053         /* Normal Operation Full Calibration Time (tZQoper) */
1054         unsigned int zqoper = 0;
1055         /* Normal Operation Short Calibration Time (tZQCS) */
1056         unsigned int zqcs = 0;
1057
1058         if (zq_en) {
1059                 zqinit = 9;     /* 512 clocks */
1060                 zqoper = 8;     /* 256 clocks */
1061                 zqcs = 6;       /* 64 clocks */
1062         }
1063
1064         ddr->ddr_zq_cntl = (0
1065                             | ((zq_en & 0x1) << 31)
1066                             | ((zqinit & 0xF) << 24)
1067                             | ((zqoper & 0xF) << 16)
1068                             | ((zqcs & 0xF) << 8)
1069                             );
1070 }
1071
1072 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1073 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1074                                 const memctl_options_t *popts)
1075 {
1076         /*
1077          * First DQS pulse rising edge after margining mode
1078          * is programmed (tWL_MRD)
1079          */
1080         unsigned int wrlvl_mrd = 0;
1081         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1082         unsigned int wrlvl_odten = 0;
1083         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1084         unsigned int wrlvl_dqsen = 0;
1085         /* WRLVL_SMPL: Write leveling sample time */
1086         unsigned int wrlvl_smpl = 0;
1087         /* WRLVL_WLR: Write leveling repeition time */
1088         unsigned int wrlvl_wlr = 0;
1089         /* WRLVL_START: Write leveling start time */
1090         unsigned int wrlvl_start = 0;
1091
1092         /* suggest enable write leveling for DDR3 due to fly-by topology */
1093         if (wrlvl_en) {
1094                 /* tWL_MRD min = 40 nCK, we set it 64 */
1095                 wrlvl_mrd = 0x6;
1096                 /* tWL_ODTEN 128 */
1097                 wrlvl_odten = 0x7;
1098                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1099                 wrlvl_dqsen = 0x5;
1100                 /*
1101                  * Write leveling sample time at least need 6 clocks
1102                  * higher than tWLO to allow enough time for progagation
1103                  * delay and sampling the prime data bits.
1104                  */
1105                 wrlvl_smpl = 0xf;
1106                 /*
1107                  * Write leveling repetition time
1108                  * at least tWLO + 6 clocks clocks
1109                  * we set it 64
1110                  */
1111                 wrlvl_wlr = 0x6;
1112                 /*
1113                  * Write leveling start time
1114                  * The value use for the DQS_ADJUST for the first sample
1115                  * when write leveling is enabled.
1116                  */
1117                 wrlvl_start = 0x8;
1118                 /*
1119                  * Override the write leveling sample and start time
1120                  * according to specific board
1121                  */
1122                 if (popts->wrlvl_override) {
1123                         wrlvl_smpl = popts->wrlvl_sample;
1124                         wrlvl_start = popts->wrlvl_start;
1125                 }
1126         }
1127
1128         ddr->ddr_wrlvl_cntl = (0
1129                                | ((wrlvl_en & 0x1) << 31)
1130                                | ((wrlvl_mrd & 0x7) << 24)
1131                                | ((wrlvl_odten & 0x7) << 20)
1132                                | ((wrlvl_dqsen & 0x7) << 16)
1133                                | ((wrlvl_smpl & 0xf) << 12)
1134                                | ((wrlvl_wlr & 0x7) << 8)
1135                                | ((wrlvl_start & 0x1F) << 0)
1136                                );
1137 }
1138
1139 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1140 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1141 {
1142         /* Self Refresh Idle Threshold */
1143         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1144 }
1145
1146 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
1147 {
1148         if (popts->addr_hash) {
1149                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
1150                 puts("Addess hashing enabled.\n");
1151         }
1152 }
1153
1154 unsigned int
1155 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1156 {
1157         unsigned int res = 0;
1158
1159         /*
1160          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1161          * not set at the same time.
1162          */
1163         if (ddr->ddr_sdram_cfg & 0x10000000
1164             && ddr->ddr_sdram_cfg & 0x00008000) {
1165                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1166                                 " should not be set at the same time.\n");
1167                 res++;
1168         }
1169
1170         return res;
1171 }
1172
1173 unsigned int
1174 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1175                                fsl_ddr_cfg_regs_t *ddr,
1176                                const common_timing_params_t *common_dimm,
1177                                const dimm_params_t *dimm_params,
1178                                unsigned int dbw_cap_adj)
1179 {
1180         unsigned int i;
1181         unsigned int cas_latency;
1182         unsigned int additive_latency;
1183         unsigned int sr_it;
1184         unsigned int zq_en;
1185         unsigned int wrlvl_en;
1186
1187         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1188
1189         if (common_dimm == NULL) {
1190                 printf("Error: subset DIMM params struct null pointer\n");
1191                 return 1;
1192         }
1193
1194         /*
1195          * Process overrides first.
1196          *
1197          * FIXME: somehow add dereated caslat to this
1198          */
1199         cas_latency = (popts->cas_latency_override)
1200                 ? popts->cas_latency_override_value
1201                 : common_dimm->lowest_common_SPD_caslat;
1202
1203         additive_latency = (popts->additive_latency_override)
1204                 ? popts->additive_latency_override_value
1205                 : common_dimm->additive_latency;
1206
1207         sr_it = (popts->auto_self_refresh_en)
1208                 ? popts->sr_it
1209                 : 0;
1210         /* ZQ calibration */
1211         zq_en = (popts->zq_en) ? 1 : 0;
1212         /* write leveling */
1213         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1214
1215         /* Chip Select Memory Bounds (CSn_BNDS) */
1216         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1217                 unsigned long long ea = 0, sa = 0;
1218                 unsigned int cs_per_dimm
1219                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
1220                 unsigned int dimm_number
1221                         = i / cs_per_dimm;
1222                 unsigned long long rank_density
1223                         = dimm_params[dimm_number].rank_density;
1224
1225                 if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
1226                         ((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
1227                         ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
1228                         /*
1229                          * Don't set up boundaries for unused CS
1230                          * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1231                          * cs2 for cs0_cs1_cs2_cs3
1232                          * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
1233                          * But we need to set the ODT_RD_CFG and
1234                          * ODT_WR_CFG for CS1_CONFIG here.
1235                          */
1236                         set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1237                         continue;
1238                 }
1239                 if (dimm_params[dimm_number].n_ranks == 0) {
1240                         debug("Skipping setup of CS%u "
1241                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
1242                         continue;
1243                 }
1244                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1245                         /*
1246                          * This works superbank 2CS
1247                          * There are 2 or more memory controllers configured
1248                          * identically, memory is interleaved between them,
1249                          * and each controller uses rank interleaving within
1250                          * itself. Therefore the starting and ending address
1251                          * on each controller is twice the amount present on
1252                          * each controller.
1253                          */
1254                         unsigned long long ctlr_density = 0;
1255                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1256                         case FSL_DDR_CS0_CS1:
1257                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1258                                 ctlr_density = dimm_params[0].rank_density * 2;
1259                                 break;
1260                         case FSL_DDR_CS2_CS3:
1261                                 ctlr_density = dimm_params[0].rank_density;
1262                                 break;
1263                         case FSL_DDR_CS0_CS1_CS2_CS3:
1264                                 /*
1265                                  * The four CS interleaving should have been verified by
1266                                  * populate_memctl_options()
1267                                  */
1268                                 ctlr_density = dimm_params[0].rank_density * 4;
1269                                 break;
1270                         default:
1271                                 break;
1272                         }
1273                         ea = (CONFIG_NUM_DDR_CONTROLLERS *
1274                                 (ctlr_density >> dbw_cap_adj)) - 1;
1275                 }
1276                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1277                         /*
1278                          * If memory interleaving between controllers is NOT
1279                          * enabled, the starting address for each memory
1280                          * controller is distinct.  However, because rank
1281                          * interleaving is enabled, the starting and ending
1282                          * addresses of the total memory on that memory
1283                          * controller needs to be programmed into its
1284                          * respective CS0_BNDS.
1285                          */
1286                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1287                         case FSL_DDR_CS0_CS1_CS2_CS3:
1288                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1289                                  * needs to be set.
1290                                  */
1291                                 sa = common_dimm->base_address;
1292                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1293                                 break;
1294                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1295                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1296                                  * and CS2_CNDS need to be set.
1297                                  */
1298                                 if ((i == 2) && (dimm_number == 0)) {
1299                                         sa = dimm_params[dimm_number].base_address +
1300                                               2 * (rank_density >> dbw_cap_adj);
1301                                         ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
1302                                 } else {
1303                                         sa = dimm_params[dimm_number].base_address;
1304                                         ea = sa + (2 * (rank_density >>
1305                                                 dbw_cap_adj)) - 1;
1306                                 }
1307                                 break;
1308                         case FSL_DDR_CS0_CS1:
1309                                 /* CS0+CS1 interleaving, CS0_CNDS needs
1310                                  * to be set
1311                                  */
1312                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1313                                         sa = dimm_params[dimm_number].base_address;
1314                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1315                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1316                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1317                                 } else {
1318                                         sa = 0;
1319                                         ea = 0;
1320                                 }
1321                                 if (i == 0)
1322                                         ea += (rank_density >> dbw_cap_adj);
1323                                 break;
1324                         case FSL_DDR_CS2_CS3:
1325                                 /* CS2+CS3 interleaving*/
1326                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1327                                         sa = dimm_params[dimm_number].base_address;
1328                                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1329                                         sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1330                                         ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1331                                 } else {
1332                                         sa = 0;
1333                                         ea = 0;
1334                                 }
1335                                 if (i == 2)
1336                                         ea += (rank_density >> dbw_cap_adj);
1337                                 break;
1338                         default:  /* No bank(chip-select) interleaving */
1339                                 break;
1340                         }
1341                 }
1342                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1343                         /*
1344                          * Only the rank on CS0 of each memory controller may
1345                          * be used if memory controller interleaving is used
1346                          * without rank interleaving within each memory
1347                          * controller.  However, the ending address programmed
1348                          * into each CS0 must be the sum of the amount of
1349                          * memory in the two CS0 ranks.
1350                          */
1351                         if (i == 0) {
1352                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1353                         }
1354
1355                 }
1356                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1357                         /*
1358                          * No rank interleaving and no memory controller
1359                          * interleaving.
1360                          */
1361                         sa = dimm_params[dimm_number].base_address;
1362                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
1363                         if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
1364                                 sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1365                                 ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
1366                         } else {
1367                                 sa = 0;
1368                                 ea = 0;
1369                         }
1370                 }
1371
1372                 sa >>= 24;
1373                 ea >>= 24;
1374
1375                 ddr->cs[i].bnds = (0
1376                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1377                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1378                         );
1379
1380                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1381                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
1382                 set_csn_config_2(i, ddr);
1383         }
1384
1385         set_ddr_eor(ddr, popts);
1386
1387 #if !defined(CONFIG_FSL_DDR1)
1388         set_timing_cfg_0(ddr);
1389 #endif
1390
1391         set_timing_cfg_3(ddr, common_dimm, cas_latency);
1392         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1393         set_timing_cfg_2(ddr, popts, common_dimm,
1394                                 cas_latency, additive_latency);
1395
1396         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1397
1398         set_ddr_sdram_cfg_2(ddr, popts);
1399         set_ddr_sdram_mode(ddr, popts, common_dimm,
1400                                 cas_latency, additive_latency);
1401         set_ddr_sdram_mode_2(ddr, popts);
1402         set_ddr_sdram_interval(ddr, popts, common_dimm);
1403         set_ddr_data_init(ddr);
1404         set_ddr_sdram_clk_cntl(ddr, popts);
1405         set_ddr_init_addr(ddr);
1406         set_ddr_init_ext_addr(ddr);
1407         set_timing_cfg_4(ddr, popts);
1408         set_timing_cfg_5(ddr);
1409
1410         set_ddr_zq_cntl(ddr, zq_en);
1411         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1412
1413         set_ddr_sr_cntr(ddr, sr_it);
1414
1415         set_ddr_sdram_rcw(ddr, common_dimm);
1416
1417         return check_fsl_memctl_config_regs(ddr);
1418 }