arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
   3  * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
   4  * DDR controller. Those are 440GP/GX/EP/GR.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005-2007
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * See file CREDITS for list of people who contributed to this
  27  * project.
  28  *
  29  * This program is free software; you can redistribute it and/or
  30  * modify it under the terms of the GNU General Public License as
  31  * published by the Free Software Foundation; either version 2 of
  32  * the License, or (at your option) any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful,
  35  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  37  * GNU General Public License for more details.
  38  *
  39  * You should have received a copy of the GNU General Public License
  40  * along with this program; if not, write to the Free Software
  41  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  42  * MA 02111-1307 USA
  43  */
  44
  45 /* define DEBUG for debugging output (obviously ;-)) */
  46 #if 0
  47 #define DEBUG
  48 #endif
  49
  50 #include <common.h>
  51 #include <asm/processor.h>
  52 #include <i2c.h>
  53 #include <asm/ppc4xx.h>
  54 #include <asm/mmu.h>
  55
  56 #include "ecc.h"
  57
  58 #if defined(CONFIG_SPD_EEPROM) &&                                       \
  59         (defined(CONFIG_440GP) || defined(CONFIG_440GX) ||              \
  60          defined(CONFIG_440EP) || defined(CONFIG_440GR))
  61
  62 /*
  63  * Set default values
  64  */
  65 #ifndef CONFIG_SYS_I2C_SPEED
  66 #define CONFIG_SYS_I2C_SPEED    50000
  67 #endif
  68
  69 #define ONE_BILLION     1000000000
  70
  71 /*
  72  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  73  */
  74 void __spd_ddr_init_hang (void)
  75 {
  76         hang ();
  77 }
  78 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  79
  80 /*-----------------------------------------------------------------------------+
  81   |  General Definition
  82   +-----------------------------------------------------------------------------*/
  83 #define DEFAULT_SPD_ADDR1       0x53
  84 #define DEFAULT_SPD_ADDR2       0x52
  85 #define MAXBANKS                4               /* at most 4 dimm banks */
  86 #define MAX_SPD_BYTES           256
  87 #define NUMHALFCYCLES           4
  88 #define NUMMEMTESTS             8
  89 #define NUMMEMWORDS             8
  90 #define MAXBXCR                 4
  91
  92 /*
  93  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  94  * region. Right now the cache should still be disabled in U-Boot because of the
  95  * EMAC driver, that need it's buffer descriptor to be located in non cached
  96  * memory.
  97  *
  98  * If at some time this restriction doesn't apply anymore, just define
  99  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 100  * everything correctly.
 101  */
 102 #ifdef CONFIG_4xx_DCACHE
 103 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 104 #else
 105 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 106 #endif
 107
 108 /* bank_parms is used to sort the bank sizes by descending order */
 109 struct bank_param {
 110         unsigned long cr;
 111         unsigned long bank_size_bytes;
 112 };
 113
 114 typedef struct bank_param BANKPARMS;
 115
 116 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 117 extern const unsigned char cfg_simulate_spd_eeprom[128];
 118 #endif
 119
 120 static unsigned char spd_read(uchar chip, uint addr);
 121 static void get_spd_info(unsigned long *dimm_populated,
 122                          unsigned char *iic0_dimm_addr,
 123                          unsigned long num_dimm_banks);
 124 static void check_mem_type(unsigned long *dimm_populated,
 125                            unsigned char *iic0_dimm_addr,
 126                            unsigned long num_dimm_banks);
 127 static void check_volt_type(unsigned long *dimm_populated,
 128                             unsigned char *iic0_dimm_addr,
 129                             unsigned long num_dimm_banks);
 130 static void program_cfg0(unsigned long *dimm_populated,
 131                          unsigned char *iic0_dimm_addr,
 132                          unsigned long  num_dimm_banks);
 133 static void program_cfg1(unsigned long *dimm_populated,
 134                          unsigned char *iic0_dimm_addr,
 135                          unsigned long num_dimm_banks);
 136 static void program_rtr(unsigned long *dimm_populated,
 137                         unsigned char *iic0_dimm_addr,
 138                         unsigned long num_dimm_banks);
 139 static void program_tr0(unsigned long *dimm_populated,
 140                         unsigned char *iic0_dimm_addr,
 141                         unsigned long num_dimm_banks);
 142 static void program_tr1(void);
 143
 144 static unsigned long program_bxcr(unsigned long *dimm_populated,
 145                                   unsigned char *iic0_dimm_addr,
 146                                   unsigned long num_dimm_banks);
 147
 148 /*
 149  * This function is reading data from the DIMM module EEPROM over the SPD bus
 150  * and uses that to program the sdram controller.
 151  *
 152  * This works on boards that has the same schematics that the AMCC walnut has.
 153  *
 154  * BUG: Don't handle ECC memory
 155  * BUG: A few values in the TR register is currently hardcoded
 156  */
 157 long int spd_sdram(void) {
 158         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 159         unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 160         unsigned long total_size;
 161         unsigned long cfg0;
 162         unsigned long mcsts;
 163         unsigned long num_dimm_banks;               /* on board dimm banks */
 164
 165         num_dimm_banks = sizeof(iic0_dimm_addr);
 166
 167         /*
 168          * Make sure I2C controller is initialized
 169          * before continuing.
 170          */
 171         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 172
 173         /*
 174          * Read the SPD information using I2C interface. Check to see if the
 175          * DIMM slots are populated.
 176          */
 177         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 178
 179         /*
 180          * Check the memory type for the dimms plugged.
 181          */
 182         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 183
 184         /*
 185          * Check the voltage type for the dimms plugged.
 186          */
 187         check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 188
 189 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 190         /*
 191          * Soft-reset SDRAM controller.
 192          */
 193         mtsdr(SDR0_SRST, SDR0_SRST_DMC);
 194         mtsdr(SDR0_SRST, 0x00000000);
 195 #endif
 196
 197         /*
 198          * program 440GP SDRAM controller options (SDRAM0_CFG0)
 199          */
 200         program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 201
 202         /*
 203          * program 440GP SDRAM controller options (SDRAM0_CFG1)
 204          */
 205         program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 206
 207         /*
 208          * program SDRAM refresh register (SDRAM0_RTR)
 209          */
 210         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 211
 212         /*
 213          * program SDRAM Timing Register 0 (SDRAM0_TR0)
 214          */
 215         program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 216
 217         /*
 218          * program the BxCR registers to find out total sdram installed
 219          */
 220         total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 221                                   num_dimm_banks);
 222
 223 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
 224         /* and program tlb entries for this size (dynamic) */
 225         program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
 226 #endif
 227
 228         /*
 229          * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 230          */
 231         mtsdram(SDRAM0_CLKTR, 0x40000000);
 232
 233         /*
 234          * delay to ensure 200 usec has elapsed
 235          */
 236         udelay(400);
 237
 238         /*
 239          * enable the memory controller
 240          */
 241         mfsdram(SDRAM0_CFG0, cfg0);
 242         mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
 243
 244         /*
 245          * wait for SDRAM_CFG0_DC_EN to complete
 246          */
 247         while (1) {
 248                 mfsdram(SDRAM0_MCSTS, mcsts);
 249                 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
 250                         break;
 251         }
 252
 253         /*
 254          * program SDRAM Timing Register 1, adding some delays
 255          */
 256         program_tr1();
 257
 258 #ifdef CONFIG_DDR_ECC
 259         /*
 260          * If ecc is enabled, initialize the parity bits.
 261          */
 262         ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
 263 #endif
 264
 265         return total_size;
 266 }
 267
 268 static unsigned char spd_read(uchar chip, uint addr)
 269 {
 270         unsigned char data[2];
 271
 272 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 273         if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
 274                 /*
 275                  * Onboard spd eeprom requested -> simulate values
 276                  */
 277                 return cfg_simulate_spd_eeprom[addr];
 278         }
 279 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
 280
 281         if (i2c_probe(chip) == 0) {
 282                 if (i2c_read(chip, addr, 1, data, 1) == 0) {
 283                         return data[0];
 284                 }
 285         }
 286
 287         return 0;
 288 }
 289
 290 static void get_spd_info(unsigned long *dimm_populated,
 291                          unsigned char *iic0_dimm_addr,
 292                          unsigned long num_dimm_banks)
 293 {
 294         unsigned long dimm_num;
 295         unsigned long dimm_found;
 296         unsigned char num_of_bytes;
 297         unsigned char total_size;
 298
 299         dimm_found = false;
 300         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 301                 num_of_bytes = 0;
 302                 total_size = 0;
 303
 304                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 305                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 306
 307                 if ((num_of_bytes != 0) && (total_size != 0)) {
 308                         dimm_populated[dimm_num] = true;
 309                         dimm_found = true;
 310                         debug("DIMM slot %lu: populated\n", dimm_num);
 311                 } else {
 312                         dimm_populated[dimm_num] = false;
 313                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 314                 }
 315         }
 316
 317         if (dimm_found == false) {
 318                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 319                 spd_ddr_init_hang ();
 320         }
 321 }
 322
 323 static void check_mem_type(unsigned long *dimm_populated,
 324                            unsigned char *iic0_dimm_addr,
 325                            unsigned long num_dimm_banks)
 326 {
 327         unsigned long dimm_num;
 328         unsigned char dimm_type;
 329
 330         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 331                 if (dimm_populated[dimm_num] == true) {
 332                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 333                         switch (dimm_type) {
 334                         case 7:
 335                                 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 336                                 break;
 337                         default:
 338                                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 339                                        dimm_num);
 340                                 printf("Only DDR SDRAM DIMMs are supported.\n");
 341                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 342                                 spd_ddr_init_hang ();
 343                                 break;
 344                         }
 345                 }
 346         }
 347 }
 348
 349 static void check_volt_type(unsigned long *dimm_populated,
 350                             unsigned char *iic0_dimm_addr,
 351                             unsigned long num_dimm_banks)
 352 {
 353         unsigned long dimm_num;
 354         unsigned long voltage_type;
 355
 356         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 357                 if (dimm_populated[dimm_num] == true) {
 358                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 359                         if (voltage_type != 0x04) {
 360                                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 361                                        dimm_num);
 362                                 spd_ddr_init_hang ();
 363                         } else {
 364                                 debug("DIMM %lu voltage level supported.\n", dimm_num);
 365                         }
 366                         break;
 367                 }
 368         }
 369 }
 370
 371 static void program_cfg0(unsigned long *dimm_populated,
 372                          unsigned char *iic0_dimm_addr,
 373                          unsigned long num_dimm_banks)
 374 {
 375         unsigned long dimm_num;
 376         unsigned long cfg0;
 377         unsigned long ecc_enabled;
 378         unsigned char ecc;
 379         unsigned char attributes;
 380         unsigned long data_width;
 381
 382         /*
 383          * get Memory Controller Options 0 data
 384          */
 385         mfsdram(SDRAM0_CFG0, cfg0);
 386
 387         /*
 388          * clear bits
 389          */
 390         cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 391                   SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 392                   SDRAM_CFG0_DMWD_MASK |
 393                   SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 394
 395
 396         /*
 397          * FIXME: assume the DDR SDRAMs in both banks are the same
 398          */
 399         ecc_enabled = true;
 400         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 401                 if (dimm_populated[dimm_num] == true) {
 402                         ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 403                         if (ecc != 0x02) {
 404                                 ecc_enabled = false;
 405                         }
 406
 407                         /*
 408                          * program Registered DIMM Enable
 409                          */
 410                         attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 411                         if ((attributes & 0x02) != 0x00) {
 412                                 cfg0 |= SDRAM_CFG0_RDEN;
 413                         }
 414
 415                         /*
 416                          * program DDR SDRAM Data Width
 417                          */
 418                         data_width =
 419                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 420                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 421                         if (data_width == 64 || data_width == 72) {
 422                                 cfg0 |= SDRAM_CFG0_DMWD_64;
 423                         } else if (data_width == 32 || data_width == 40) {
 424                                 cfg0 |= SDRAM_CFG0_DMWD_32;
 425                         } else {
 426                                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 427                                        data_width);
 428                                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 429                                 spd_ddr_init_hang ();
 430                         }
 431                         break;
 432                 }
 433         }
 434
 435         /*
 436          * program Memory Data Error Checking
 437          */
 438         if (ecc_enabled == true) {
 439                 cfg0 |= SDRAM_CFG0_MCHK_GEN;
 440         } else {
 441                 cfg0 |= SDRAM_CFG0_MCHK_NON;
 442         }
 443
 444         /*
 445          * program Page Management Unit (0 == enabled)
 446          */
 447         cfg0 &= ~SDRAM_CFG0_PMUD;
 448
 449         /*
 450          * program Memory Controller Options 0
 451          * Note: DCEN must be enabled after all DDR SDRAM controller
 452          * configuration registers get initialized.
 453          */
 454         mtsdram(SDRAM0_CFG0, cfg0);
 455 }
 456
 457 static void program_cfg1(unsigned long *dimm_populated,
 458                          unsigned char *iic0_dimm_addr,
 459                          unsigned long num_dimm_banks)
 460 {
 461         unsigned long cfg1;
 462         mfsdram(SDRAM0_CFG1, cfg1);
 463
 464         /*
 465          * Self-refresh exit, disable PM
 466          */
 467         cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 468
 469         /*
 470          * program Memory Controller Options 1
 471          */
 472         mtsdram(SDRAM0_CFG1, cfg1);
 473 }
 474
 475 static void program_rtr(unsigned long *dimm_populated,
 476                         unsigned char *iic0_dimm_addr,
 477                         unsigned long num_dimm_banks)
 478 {
 479         unsigned long dimm_num;
 480         unsigned long bus_period_x_10;
 481         unsigned long refresh_rate = 0;
 482         unsigned char refresh_rate_type;
 483         unsigned long refresh_interval;
 484         unsigned long sdram_rtr;
 485         PPC4xx_SYS_INFO sys_info;
 486
 487         /*
 488          * get the board info
 489          */
 490         get_sys_info(&sys_info);
 491         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 492
 493         for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
 494                 if (dimm_populated[dimm_num] == true) {
 495                         refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 496                         switch (refresh_rate_type) {
 497                         case 0x00:
 498                                 refresh_rate = 15625;
 499                                 break;
 500                         case 0x01:
 501                                 refresh_rate = 15625/4;
 502                                 break;
 503                         case 0x02:
 504                                 refresh_rate = 15625/2;
 505                                 break;
 506                         case 0x03:
 507                                 refresh_rate = 15626*2;
 508                                 break;
 509                         case 0x04:
 510                                 refresh_rate = 15625*4;
 511                                 break;
 512                         case 0x05:
 513                                 refresh_rate = 15625*8;
 514                                 break;
 515                         default:
 516                                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
 517                                        dimm_num);
 518                                 printf("Replace the DIMM module with a supported DIMM.\n");
 519                                 break;
 520                         }
 521
 522                         break;
 523                 }
 524         }
 525
 526         refresh_interval = refresh_rate * 10 / bus_period_x_10;
 527         sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
 528
 529         /*
 530          * program Refresh Timer Register (SDRAM0_RTR)
 531          */
 532         mtsdram(SDRAM0_RTR, sdram_rtr);
 533 }
 534
 535 static void program_tr0(unsigned long *dimm_populated,
 536                          unsigned char *iic0_dimm_addr,
 537                          unsigned long num_dimm_banks)
 538 {
 539         unsigned long dimm_num;
 540         unsigned long tr0;
 541         unsigned char wcsbc;
 542         unsigned char t_rp_ns;
 543         unsigned char t_rcd_ns;
 544         unsigned char t_ras_ns;
 545         unsigned long t_rp_clk;
 546         unsigned long t_ras_rcd_clk;
 547         unsigned long t_rcd_clk;
 548         unsigned long t_rfc_clk;
 549         unsigned long plb_check;
 550         unsigned char cas_bit;
 551         unsigned long cas_index;
 552         unsigned char cas_2_0_available;
 553         unsigned char cas_2_5_available;
 554         unsigned char cas_3_0_available;
 555         unsigned long cycle_time_ns_x_10[3];
 556         unsigned long tcyc_3_0_ns_x_10;
 557         unsigned long tcyc_2_5_ns_x_10;
 558         unsigned long tcyc_2_0_ns_x_10;
 559         unsigned long tcyc_reg;
 560         unsigned long bus_period_x_10;
 561         PPC4xx_SYS_INFO sys_info;
 562         unsigned long residue;
 563
 564         /*
 565          * get the board info
 566          */
 567         get_sys_info(&sys_info);
 568         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 569
 570         /*
 571          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 572          */
 573         mfsdram(SDRAM0_TR0, tr0);
 574         tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
 575                  SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
 576                  SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
 577                  SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
 578
 579         /*
 580          * initialization
 581          */
 582         wcsbc = 0;
 583         t_rp_ns = 0;
 584         t_rcd_ns = 0;
 585         t_ras_ns = 0;
 586         cas_2_0_available = true;
 587         cas_2_5_available = true;
 588         cas_3_0_available = true;
 589         tcyc_2_0_ns_x_10 = 0;
 590         tcyc_2_5_ns_x_10 = 0;
 591         tcyc_3_0_ns_x_10 = 0;
 592
 593         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 594                 if (dimm_populated[dimm_num] == true) {
 595                         wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 596                         t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 597                         t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
 598                         t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
 599                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 600
 601                         for (cas_index = 0; cas_index < 3; cas_index++) {
 602                                 switch (cas_index) {
 603                                 case 0:
 604                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 605                                         break;
 606                                 case 1:
 607                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
 608                                         break;
 609                                 default:
 610                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
 611                                         break;
 612                                 }
 613
 614                                 if ((tcyc_reg & 0x0F) >= 10) {
 615                                         printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
 616                                                dimm_num);
 617                                         spd_ddr_init_hang ();
 618                                 }
 619
 620                                 cycle_time_ns_x_10[cas_index] =
 621                                         (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
 622                         }
 623
 624                         cas_index = 0;
 625
 626                         if ((cas_bit & 0x80) != 0) {
 627                                 cas_index += 3;
 628                         } else if ((cas_bit & 0x40) != 0) {
 629                                 cas_index += 2;
 630                         } else if ((cas_bit & 0x20) != 0) {
 631                                 cas_index += 1;
 632                         }
 633
 634                         if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
 635                                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 636                                 cas_index++;
 637                         } else {
 638                                 if (cas_index != 0) {
 639                                         cas_index++;
 640                                 }
 641                                 cas_3_0_available = false;
 642                         }
 643
 644                         if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
 645                                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
 646                                 cas_index++;
 647                         } else {
 648                                 if (cas_index != 0) {
 649                                         cas_index++;
 650                                 }
 651                                 cas_2_5_available = false;
 652                         }
 653
 654                         if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
 655                                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 656                                 cas_index++;
 657                         } else {
 658                                 if (cas_index != 0) {
 659                                         cas_index++;
 660                                 }
 661                                 cas_2_0_available = false;
 662                         }
 663
 664                         break;
 665                 }
 666         }
 667
 668         /*
 669          * Program SD_WR and SD_WCSBC fields
 670          */
 671         tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
 672         switch (wcsbc) {
 673         case 0:
 674                 tr0 |= SDRAM_TR0_SDWD_0_CLK;
 675                 break;
 676         default:
 677                 tr0 |= SDRAM_TR0_SDWD_1_CLK;
 678                 break;
 679         }
 680
 681         /*
 682          * Program SD_CASL field
 683          */
 684         if ((cas_2_0_available == true) &&
 685             (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 686                 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
 687         } else if ((cas_2_5_available == true) &&
 688                  (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 689                 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
 690         } else if ((cas_3_0_available == true) &&
 691                  (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 692                 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 693         } else {
 694                 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
 695                 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
 696                 printf("Make sure the PLB speed is within the supported range.\n");
 697                 spd_ddr_init_hang ();
 698         }
 699
 700         /*
 701          * Calculate Trp in clock cycles and round up if necessary
 702          * Program SD_PTA field
 703          */
 704         t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
 705         plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
 706         if (sys_info.freqPLB != plb_check) {
 707                 t_rp_clk++;
 708         }
 709         switch ((unsigned long)t_rp_clk) {
 710         case 0:
 711         case 1:
 712         case 2:
 713                 tr0 |= SDRAM_TR0_SDPA_2_CLK;
 714                 break;
 715         case 3:
 716                 tr0 |= SDRAM_TR0_SDPA_3_CLK;
 717                 break;
 718         default:
 719                 tr0 |= SDRAM_TR0_SDPA_4_CLK;
 720                 break;
 721         }
 722
 723         /*
 724          * Program SD_CTP field
 725          */
 726         t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
 727         plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
 728         if (sys_info.freqPLB != plb_check) {
 729                 t_ras_rcd_clk++;
 730         }
 731         switch (t_ras_rcd_clk) {
 732         case 0:
 733         case 1:
 734         case 2:
 735                 tr0 |= SDRAM_TR0_SDCP_2_CLK;
 736                 break;
 737         case 3:
 738                 tr0 |= SDRAM_TR0_SDCP_3_CLK;
 739                 break;
 740         case 4:
 741                 tr0 |= SDRAM_TR0_SDCP_4_CLK;
 742                 break;
 743         default:
 744                 tr0 |= SDRAM_TR0_SDCP_5_CLK;
 745                 break;
 746         }
 747
 748         /*
 749          * Program SD_LDF field
 750          */
 751         tr0 |= SDRAM_TR0_SDLD_2_CLK;
 752
 753         /*
 754          * Program SD_RFTA field
 755          * FIXME tRFC hardcoded as 75 nanoseconds
 756          */
 757         t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
 758         residue = sys_info.freqPLB % (ONE_BILLION / 75);
 759         if (residue >= (ONE_BILLION / 150)) {
 760                 t_rfc_clk++;
 761         }
 762         switch (t_rfc_clk) {
 763         case 0:
 764         case 1:
 765         case 2:
 766         case 3:
 767         case 4:
 768         case 5:
 769         case 6:
 770                 tr0 |= SDRAM_TR0_SDRA_6_CLK;
 771                 break;
 772         case 7:
 773                 tr0 |= SDRAM_TR0_SDRA_7_CLK;
 774                 break;
 775         case 8:
 776                 tr0 |= SDRAM_TR0_SDRA_8_CLK;
 777                 break;
 778         case 9:
 779                 tr0 |= SDRAM_TR0_SDRA_9_CLK;
 780                 break;
 781         case 10:
 782                 tr0 |= SDRAM_TR0_SDRA_10_CLK;
 783                 break;
 784         case 11:
 785                 tr0 |= SDRAM_TR0_SDRA_11_CLK;
 786                 break;
 787         case 12:
 788                 tr0 |= SDRAM_TR0_SDRA_12_CLK;
 789                 break;
 790         default:
 791                 tr0 |= SDRAM_TR0_SDRA_13_CLK;
 792                 break;
 793         }
 794
 795         /*
 796          * Program SD_RCD field
 797          */
 798         t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
 799         plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
 800         if (sys_info.freqPLB != plb_check) {
 801                 t_rcd_clk++;
 802         }
 803         switch (t_rcd_clk) {
 804         case 0:
 805         case 1:
 806         case 2:
 807                 tr0 |= SDRAM_TR0_SDRD_2_CLK;
 808                 break;
 809         case 3:
 810                 tr0 |= SDRAM_TR0_SDRD_3_CLK;
 811                 break;
 812         default:
 813                 tr0 |= SDRAM_TR0_SDRD_4_CLK;
 814                 break;
 815         }
 816
 817         debug("tr0: %lx\n", tr0);
 818         mtsdram(SDRAM0_TR0, tr0);
 819 }
 820
 821 static int short_mem_test(void)
 822 {
 823         unsigned long i, j;
 824         unsigned long bxcr_num;
 825         unsigned long *membase;
 826         const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 827                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 828                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
 829                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 830                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
 831                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 832                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
 833                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 834                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
 835                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 836                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
 837                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 838                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
 839                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 840                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
 841                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 842                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
 843
 844         for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
 845                 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
 846                 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
 847                         /* Bank is enabled */
 848                         membase = (unsigned long*)
 849                                 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
 850
 851                         /*
 852                          * Run the short memory test
 853                          */
 854                         for (i = 0; i < NUMMEMTESTS; i++) {
 855                                 for (j = 0; j < NUMMEMWORDS; j++) {
 856                                         /* printf("bank enabled base:%x\n", &membase[j]); */
 857                                         membase[j] = test[i][j];
 858                                         ppcDcbf((unsigned long)&(membase[j]));
 859                                 }
 860
 861                                 for (j = 0; j < NUMMEMWORDS; j++) {
 862                                         if (membase[j] != test[i][j]) {
 863                                                 ppcDcbf((unsigned long)&(membase[j]));
 864                                                 return 0;
 865                                         }
 866                                         ppcDcbf((unsigned long)&(membase[j]));
 867                                 }
 868
 869                                 if (j < NUMMEMWORDS)
 870                                         return 0;
 871                         }
 872
 873                         /*
 874                          * see if the rdclt value passed
 875                          */
 876                         if (i < NUMMEMTESTS)
 877                                 return 0;
 878                 }
 879         }
 880
 881         return 1;
 882 }
 883
 884 static void program_tr1(void)
 885 {
 886         unsigned long tr0;
 887         unsigned long tr1;
 888         unsigned long cfg0;
 889         unsigned long ecc_temp;
 890         unsigned long dlycal;
 891         unsigned long dly_val;
 892         unsigned long k;
 893         unsigned long max_pass_length;
 894         unsigned long current_pass_length;
 895         unsigned long current_fail_length;
 896         unsigned long current_start;
 897         unsigned long rdclt;
 898         unsigned long rdclt_offset;
 899         long max_start;
 900         long max_end;
 901         long rdclt_average;
 902         unsigned char window_found;
 903         unsigned char fail_found;
 904         unsigned char pass_found;
 905         PPC4xx_SYS_INFO sys_info;
 906
 907         /*
 908          * get the board info
 909          */
 910         get_sys_info(&sys_info);
 911
 912         /*
 913          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 914          */
 915         mfsdram(SDRAM0_TR1, tr1);
 916         tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
 917                  SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
 918
 919         mfsdram(SDRAM0_TR0, tr0);
 920         if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
 921             (sys_info.freqPLB > 100000000)) {
 922                 tr1 |= SDRAM_TR1_RDSS_TR2;
 923                 tr1 |= SDRAM_TR1_RDSL_STAGE3;
 924                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
 925         } else {
 926                 tr1 |= SDRAM_TR1_RDSS_TR1;
 927                 tr1 |= SDRAM_TR1_RDSL_STAGE2;
 928                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
 929         }
 930
 931         /*
 932          * save CFG0 ECC setting to a temporary variable and turn ECC off
 933          */
 934         mfsdram(SDRAM0_CFG0, cfg0);
 935         ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
 936         mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
 937
 938         /*
 939          * get the delay line calibration register value
 940          */
 941         mfsdram(SDRAM0_DLYCAL, dlycal);
 942         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
 943
 944         max_pass_length = 0;
 945         max_start = 0;
 946         max_end = 0;
 947         current_pass_length = 0;
 948         current_fail_length = 0;
 949         current_start = 0;
 950         rdclt_offset = 0;
 951         window_found = false;
 952         fail_found = false;
 953         pass_found = false;
 954         debug("Starting memory test ");
 955
 956         for (k = 0; k < NUMHALFCYCLES; k++) {
 957                 for (rdclt = 0; rdclt < dly_val; rdclt++) {
 958                         /*
 959                          * Set the timing reg for the test.
 960                          */
 961                         mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 962
 963                         if (short_mem_test()) {
 964                                 if (fail_found == true) {
 965                                         pass_found = true;
 966                                         if (current_pass_length == 0) {
 967                                                 current_start = rdclt_offset + rdclt;
 968                                         }
 969
 970                                         current_fail_length = 0;
 971                                         current_pass_length++;
 972
 973                                         if (current_pass_length > max_pass_length) {
 974                                                 max_pass_length = current_pass_length;
 975                                                 max_start = current_start;
 976                                                 max_end = rdclt_offset + rdclt;
 977                                         }
 978                                 }
 979                         } else {
 980                                 current_pass_length = 0;
 981                                 current_fail_length++;
 982
 983                                 if (current_fail_length >= (dly_val>>2)) {
 984                                         if (fail_found == false) {
 985                                                 fail_found = true;
 986                                         } else if (pass_found == true) {
 987                                                 window_found = true;
 988                                                 break;
 989                                         }
 990                                 }
 991                         }
 992                 }
 993                 debug(".");
 994
 995                 if (window_found == true)
 996                         break;
 997
 998                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
 999                 rdclt_offset += dly_val;
1000         }
1001         debug("\n");
1002
1003         /*
1004          * make sure we find the window
1005          */
1006         if (window_found == false) {
1007                 printf("ERROR: Cannot determine a common read delay.\n");
1008                 spd_ddr_init_hang ();
1009         }
1010
1011         /*
1012          * restore the orignal ECC setting
1013          */
1014         mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1015
1016         /*
1017          * set the SDRAM TR1 RDCD value
1018          */
1019         tr1 &= ~SDRAM_TR1_RDCD_MASK;
1020         if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1021                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1022         } else {
1023                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1024         }
1025
1026         /*
1027          * set the SDRAM TR1 RDCLT value
1028          */
1029         tr1 &= ~SDRAM_TR1_RDCT_MASK;
1030         while (max_end >= (dly_val << 1)) {
1031                 max_end -= (dly_val << 1);
1032                 max_start -= (dly_val << 1);
1033         }
1034
1035         rdclt_average = ((max_start + max_end) >> 1);
1036
1037         if (rdclt_average < 0) {
1038                 rdclt_average = 0;
1039         }
1040
1041         if (rdclt_average >= dly_val) {
1042                 rdclt_average -= dly_val;
1043                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1044         }
1045         tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1046
1047         debug("tr1: %lx\n", tr1);
1048
1049         /*
1050          * program SDRAM Timing Register 1 TR1
1051          */
1052         mtsdram(SDRAM0_TR1, tr1);
1053 }
1054
1055 static unsigned long program_bxcr(unsigned long *dimm_populated,
1056                                   unsigned char *iic0_dimm_addr,
1057                                   unsigned long num_dimm_banks)
1058 {
1059         unsigned long dimm_num;
1060         unsigned long bank_base_addr;
1061         unsigned long cr;
1062         unsigned long i;
1063         unsigned long j;
1064         unsigned long temp;
1065         unsigned char num_row_addr;
1066         unsigned char num_col_addr;
1067         unsigned char num_banks;
1068         unsigned char bank_size_id;
1069         unsigned long ctrl_bank_num[MAXBANKS];
1070         unsigned long bx_cr_num;
1071         unsigned long largest_size_index;
1072         unsigned long largest_size;
1073         unsigned long current_size_index;
1074         BANKPARMS bank_parms[MAXBXCR];
1075         unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1076         unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1077
1078         /*
1079          * Set the BxCR regs.  First, wipe out the bank config registers.
1080          */
1081         for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1082                 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
1083                 mtdcr(SDRAM0_CFGDATA, 0x00000000);
1084                 bank_parms[bx_cr_num].bank_size_bytes = 0;
1085         }
1086
1087 #ifdef CONFIG_BAMBOO
1088         /*
1089          * This next section is hardware dependent and must be programmed
1090          * to match the hardware.  For bamboo, the following holds...
1091          * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1092          * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1093          * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1094          * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1095          * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1096          */
1097         ctrl_bank_num[0] = 0;
1098         ctrl_bank_num[1] = 1;
1099         ctrl_bank_num[2] = 3;
1100 #else
1101         /*
1102          * Ocotea, Ebony and the other IBM/AMCC eval boards have
1103          * 2 DIMM slots with each max 2 banks
1104          */
1105         ctrl_bank_num[0] = 0;
1106         ctrl_bank_num[1] = 2;
1107 #endif
1108
1109         /*
1110          * reset the bank_base address
1111          */
1112         bank_base_addr = CONFIG_SYS_SDRAM_BASE;
1113
1114         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1115                 if (dimm_populated[dimm_num] == true) {
1116                         num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1117                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1118                         num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1119                         bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1120                         debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
1121                               num_row_addr, num_col_addr, num_banks);
1122
1123                         /*
1124                          * Set the SDRAM0_BxCR regs
1125                          */
1126                         cr = 0;
1127                         switch (bank_size_id) {
1128                         case 0x02:
1129                                 cr |= SDRAM_BXCR_SDSZ_8;
1130                                 break;
1131                         case 0x04:
1132                                 cr |= SDRAM_BXCR_SDSZ_16;
1133                                 break;
1134                         case 0x08:
1135                                 cr |= SDRAM_BXCR_SDSZ_32;
1136                                 break;
1137                         case 0x10:
1138                                 cr |= SDRAM_BXCR_SDSZ_64;
1139                                 break;
1140                         case 0x20:
1141                                 cr |= SDRAM_BXCR_SDSZ_128;
1142                                 break;
1143                         case 0x40:
1144                                 cr |= SDRAM_BXCR_SDSZ_256;
1145                                 break;
1146                         case 0x80:
1147                                 cr |= SDRAM_BXCR_SDSZ_512;
1148                                 break;
1149                         default:
1150                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1151                                        dimm_num);
1152                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1153                                        bank_size_id);
1154                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1155                                 spd_ddr_init_hang ();
1156                         }
1157
1158                         switch (num_col_addr) {
1159                         case 0x08:
1160                                 cr |= SDRAM_BXCR_SDAM_1;
1161                                 break;
1162                         case 0x09:
1163                                 cr |= SDRAM_BXCR_SDAM_2;
1164                                 break;
1165                         case 0x0A:
1166                                 cr |= SDRAM_BXCR_SDAM_3;
1167                                 break;
1168                         case 0x0B:
1169                                 cr |= SDRAM_BXCR_SDAM_4;
1170                                 break;
1171                         default:
1172                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1173                                        dimm_num);
1174                                 printf("ERROR: Unsupported value for number of "
1175                                        "column addresses: %d.\n", num_col_addr);
1176                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1177                                 spd_ddr_init_hang ();
1178                         }
1179
1180                         /*
1181                          * enable the bank
1182                          */
1183                         cr |= SDRAM_BXCR_SDBE;
1184
1185                         for (i = 0; i < num_banks; i++) {
1186                                 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1187                                         (4 << 20) * bank_size_id;
1188                                 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1189                                 debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
1190                                         "bank_size_bytes=%ld\n",
1191                                         dimm_num, i,
1192                                         ctrl_bank_num[dimm_num] + i,
1193                                         bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
1194                         }
1195                 }
1196         }
1197
1198         /* Initialize sort tables */
1199         for (i = 0; i < MAXBXCR; i++) {
1200                 sorted_bank_num[i] = i;
1201                 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1202         }
1203
1204         for (i = 0; i < MAXBXCR-1; i++) {
1205                 largest_size = sorted_bank_size[i];
1206                 largest_size_index = 255;
1207
1208                 /* Find the largest remaining value */
1209                 for (j = i + 1; j < MAXBXCR; j++) {
1210                         if (sorted_bank_size[j] > largest_size) {
1211                                 /* Save largest remaining value and its index */
1212                                 largest_size = sorted_bank_size[j];
1213                                 largest_size_index = j;
1214                         }
1215                 }
1216
1217                 if (largest_size_index != 255) {
1218                         /* Swap the current and largest values */
1219                         current_size_index = sorted_bank_num[largest_size_index];
1220                         sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1221                         sorted_bank_size[i] = largest_size;
1222                         sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1223                         sorted_bank_num[i] = current_size_index;
1224                 }
1225         }
1226
1227         /* Set the SDRAM0_BxCR regs thanks to sort tables */
1228         for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1229                 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1230                         mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
1231                         temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1232                                                   SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1233                         temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1234                                 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1235                         mtdcr(SDRAM0_CFGDATA, temp);
1236                         bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1237                         debug("SDRAM0_B%ldCR=0x%08lx\n",
1238                                 sorted_bank_num[bx_cr_num], temp);
1239                 }
1240         }
1241
1242         return(bank_base_addr);
1243 }
1244 #endif /* CONFIG_SPD_EEPROM */