arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2009
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  54
  55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  56         do {                                                            \
  57                 u32 data;                                               \
  58                 mfsdram(SDRAM_##mnemonic, data);                        \
  59                 printf("%20s[%02x] = 0x%08X\n",                         \
  60                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  61         } while (0)
  62
  63 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  64         do {                                                            \
  65                 u32 data;                                               \
  66                 data = mfdcr(SDRAM_##mnemonic);                         \
  67                 printf("%20s[%02x] = 0x%08X\n",                         \
  68                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  69         } while (0)
  70
  71 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  72 static void update_rdcc(void)
  73 {
  74         u32 val;
  75
  76         /*
  77          * Complete RDSS configuration as mentioned on page 7 of the AMCC
  78          * PowerPC440SP/SPe DDR2 application note:
  79          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  80          *
  81          * Or item #10 "10. Complete RDSS configuration" in chapter
  82          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  83          * manual.
  84          */
  85         mfsdram(SDRAM_RTSR, val);
  86         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  87                 mfsdram(SDRAM_RDCC, val);
  88                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  89                         val += 0x40000000;
  90                         mtsdram(SDRAM_RDCC, val);
  91                 }
  92         }
  93 }
  94 #endif
  95
  96 #if defined(CONFIG_440)
  97 /*
  98  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  99  * memory region. Right now the cache should still be disabled in U-Boot
 100  * because of the EMAC driver, that need its buffer descriptor to be located
 101  * in non cached memory.
 102  *
 103  * If at some time this restriction doesn't apply anymore, just define
 104  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 105  * everything correctly.
 106  */
 107 #ifdef CONFIG_4xx_DCACHE
 108 /* enable caching on SDRAM */
 109 #define MY_TLB_WORD2_I_ENABLE           0
 110 #else
 111 /* disable caching on SDRAM */
 112 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
 113 #endif /* CONFIG_4xx_DCACHE */
 114
 115 void dcbz_area(u32 start_address, u32 num_bytes);
 116 #endif /* CONFIG_440 */
 117
 118 #define MAXRANKS        4
 119 #define MAXBXCF         4
 120
 121 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 122
 123 #if !defined(CONFIG_NAND_SPL)
 124 /*-----------------------------------------------------------------------------+
 125  * sdram_memsize
 126  *-----------------------------------------------------------------------------*/
 127 phys_size_t sdram_memsize(void)
 128 {
 129         phys_size_t mem_size;
 130         unsigned long mcopt2;
 131         unsigned long mcstat;
 132         unsigned long mb0cf;
 133         unsigned long sdsz;
 134         unsigned long i;
 135
 136         mem_size = 0;
 137
 138         mfsdram(SDRAM_MCOPT2, mcopt2);
 139         mfsdram(SDRAM_MCSTAT, mcstat);
 140
 141         /* DDR controller must be enabled and not in self-refresh. */
 142         /* Otherwise memsize is zero. */
 143         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 144             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 145             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 146                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 147                 for (i = 0; i < MAXBXCF; i++) {
 148                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 149                         /* Banks enabled */
 150                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 151 #if defined(CONFIG_440)
 152                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 153 #else
 154                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 155 #endif
 156                                 switch(sdsz) {
 157                                 case SDRAM_RXBAS_SDSZ_8:
 158                                         mem_size+=8;
 159                                         break;
 160                                 case SDRAM_RXBAS_SDSZ_16:
 161                                         mem_size+=16;
 162                                         break;
 163                                 case SDRAM_RXBAS_SDSZ_32:
 164                                         mem_size+=32;
 165                                         break;
 166                                 case SDRAM_RXBAS_SDSZ_64:
 167                                         mem_size+=64;
 168                                         break;
 169                                 case SDRAM_RXBAS_SDSZ_128:
 170                                         mem_size+=128;
 171                                         break;
 172                                 case SDRAM_RXBAS_SDSZ_256:
 173                                         mem_size+=256;
 174                                         break;
 175                                 case SDRAM_RXBAS_SDSZ_512:
 176                                         mem_size+=512;
 177                                         break;
 178                                 case SDRAM_RXBAS_SDSZ_1024:
 179                                         mem_size+=1024;
 180                                         break;
 181                                 case SDRAM_RXBAS_SDSZ_2048:
 182                                         mem_size+=2048;
 183                                         break;
 184                                 case SDRAM_RXBAS_SDSZ_4096:
 185                                         mem_size+=4096;
 186                                         break;
 187                                 default:
 188                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 189                                                , sdsz);
 190                                         mem_size=0;
 191                                         break;
 192                                 }
 193                         }
 194                 }
 195         }
 196
 197         return mem_size << 20;
 198 }
 199
 200 /*-----------------------------------------------------------------------------+
 201  * is_ecc_enabled
 202  *-----------------------------------------------------------------------------*/
 203 static unsigned long is_ecc_enabled(void)
 204 {
 205         unsigned long val;
 206
 207         mfsdram(SDRAM_MCOPT1, val);
 208
 209         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
 210 }
 211
 212 /*-----------------------------------------------------------------------------+
 213  * board_add_ram_info
 214  *-----------------------------------------------------------------------------*/
 215 void board_add_ram_info(int use_default)
 216 {
 217         PPC4xx_SYS_INFO board_cfg;
 218         u32 val;
 219
 220         if (is_ecc_enabled())
 221                 puts(" (ECC");
 222         else
 223                 puts(" (ECC not");
 224
 225         get_sys_info(&board_cfg);
 226
 227 #if defined(CONFIG_405EX)
 228         val = board_cfg.freqPLB;
 229 #else
 230         mfsdr(SDR0_DDR0, val);
 231         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 232 #endif
 233         printf(" enabled, %d MHz", (val * 2) / 1000000);
 234
 235         mfsdram(SDRAM_MMODE, val);
 236         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 237         printf(", CL%d)", val);
 238 }
 239 #endif /* !CONFIG_NAND_SPL */
 240
 241 #if defined(CONFIG_SPD_EEPROM)
 242
 243 /*-----------------------------------------------------------------------------+
 244  * Defines
 245  *-----------------------------------------------------------------------------*/
 246 #ifndef TRUE
 247 #define TRUE            1
 248 #endif
 249 #ifndef FALSE
 250 #define FALSE           0
 251 #endif
 252
 253 #define SDRAM_DDR1      1
 254 #define SDRAM_DDR2      2
 255 #define SDRAM_NONE      0
 256
 257 #define MAXDIMMS        2
 258 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 259
 260 #define ONE_BILLION     1000000000
 261
 262 #define CMD_NOP         (7 << 19)
 263 #define CMD_PRECHARGE   (2 << 19)
 264 #define CMD_REFRESH     (1 << 19)
 265 #define CMD_EMR         (0 << 19)
 266 #define CMD_READ        (5 << 19)
 267 #define CMD_WRITE       (4 << 19)
 268
 269 #define SELECT_MR       (0 << 16)
 270 #define SELECT_EMR      (1 << 16)
 271 #define SELECT_EMR2     (2 << 16)
 272 #define SELECT_EMR3     (3 << 16)
 273
 274 /* MR */
 275 #define DLL_RESET       0x00000100
 276
 277 #define WRITE_RECOV_2   (1 << 9)
 278 #define WRITE_RECOV_3   (2 << 9)
 279 #define WRITE_RECOV_4   (3 << 9)
 280 #define WRITE_RECOV_5   (4 << 9)
 281 #define WRITE_RECOV_6   (5 << 9)
 282
 283 #define BURST_LEN_4     0x00000002
 284
 285 /* EMR */
 286 #define ODT_0_OHM       0x00000000
 287 #define ODT_50_OHM      0x00000044
 288 #define ODT_75_OHM      0x00000004
 289 #define ODT_150_OHM     0x00000040
 290
 291 #define ODS_FULL        0x00000000
 292 #define ODS_REDUCED     0x00000002
 293 #define OCD_CALIB_DEF   0x00000380
 294
 295 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 296 #define ODT_EB0R        (0x80000000 >> 8)
 297 #define ODT_EB0W        (0x80000000 >> 7)
 298 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 299 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 300 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 301
 302 /* Defines for the Read Cycle Delay test */
 303 #define NUMMEMTESTS     8
 304 #define NUMMEMWORDS     8
 305 #define NUMLOOPS        64              /* memory test loops */
 306
 307 /*
 308  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 309  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 310  * need some free virtual address space for the remaining peripherals like, SoC
 311  * devices, FLASH etc.
 312  *
 313  * Note that ECC is currently not supported on configurations with more than 2GB
 314  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 315  * the ECC parity byte of the remaining area can't be written.
 316  */
 317
 318 /*
 319  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 320  */
 321 void __spd_ddr_init_hang (void)
 322 {
 323         hang ();
 324 }
 325 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 326
 327 /*
 328  * To provide an interface for board specific config values in this common
 329  * DDR setup code, we implement he "weak" default functions here. They return
 330  * the default value back to the caller.
 331  *
 332  * Please see include/configs/yucca.h for an example fora board specific
 333  * implementation.
 334  */
 335 u32 __ddr_wrdtr(u32 default_val)
 336 {
 337         return default_val;
 338 }
 339 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 340
 341 u32 __ddr_clktr(u32 default_val)
 342 {
 343         return default_val;
 344 }
 345 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 346
 347
 348 /* Private Structure Definitions */
 349
 350 /* enum only to ease code for cas latency setting */
 351 typedef enum ddr_cas_id {
 352         DDR_CAS_2      = 20,
 353         DDR_CAS_2_5    = 25,
 354         DDR_CAS_3      = 30,
 355         DDR_CAS_4      = 40,
 356         DDR_CAS_5      = 50
 357 } ddr_cas_id_t;
 358
 359 /*-----------------------------------------------------------------------------+
 360  * Prototypes
 361  *-----------------------------------------------------------------------------*/
 362 static void get_spd_info(unsigned long *dimm_populated,
 363                          unsigned char *iic0_dimm_addr,
 364                          unsigned long num_dimm_banks);
 365 static void check_mem_type(unsigned long *dimm_populated,
 366                            unsigned char *iic0_dimm_addr,
 367                            unsigned long num_dimm_banks);
 368 static void check_frequency(unsigned long *dimm_populated,
 369                             unsigned char *iic0_dimm_addr,
 370                             unsigned long num_dimm_banks);
 371 static void check_rank_number(unsigned long *dimm_populated,
 372                               unsigned char *iic0_dimm_addr,
 373                               unsigned long num_dimm_banks);
 374 static void check_voltage_type(unsigned long *dimm_populated,
 375                                unsigned char *iic0_dimm_addr,
 376                                unsigned long num_dimm_banks);
 377 static void program_memory_queue(unsigned long *dimm_populated,
 378                                  unsigned char *iic0_dimm_addr,
 379                                  unsigned long num_dimm_banks);
 380 static void program_codt(unsigned long *dimm_populated,
 381                          unsigned char *iic0_dimm_addr,
 382                          unsigned long num_dimm_banks);
 383 static void program_mode(unsigned long *dimm_populated,
 384                          unsigned char *iic0_dimm_addr,
 385                          unsigned long num_dimm_banks,
 386                          ddr_cas_id_t *selected_cas,
 387                          int *write_recovery);
 388 static void program_tr(unsigned long *dimm_populated,
 389                        unsigned char *iic0_dimm_addr,
 390                        unsigned long num_dimm_banks);
 391 static void program_rtr(unsigned long *dimm_populated,
 392                         unsigned char *iic0_dimm_addr,
 393                         unsigned long num_dimm_banks);
 394 static void program_bxcf(unsigned long *dimm_populated,
 395                          unsigned char *iic0_dimm_addr,
 396                          unsigned long num_dimm_banks);
 397 static void program_copt1(unsigned long *dimm_populated,
 398                           unsigned char *iic0_dimm_addr,
 399                           unsigned long num_dimm_banks);
 400 static void program_initplr(unsigned long *dimm_populated,
 401                             unsigned char *iic0_dimm_addr,
 402                             unsigned long num_dimm_banks,
 403                             ddr_cas_id_t selected_cas,
 404                             int write_recovery);
 405 #ifdef CONFIG_DDR_ECC
 406 static void program_ecc(unsigned long *dimm_populated,
 407                         unsigned char *iic0_dimm_addr,
 408                         unsigned long num_dimm_banks,
 409                         unsigned long tlb_word2_i_value);
 410 #endif
 411 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 412 static void program_DQS_calibration(unsigned long *dimm_populated,
 413                                 unsigned char *iic0_dimm_addr,
 414                                 unsigned long num_dimm_banks);
 415 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 416 static void     test(void);
 417 #else
 418 static void     DQS_calibration_process(void);
 419 #endif
 420 #endif
 421 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 422
 423 static unsigned char spd_read(uchar chip, uint addr)
 424 {
 425         unsigned char data[2];
 426
 427         if (i2c_probe(chip) == 0)
 428                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 429                         return data[0];
 430
 431         return 0;
 432 }
 433
 434 /*-----------------------------------------------------------------------------+
 435  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 436  * Note: This routine runs from flash with a stack set up in the chip's
 437  * sram space.  It is important that the routine does not require .sbss, .bss or
 438  * .data sections.  It also cannot call routines that require these sections.
 439  *-----------------------------------------------------------------------------*/
 440 /*-----------------------------------------------------------------------------
 441  * Function:     initdram
 442  * Description:  Configures SDRAM memory banks for DDR operation.
 443  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 444  *               via the IIC bus and then configures the DDR SDRAM memory
 445  *               banks appropriately. If Auto Memory Configuration is
 446  *               not used, it is assumed that no DIMM is plugged
 447  *-----------------------------------------------------------------------------*/
 448 phys_size_t initdram(int board_type)
 449 {
 450         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 451         unsigned char spd0[MAX_SPD_BYTES];
 452         unsigned char spd1[MAX_SPD_BYTES];
 453         unsigned char *dimm_spd[MAXDIMMS];
 454         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 455         unsigned long num_dimm_banks;           /* on board dimm banks */
 456         unsigned long val;
 457         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 458         int write_recovery;
 459         phys_size_t dram_size = 0;
 460
 461         num_dimm_banks = sizeof(iic0_dimm_addr);
 462
 463         /*------------------------------------------------------------------
 464          * Set up an array of SPD matrixes.
 465          *-----------------------------------------------------------------*/
 466         dimm_spd[0] = spd0;
 467         dimm_spd[1] = spd1;
 468
 469         /*------------------------------------------------------------------
 470          * Reset the DDR-SDRAM controller.
 471          *-----------------------------------------------------------------*/
 472         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 473         mtsdr(SDR0_SRST, 0x00000000);
 474
 475         /*
 476          * Make sure I2C controller is initialized
 477          * before continuing.
 478          */
 479
 480         /* switch to correct I2C bus */
 481         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 482         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 483
 484         /*------------------------------------------------------------------
 485          * Clear out the serial presence detect buffers.
 486          * Perform IIC reads from the dimm.  Fill in the spds.
 487          * Check to see if the dimm slots are populated
 488          *-----------------------------------------------------------------*/
 489         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 490
 491         /*------------------------------------------------------------------
 492          * Check the memory type for the dimms plugged.
 493          *-----------------------------------------------------------------*/
 494         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 495
 496         /*------------------------------------------------------------------
 497          * Check the frequency supported for the dimms plugged.
 498          *-----------------------------------------------------------------*/
 499         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 500
 501         /*------------------------------------------------------------------
 502          * Check the total rank number.
 503          *-----------------------------------------------------------------*/
 504         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 505
 506         /*------------------------------------------------------------------
 507          * Check the voltage type for the dimms plugged.
 508          *-----------------------------------------------------------------*/
 509         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 510
 511         /*------------------------------------------------------------------
 512          * Program SDRAM controller options 2 register
 513          * Except Enabling of the memory controller.
 514          *-----------------------------------------------------------------*/
 515         mfsdram(SDRAM_MCOPT2, val);
 516         mtsdram(SDRAM_MCOPT2,
 517                 (val &
 518                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 519                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 520                    SDRAM_MCOPT2_ISIE_MASK))
 521                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 522                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 523                    SDRAM_MCOPT2_ISIE_ENABLE));
 524
 525         /*------------------------------------------------------------------
 526          * Program SDRAM controller options 1 register
 527          * Note: Does not enable the memory controller.
 528          *-----------------------------------------------------------------*/
 529         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 530
 531         /*------------------------------------------------------------------
 532          * Set the SDRAM Controller On Die Termination Register
 533          *-----------------------------------------------------------------*/
 534         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 535
 536         /*------------------------------------------------------------------
 537          * Program SDRAM refresh register.
 538          *-----------------------------------------------------------------*/
 539         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 540
 541         /*------------------------------------------------------------------
 542          * Program SDRAM mode register.
 543          *-----------------------------------------------------------------*/
 544         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 545                      &selected_cas, &write_recovery);
 546
 547         /*------------------------------------------------------------------
 548          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 549          *-----------------------------------------------------------------*/
 550         mfsdram(SDRAM_WRDTR, val);
 551         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 552                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 553
 554         /*------------------------------------------------------------------
 555          * Set the SDRAM Clock Timing Register
 556          *-----------------------------------------------------------------*/
 557         mfsdram(SDRAM_CLKTR, val);
 558         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 559                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 560
 561         /*------------------------------------------------------------------
 562          * Program the BxCF registers.
 563          *-----------------------------------------------------------------*/
 564         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 565
 566         /*------------------------------------------------------------------
 567          * Program SDRAM timing registers.
 568          *-----------------------------------------------------------------*/
 569         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 570
 571         /*------------------------------------------------------------------
 572          * Set the Extended Mode register
 573          *-----------------------------------------------------------------*/
 574         mfsdram(SDRAM_MEMODE, val);
 575         mtsdram(SDRAM_MEMODE,
 576                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 577                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 578                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 579                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 580
 581         /*------------------------------------------------------------------
 582          * Program Initialization preload registers.
 583          *-----------------------------------------------------------------*/
 584         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 585                         selected_cas, write_recovery);
 586
 587         /*------------------------------------------------------------------
 588          * Delay to ensure 200usec have elapsed since reset.
 589          *-----------------------------------------------------------------*/
 590         udelay(400);
 591
 592         /*------------------------------------------------------------------
 593          * Set the memory queue core base addr.
 594          *-----------------------------------------------------------------*/
 595         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 596
 597         /*------------------------------------------------------------------
 598          * Program SDRAM controller options 2 register
 599          * Enable the memory controller.
 600          *-----------------------------------------------------------------*/
 601         mfsdram(SDRAM_MCOPT2, val);
 602         mtsdram(SDRAM_MCOPT2,
 603                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 604                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 605                          SDRAM_MCOPT2_IPTR_EXECUTE);
 606
 607         /*------------------------------------------------------------------
 608          * Wait for IPTR_EXECUTE init sequence to complete.
 609          *-----------------------------------------------------------------*/
 610         do {
 611                 mfsdram(SDRAM_MCSTAT, val);
 612         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 613
 614         /* enable the controller only after init sequence completes */
 615         mfsdram(SDRAM_MCOPT2, val);
 616         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 617
 618         /* Make sure delay-line calibration is done before proceeding */
 619         do {
 620                 mfsdram(SDRAM_DLCR, val);
 621         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 622
 623         /* get installed memory size */
 624         dram_size = sdram_memsize();
 625
 626         /*
 627          * Limit size to 2GB
 628          */
 629         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 630                 dram_size = CONFIG_MAX_MEM_MAPPED;
 631
 632         /* and program tlb entries for this size (dynamic) */
 633
 634         /*
 635          * Program TLB entries with caches enabled, for best performace
 636          * while auto-calibrating and ECC generation
 637          */
 638         program_tlb(0, 0, dram_size, 0);
 639
 640         /*------------------------------------------------------------------
 641          * DQS calibration.
 642          *-----------------------------------------------------------------*/
 643 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 644         DQS_autocalibration();
 645 #else
 646         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 647 #endif
 648         /*
 649          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
 650          * PowerPC440SP/SPe DDR2 application note:
 651          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
 652          */
 653         update_rdcc();
 654
 655 #ifdef CONFIG_DDR_ECC
 656         /*------------------------------------------------------------------
 657          * If ecc is enabled, initialize the parity bits.
 658          *-----------------------------------------------------------------*/
 659         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 660 #endif
 661
 662         /*
 663          * Now after initialization (auto-calibration and ECC generation)
 664          * remove the TLB entries with caches enabled and program again with
 665          * desired cache functionality
 666          */
 667         remove_tlb(0, dram_size);
 668         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 669
 670         ppc4xx_ibm_ddr2_register_dump();
 671
 672         /*
 673          * Clear potential errors resulting from auto-calibration.
 674          * If not done, then we could get an interrupt later on when
 675          * exceptions are enabled.
 676          */
 677         set_mcsr(get_mcsr());
 678
 679         return sdram_memsize();
 680 }
 681
 682 static void get_spd_info(unsigned long *dimm_populated,
 683                          unsigned char *iic0_dimm_addr,
 684                          unsigned long num_dimm_banks)
 685 {
 686         unsigned long dimm_num;
 687         unsigned long dimm_found;
 688         unsigned char num_of_bytes;
 689         unsigned char total_size;
 690
 691         dimm_found = FALSE;
 692         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 693                 num_of_bytes = 0;
 694                 total_size = 0;
 695
 696                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 697                 debug("\nspd_read(0x%x) returned %d\n",
 698                       iic0_dimm_addr[dimm_num], num_of_bytes);
 699                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 700                 debug("spd_read(0x%x) returned %d\n",
 701                       iic0_dimm_addr[dimm_num], total_size);
 702
 703                 if ((num_of_bytes != 0) && (total_size != 0)) {
 704                         dimm_populated[dimm_num] = TRUE;
 705                         dimm_found = TRUE;
 706                         debug("DIMM slot %lu: populated\n", dimm_num);
 707                 } else {
 708                         dimm_populated[dimm_num] = FALSE;
 709                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 710                 }
 711         }
 712
 713         if (dimm_found == FALSE) {
 714                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 715                 spd_ddr_init_hang ();
 716         }
 717 }
 718
 719
 720 /*------------------------------------------------------------------
 721  * For the memory DIMMs installed, this routine verifies that they
 722  * really are DDR specific DIMMs.
 723  *-----------------------------------------------------------------*/
 724 static void check_mem_type(unsigned long *dimm_populated,
 725                            unsigned char *iic0_dimm_addr,
 726                            unsigned long num_dimm_banks)
 727 {
 728         unsigned long dimm_num;
 729         unsigned long dimm_type;
 730
 731         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 732                 if (dimm_populated[dimm_num] == TRUE) {
 733                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 734                         switch (dimm_type) {
 735                         case 1:
 736                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 737                                        "slot %d.\n", (unsigned int)dimm_num);
 738                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 739                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 740                                 spd_ddr_init_hang ();
 741                                 break;
 742                         case 2:
 743                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 744                                        (unsigned int)dimm_num);
 745                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 746                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 747                                 spd_ddr_init_hang ();
 748                                 break;
 749                         case 3:
 750                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 751                                        (unsigned int)dimm_num);
 752                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 753                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 754                                 spd_ddr_init_hang ();
 755                                 break;
 756                         case 4:
 757                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 758                                        (unsigned int)dimm_num);
 759                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 760                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 761                                 spd_ddr_init_hang ();
 762                                 break;
 763                         case 5:
 764                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 765                                        (unsigned int)dimm_num);
 766                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 767                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 768                                 spd_ddr_init_hang ();
 769                                 break;
 770                         case 6:
 771                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 772                                        (unsigned int)dimm_num);
 773                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 774                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 775                                 spd_ddr_init_hang ();
 776                                 break;
 777                         case 7:
 778                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 779                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 780                                 break;
 781                         case 8:
 782                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 783                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 784                                 break;
 785                         default:
 786                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 787                                        (unsigned int)dimm_num);
 788                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 789                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 790                                 spd_ddr_init_hang ();
 791                                 break;
 792                         }
 793                 }
 794         }
 795         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 796                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 797                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 798                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 799                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 800                         spd_ddr_init_hang ();
 801                 }
 802         }
 803 }
 804
 805 /*------------------------------------------------------------------
 806  * For the memory DIMMs installed, this routine verifies that
 807  * frequency previously calculated is supported.
 808  *-----------------------------------------------------------------*/
 809 static void check_frequency(unsigned long *dimm_populated,
 810                             unsigned char *iic0_dimm_addr,
 811                             unsigned long num_dimm_banks)
 812 {
 813         unsigned long dimm_num;
 814         unsigned long tcyc_reg;
 815         unsigned long cycle_time;
 816         unsigned long calc_cycle_time;
 817         unsigned long sdram_freq;
 818         unsigned long sdr_ddrpll;
 819         PPC4xx_SYS_INFO board_cfg;
 820
 821         /*------------------------------------------------------------------
 822          * Get the board configuration info.
 823          *-----------------------------------------------------------------*/
 824         get_sys_info(&board_cfg);
 825
 826         mfsdr(SDR0_DDR0, sdr_ddrpll);
 827         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 828
 829         /*
 830          * calc_cycle_time is calculated from DDR frequency set by board/chip
 831          * and is expressed in multiple of 10 picoseconds
 832          * to match the way DIMM cycle time is calculated below.
 833          */
 834         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 835
 836         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 837                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 838                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 839                         /*
 840                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 841                          * the higher order nibble (bits 4-7) designates the cycle time
 842                          * to a granularity of 1ns;
 843                          * the value presented by the lower order nibble (bits 0-3)
 844                          * has a granularity of .1ns and is added to the value designated
 845                          * by the higher nibble. In addition, four lines of the lower order
 846                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 847                          */
 848                          /* Convert from hex to decimal */
 849                         if ((tcyc_reg & 0x0F) == 0x0D)
 850                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 851                         else if ((tcyc_reg & 0x0F) == 0x0C)
 852                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 853                         else if ((tcyc_reg & 0x0F) == 0x0B)
 854                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 855                         else if ((tcyc_reg & 0x0F) == 0x0A)
 856                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 857                         else
 858                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 859                                         ((tcyc_reg & 0x0F)*10);
 860                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 861
 862                         if  (cycle_time > (calc_cycle_time + 10)) {
 863                                 /*
 864                                  * the provided sdram cycle_time is too small
 865                                  * for the available DIMM cycle_time.
 866                                  * The additionnal 100ps is here to accept a small incertainty.
 867                                  */
 868                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 869                                        "slot %d \n while calculated cycle time is %d ps.\n",
 870                                        (unsigned int)(cycle_time*10),
 871                                        (unsigned int)dimm_num,
 872                                        (unsigned int)(calc_cycle_time*10));
 873                                 printf("Replace the DIMM, or change DDR frequency via "
 874                                        "strapping bits.\n\n");
 875                                 spd_ddr_init_hang ();
 876                         }
 877                 }
 878         }
 879 }
 880
 881 /*------------------------------------------------------------------
 882  * For the memory DIMMs installed, this routine verifies two
 883  * ranks/banks maximum are availables.
 884  *-----------------------------------------------------------------*/
 885 static void check_rank_number(unsigned long *dimm_populated,
 886                               unsigned char *iic0_dimm_addr,
 887                               unsigned long num_dimm_banks)
 888 {
 889         unsigned long dimm_num;
 890         unsigned long dimm_rank;
 891         unsigned long total_rank = 0;
 892
 893         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 894                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 895                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 896                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 897                                 dimm_rank = (dimm_rank & 0x0F) +1;
 898                         else
 899                                 dimm_rank = dimm_rank & 0x0F;
 900
 901
 902                         if (dimm_rank > MAXRANKS) {
 903                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 904                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 905                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 906                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 907                                 spd_ddr_init_hang ();
 908                         } else
 909                                 total_rank += dimm_rank;
 910                 }
 911                 if (total_rank > MAXRANKS) {
 912                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 913                                "for all slots.\n", (unsigned int)total_rank);
 914                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 915                         printf("Remove one of the DIMM modules.\n\n");
 916                         spd_ddr_init_hang ();
 917                 }
 918         }
 919 }
 920
 921 /*------------------------------------------------------------------
 922  * only support 2.5V modules.
 923  * This routine verifies this.
 924  *-----------------------------------------------------------------*/
 925 static void check_voltage_type(unsigned long *dimm_populated,
 926                                unsigned char *iic0_dimm_addr,
 927                                unsigned long num_dimm_banks)
 928 {
 929         unsigned long dimm_num;
 930         unsigned long voltage_type;
 931
 932         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 933                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 934                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 935                         switch (voltage_type) {
 936                         case 0x00:
 937                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 938                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 939                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 940                                        (unsigned int)dimm_num);
 941                                 spd_ddr_init_hang ();
 942                                 break;
 943                         case 0x01:
 944                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 945                                 printf("This DIMM is LVTTL.\n");
 946                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 947                                        (unsigned int)dimm_num);
 948                                 spd_ddr_init_hang ();
 949                                 break;
 950                         case 0x02:
 951                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 952                                 printf("This DIMM is 1.5 Volt.\n");
 953                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 954                                        (unsigned int)dimm_num);
 955                                 spd_ddr_init_hang ();
 956                                 break;
 957                         case 0x03:
 958                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 959                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 960                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 961                                        (unsigned int)dimm_num);
 962                                 spd_ddr_init_hang ();
 963                                 break;
 964                         case 0x04:
 965                                 /* 2.5 Voltage only for DDR1 */
 966                                 break;
 967                         case 0x05:
 968                                 /* 1.8 Voltage only for DDR2 */
 969                                 break;
 970                         default:
 971                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 972                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 973                                        (unsigned int)dimm_num);
 974                                 spd_ddr_init_hang ();
 975                                 break;
 976                         }
 977                 }
 978         }
 979 }
 980
 981 /*-----------------------------------------------------------------------------+
 982  * program_copt1.
 983  *-----------------------------------------------------------------------------*/
 984 static void program_copt1(unsigned long *dimm_populated,
 985                           unsigned char *iic0_dimm_addr,
 986                           unsigned long num_dimm_banks)
 987 {
 988         unsigned long dimm_num;
 989         unsigned long mcopt1;
 990         unsigned long ecc_enabled;
 991         unsigned long ecc = 0;
 992         unsigned long data_width = 0;
 993         unsigned long dimm_32bit;
 994         unsigned long dimm_64bit;
 995         unsigned long registered = 0;
 996         unsigned long attribute = 0;
 997         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 998         unsigned long bankcount;
 999         unsigned long ddrtype;
1000         unsigned long val;
1001
1002 #ifdef CONFIG_DDR_ECC
1003         ecc_enabled = TRUE;
1004 #else
1005         ecc_enabled = FALSE;
1006 #endif
1007         dimm_32bit = FALSE;
1008         dimm_64bit = FALSE;
1009         buf0 = FALSE;
1010         buf1 = FALSE;
1011
1012         /*------------------------------------------------------------------
1013          * Set memory controller options reg 1, SDRAM_MCOPT1.
1014          *-----------------------------------------------------------------*/
1015         mfsdram(SDRAM_MCOPT1, val);
1016         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1017                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
1018                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1019                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1020                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1021                          SDRAM_MCOPT1_DREF_MASK);
1022
1023         mcopt1 |= SDRAM_MCOPT1_QDEP;
1024         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1025         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1026         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1027         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1028         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1029
1030         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1031                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1032                         /* test ecc support */
1033                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1034                         if (ecc != 0x02) /* ecc not supported */
1035                                 ecc_enabled = FALSE;
1036
1037                         /* test bank count */
1038                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1039                         if (bankcount == 0x04) /* bank count = 4 */
1040                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1041                         else /* bank count = 8 */
1042                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1043
1044                         /* test DDR type */
1045                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1046                         /* test for buffered/unbuffered, registered, differential clocks */
1047                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1048                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1049
1050                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1051                         if (dimm_num == 0) {
1052                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1053                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1054                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1055                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1056                                 if (registered == 1) { /* DDR2 always buffered */
1057                                         /* TODO: what about above  comments ? */
1058                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1059                                         buf0 = TRUE;
1060                                 } else {
1061                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1062                                         if ((attribute & 0x02) == 0x00) {
1063                                                 /* buffered not supported */
1064                                                 buf0 = FALSE;
1065                                         } else {
1066                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1067                                                 buf0 = TRUE;
1068                                         }
1069                                 }
1070                         }
1071                         else if (dimm_num == 1) {
1072                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1073                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1074                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1075                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1076                                 if (registered == 1) {
1077                                         /* DDR2 always buffered */
1078                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1079                                         buf1 = TRUE;
1080                                 } else {
1081                                         if ((attribute & 0x02) == 0x00) {
1082                                                 /* buffered not supported */
1083                                                 buf1 = FALSE;
1084                                         } else {
1085                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1086                                                 buf1 = TRUE;
1087                                         }
1088                                 }
1089                         }
1090
1091                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1092                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1093                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1094
1095                         switch (data_width) {
1096                         case 72:
1097                         case 64:
1098                                 dimm_64bit = TRUE;
1099                                 break;
1100                         case 40:
1101                         case 32:
1102                                 dimm_32bit = TRUE;
1103                                 break;
1104                         default:
1105                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1106                                        data_width);
1107                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1108                                 break;
1109                         }
1110                 }
1111         }
1112
1113         /* verify matching properties */
1114         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1115                 if (buf0 != buf1) {
1116                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1117                         spd_ddr_init_hang ();
1118                 }
1119         }
1120
1121         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1122                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1123                 spd_ddr_init_hang ();
1124         }
1125         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1126                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1127         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1128                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1129         } else {
1130                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1131                 spd_ddr_init_hang ();
1132         }
1133
1134         if (ecc_enabled == TRUE)
1135                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1136         else
1137                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1138
1139         mtsdram(SDRAM_MCOPT1, mcopt1);
1140 }
1141
1142 /*-----------------------------------------------------------------------------+
1143  * program_codt.
1144  *-----------------------------------------------------------------------------*/
1145 static void program_codt(unsigned long *dimm_populated,
1146                          unsigned char *iic0_dimm_addr,
1147                          unsigned long num_dimm_banks)
1148 {
1149         unsigned long codt;
1150         unsigned long modt0 = 0;
1151         unsigned long modt1 = 0;
1152         unsigned long modt2 = 0;
1153         unsigned long modt3 = 0;
1154         unsigned char dimm_num;
1155         unsigned char dimm_rank;
1156         unsigned char total_rank = 0;
1157         unsigned char total_dimm = 0;
1158         unsigned char dimm_type = 0;
1159         unsigned char firstSlot = 0;
1160
1161         /*------------------------------------------------------------------
1162          * Set the SDRAM Controller On Die Termination Register
1163          *-----------------------------------------------------------------*/
1164         mfsdram(SDRAM_CODT, codt);
1165         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1166         codt |= SDRAM_CODT_IO_NMODE;
1167
1168         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1169                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1170                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1171                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1172                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1173                                 dimm_type = SDRAM_DDR2;
1174                         } else {
1175                                 dimm_rank = dimm_rank & 0x0F;
1176                                 dimm_type = SDRAM_DDR1;
1177                         }
1178
1179                         total_rank += dimm_rank;
1180                         total_dimm++;
1181                         if ((dimm_num == 0) && (total_dimm == 1))
1182                                 firstSlot = TRUE;
1183                         else
1184                                 firstSlot = FALSE;
1185                 }
1186         }
1187         if (dimm_type == SDRAM_DDR2) {
1188                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1189                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1190                         if (total_rank == 1) {  /* PUUU */
1191                                 codt |= CALC_ODT_R(0);
1192                                 modt0 = CALC_ODT_W(0);
1193                                 modt1 = 0x00000000;
1194                                 modt2 = 0x00000000;
1195                                 modt3 = 0x00000000;
1196                         }
1197                         if (total_rank == 2) {  /* PPUU */
1198                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1199                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1200                                 modt1 = 0x00000000;
1201                                 modt2 = 0x00000000;
1202                                 modt3 = 0x00000000;
1203                         }
1204                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1205                         if (total_rank == 1) {  /* UUPU */
1206                                 codt |= CALC_ODT_R(2);
1207                                 modt0 = 0x00000000;
1208                                 modt1 = 0x00000000;
1209                                 modt2 = CALC_ODT_W(2);
1210                                 modt3 = 0x00000000;
1211                         }
1212                         if (total_rank == 2) {  /* UUPP */
1213                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1214                                 modt0 = 0x00000000;
1215                                 modt1 = 0x00000000;
1216                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1217                                 modt3 = 0x00000000;
1218                         }
1219                 }
1220                 if (total_dimm == 2) {
1221                         if (total_rank == 2) {  /* PUPU */
1222                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1223                                 modt0 = CALC_ODT_RW(2);
1224                                 modt1 = 0x00000000;
1225                                 modt2 = CALC_ODT_RW(0);
1226                                 modt3 = 0x00000000;
1227                         }
1228                         if (total_rank == 4) {  /* PPPP */
1229                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1230                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1231                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1232                                 modt1 = 0x00000000;
1233                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1234                                 modt3 = 0x00000000;
1235                         }
1236                 }
1237         } else {
1238                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1239                 modt0 = 0x00000000;
1240                 modt1 = 0x00000000;
1241                 modt2 = 0x00000000;
1242                 modt3 = 0x00000000;
1243
1244                 if (total_dimm == 1) {
1245                         if (total_rank == 1)
1246                                 codt |= 0x00800000;
1247                         if (total_rank == 2)
1248                                 codt |= 0x02800000;
1249                 }
1250                 if (total_dimm == 2) {
1251                         if (total_rank == 2)
1252                                 codt |= 0x08800000;
1253                         if (total_rank == 4)
1254                                 codt |= 0x2a800000;
1255                 }
1256         }
1257
1258         debug("nb of dimm %d\n", total_dimm);
1259         debug("nb of rank %d\n", total_rank);
1260         if (total_dimm == 1)
1261                 debug("dimm in slot %d\n", firstSlot);
1262
1263         mtsdram(SDRAM_CODT, codt);
1264         mtsdram(SDRAM_MODT0, modt0);
1265         mtsdram(SDRAM_MODT1, modt1);
1266         mtsdram(SDRAM_MODT2, modt2);
1267         mtsdram(SDRAM_MODT3, modt3);
1268 }
1269
1270 /*-----------------------------------------------------------------------------+
1271  * program_initplr.
1272  *-----------------------------------------------------------------------------*/
1273 static void program_initplr(unsigned long *dimm_populated,
1274                             unsigned char *iic0_dimm_addr,
1275                             unsigned long num_dimm_banks,
1276                             ddr_cas_id_t selected_cas,
1277                             int write_recovery)
1278 {
1279         u32 cas = 0;
1280         u32 odt = 0;
1281         u32 ods = 0;
1282         u32 mr;
1283         u32 wr;
1284         u32 emr;
1285         u32 emr2;
1286         u32 emr3;
1287         int dimm_num;
1288         int total_dimm = 0;
1289
1290         /******************************************************
1291          ** Assumption: if more than one DIMM, all DIMMs are the same
1292          **             as already checked in check_memory_type
1293          ******************************************************/
1294
1295         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1296                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1297                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1298                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1299                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1300                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1301                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1302                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1303                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1304         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1305                 switch (selected_cas) {
1306                 case DDR_CAS_3:
1307                         cas = 3 << 4;
1308                         break;
1309                 case DDR_CAS_4:
1310                         cas = 4 << 4;
1311                         break;
1312                 case DDR_CAS_5:
1313                         cas = 5 << 4;
1314                         break;
1315                 default:
1316                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1317                         spd_ddr_init_hang ();
1318                         break;
1319                 }
1320
1321 #if 0
1322                 /*
1323                  * ToDo - Still a problem with the write recovery:
1324                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1325                  * in the INITPLR reg to the value calculated in program_mode()
1326                  * results in not correctly working DDR2 memory (crash after
1327                  * relocation).
1328                  *
1329                  * So for now, set the write recovery to 3. This seems to work
1330                  * on the Corair module too.
1331                  *
1332                  * 2007-03-01, sr
1333                  */
1334                 switch (write_recovery) {
1335                 case 3:
1336                         wr = WRITE_RECOV_3;
1337                         break;
1338                 case 4:
1339                         wr = WRITE_RECOV_4;
1340                         break;
1341                 case 5:
1342                         wr = WRITE_RECOV_5;
1343                         break;
1344                 case 6:
1345                         wr = WRITE_RECOV_6;
1346                         break;
1347                 default:
1348                         printf("ERROR: write recovery not support (%d)", write_recovery);
1349                         spd_ddr_init_hang ();
1350                         break;
1351                 }
1352 #else
1353                 wr = WRITE_RECOV_3; /* test-only, see description above */
1354 #endif
1355
1356                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1357                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1358                                 total_dimm++;
1359                 if (total_dimm == 1) {
1360                         odt = ODT_150_OHM;
1361                         ods = ODS_FULL;
1362                 } else if (total_dimm == 2) {
1363                         odt = ODT_75_OHM;
1364                         ods = ODS_REDUCED;
1365                 } else {
1366                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1367                         spd_ddr_init_hang ();
1368                 }
1369
1370                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1371                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1372                 emr2 = CMD_EMR | SELECT_EMR2;
1373                 emr3 = CMD_EMR | SELECT_EMR3;
1374                 /* NOP - Wait 106 MemClk cycles */
1375                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1376                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1377                 udelay(1000);
1378                 /* precharge 4 MemClk cycles */
1379                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1380                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1381                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1382                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1383                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1384                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1385                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1386                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1387                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1388                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1389                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1390                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1391                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1392                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1393                 udelay(1000);
1394                 /* precharge 4 MemClk cycles */
1395                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1396                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1397                 /* Refresh 25 MemClk cycles */
1398                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1399                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1400                 /* Refresh 25 MemClk cycles */
1401                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1402                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1403                 /* Refresh 25 MemClk cycles */
1404                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1405                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1406                 /* Refresh 25 MemClk cycles */
1407                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1408                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1409                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1410                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1411                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1412                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1413                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1414                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1415                 /* EMR OCD Exit */
1416                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1417                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1418         } else {
1419                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1420                 spd_ddr_init_hang ();
1421         }
1422 }
1423
1424 /*------------------------------------------------------------------
1425  * This routine programs the SDRAM_MMODE register.
1426  * the selected_cas is an output parameter, that will be passed
1427  * by caller to call the above program_initplr( )
1428  *-----------------------------------------------------------------*/
1429 static void program_mode(unsigned long *dimm_populated,
1430                          unsigned char *iic0_dimm_addr,
1431                          unsigned long num_dimm_banks,
1432                          ddr_cas_id_t *selected_cas,
1433                          int *write_recovery)
1434 {
1435         unsigned long dimm_num;
1436         unsigned long sdram_ddr1;
1437         unsigned long t_wr_ns;
1438         unsigned long t_wr_clk;
1439         unsigned long cas_bit;
1440         unsigned long cas_index;
1441         unsigned long sdram_freq;
1442         unsigned long ddr_check;
1443         unsigned long mmode;
1444         unsigned long tcyc_reg;
1445         unsigned long cycle_2_0_clk;
1446         unsigned long cycle_2_5_clk;
1447         unsigned long cycle_3_0_clk;
1448         unsigned long cycle_4_0_clk;
1449         unsigned long cycle_5_0_clk;
1450         unsigned long max_2_0_tcyc_ns_x_100;
1451         unsigned long max_2_5_tcyc_ns_x_100;
1452         unsigned long max_3_0_tcyc_ns_x_100;
1453         unsigned long max_4_0_tcyc_ns_x_100;
1454         unsigned long max_5_0_tcyc_ns_x_100;
1455         unsigned long cycle_time_ns_x_100[3];
1456         PPC4xx_SYS_INFO board_cfg;
1457         unsigned char cas_2_0_available;
1458         unsigned char cas_2_5_available;
1459         unsigned char cas_3_0_available;
1460         unsigned char cas_4_0_available;
1461         unsigned char cas_5_0_available;
1462         unsigned long sdr_ddrpll;
1463
1464         /*------------------------------------------------------------------
1465          * Get the board configuration info.
1466          *-----------------------------------------------------------------*/
1467         get_sys_info(&board_cfg);
1468
1469         mfsdr(SDR0_DDR0, sdr_ddrpll);
1470         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1471         debug("sdram_freq=%lu\n", sdram_freq);
1472
1473         /*------------------------------------------------------------------
1474          * Handle the timing.  We need to find the worst case timing of all
1475          * the dimm modules installed.
1476          *-----------------------------------------------------------------*/
1477         t_wr_ns = 0;
1478         cas_2_0_available = TRUE;
1479         cas_2_5_available = TRUE;
1480         cas_3_0_available = TRUE;
1481         cas_4_0_available = TRUE;
1482         cas_5_0_available = TRUE;
1483         max_2_0_tcyc_ns_x_100 = 10;
1484         max_2_5_tcyc_ns_x_100 = 10;
1485         max_3_0_tcyc_ns_x_100 = 10;
1486         max_4_0_tcyc_ns_x_100 = 10;
1487         max_5_0_tcyc_ns_x_100 = 10;
1488         sdram_ddr1 = TRUE;
1489
1490         /* loop through all the DIMM slots on the board */
1491         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1492                 /* If a dimm is installed in a particular slot ... */
1493                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1494                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1495                                 sdram_ddr1 = TRUE;
1496                         else
1497                                 sdram_ddr1 = FALSE;
1498
1499                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1500                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1501                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1502
1503                         /* For a particular DIMM, grab the three CAS values it supports */
1504                         for (cas_index = 0; cas_index < 3; cas_index++) {
1505                                 switch (cas_index) {
1506                                 case 0:
1507                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1508                                         break;
1509                                 case 1:
1510                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1511                                         break;
1512                                 default:
1513                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1514                                         break;
1515                                 }
1516
1517                                 if ((tcyc_reg & 0x0F) >= 10) {
1518                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1519                                                 /* Convert from hex to decimal */
1520                                                 cycle_time_ns_x_100[cas_index] =
1521                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1522                                         } else {
1523                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1524                                                        "in slot %d\n", (unsigned int)dimm_num);
1525                                                 spd_ddr_init_hang ();
1526                                         }
1527                                 } else {
1528                                         /* Convert from hex to decimal */
1529                                         cycle_time_ns_x_100[cas_index] =
1530                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1531                                                 ((tcyc_reg & 0x0F)*10);
1532                                 }
1533                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1534                                       cycle_time_ns_x_100[cas_index]);
1535                         }
1536
1537                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1538                         /* supported for a particular DIMM. */
1539                         cas_index = 0;
1540
1541                         if (sdram_ddr1) {
1542                                 /*
1543                                  * DDR devices use the following bitmask for CAS latency:
1544                                  *  Bit   7    6    5    4    3    2    1    0
1545                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1546                                  */
1547                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1548                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1549                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1550                                                                     cycle_time_ns_x_100[cas_index]);
1551                                         cas_index++;
1552                                 } else {
1553                                         if (cas_index != 0)
1554                                                 cas_index++;
1555                                         cas_4_0_available = FALSE;
1556                                 }
1557
1558                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1559                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1560                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1561                                                                     cycle_time_ns_x_100[cas_index]);
1562                                         cas_index++;
1563                                 } else {
1564                                         if (cas_index != 0)
1565                                                 cas_index++;
1566                                         cas_3_0_available = FALSE;
1567                                 }
1568
1569                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1570                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1571                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1572                                                                     cycle_time_ns_x_100[cas_index]);
1573                                         cas_index++;
1574                                 } else {
1575                                         if (cas_index != 0)
1576                                                 cas_index++;
1577                                         cas_2_5_available = FALSE;
1578                                 }
1579
1580                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1581                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1582                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1583                                                                     cycle_time_ns_x_100[cas_index]);
1584                                         cas_index++;
1585                                 } else {
1586                                         if (cas_index != 0)
1587                                                 cas_index++;
1588                                         cas_2_0_available = FALSE;
1589                                 }
1590                         } else {
1591                                 /*
1592                                  * DDR2 devices use the following bitmask for CAS latency:
1593                                  *  Bit   7    6    5    4    3    2    1    0
1594                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1595                                  */
1596                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1597                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1598                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1599                                                                     cycle_time_ns_x_100[cas_index]);
1600                                         cas_index++;
1601                                 } else {
1602                                         if (cas_index != 0)
1603                                                 cas_index++;
1604                                         cas_5_0_available = FALSE;
1605                                 }
1606
1607                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1608                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1609                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1610                                                                     cycle_time_ns_x_100[cas_index]);
1611                                         cas_index++;
1612                                 } else {
1613                                         if (cas_index != 0)
1614                                                 cas_index++;
1615                                         cas_4_0_available = FALSE;
1616                                 }
1617
1618                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1619                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1620                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1621                                                                     cycle_time_ns_x_100[cas_index]);
1622                                         cas_index++;
1623                                 } else {
1624                                         if (cas_index != 0)
1625                                                 cas_index++;
1626                                         cas_3_0_available = FALSE;
1627                                 }
1628                         }
1629                 }
1630         }
1631
1632         /*------------------------------------------------------------------
1633          * Set the SDRAM mode, SDRAM_MMODE
1634          *-----------------------------------------------------------------*/
1635         mfsdram(SDRAM_MMODE, mmode);
1636         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1637
1638         /* add 10 here because of rounding problems */
1639         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1640         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1641         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1642         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1643         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1644         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1645         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1646         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1647
1648         if (sdram_ddr1 == TRUE) { /* DDR1 */
1649                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1650                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1651                         *selected_cas = DDR_CAS_2;
1652                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1653                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1654                         *selected_cas = DDR_CAS_2_5;
1655                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1656                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1657                         *selected_cas = DDR_CAS_3;
1658                 } else {
1659                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1660                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1661                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1662                         spd_ddr_init_hang ();
1663                 }
1664         } else { /* DDR2 */
1665                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1666                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1667                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1668                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1669                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1670                         *selected_cas = DDR_CAS_3;
1671                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1672                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1673                         *selected_cas = DDR_CAS_4;
1674                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1675                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1676                         *selected_cas = DDR_CAS_5;
1677                 } else {
1678                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1679                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1680                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1681                         printf("cas3=%d cas4=%d cas5=%d\n",
1682                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1683                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1684                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1685                         spd_ddr_init_hang ();
1686                 }
1687         }
1688
1689         if (sdram_ddr1 == TRUE)
1690                 mmode |= SDRAM_MMODE_WR_DDR1;
1691         else {
1692
1693                 /* loop through all the DIMM slots on the board */
1694                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1695                         /* If a dimm is installed in a particular slot ... */
1696                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1697                                 t_wr_ns = max(t_wr_ns,
1698                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1699                 }
1700
1701                 /*
1702                  * convert from nanoseconds to ddr clocks
1703                  * round up if necessary
1704                  */
1705                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1706                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1707                 if (sdram_freq != ddr_check)
1708                         t_wr_clk++;
1709
1710                 switch (t_wr_clk) {
1711                 case 0:
1712                 case 1:
1713                 case 2:
1714                 case 3:
1715                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1716                         break;
1717                 case 4:
1718                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1719                         break;
1720                 case 5:
1721                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1722                         break;
1723                 default:
1724                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1725                         break;
1726                 }
1727                 *write_recovery = t_wr_clk;
1728         }
1729
1730         debug("CAS latency = %d\n", *selected_cas);
1731         debug("Write recovery = %d\n", *write_recovery);
1732
1733         mtsdram(SDRAM_MMODE, mmode);
1734 }
1735
1736 /*-----------------------------------------------------------------------------+
1737  * program_rtr.
1738  *-----------------------------------------------------------------------------*/
1739 static void program_rtr(unsigned long *dimm_populated,
1740                         unsigned char *iic0_dimm_addr,
1741                         unsigned long num_dimm_banks)
1742 {
1743         PPC4xx_SYS_INFO board_cfg;
1744         unsigned long max_refresh_rate;
1745         unsigned long dimm_num;
1746         unsigned long refresh_rate_type;
1747         unsigned long refresh_rate;
1748         unsigned long rint;
1749         unsigned long sdram_freq;
1750         unsigned long sdr_ddrpll;
1751         unsigned long val;
1752
1753         /*------------------------------------------------------------------
1754          * Get the board configuration info.
1755          *-----------------------------------------------------------------*/
1756         get_sys_info(&board_cfg);
1757
1758         /*------------------------------------------------------------------
1759          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1760          *-----------------------------------------------------------------*/
1761         mfsdr(SDR0_DDR0, sdr_ddrpll);
1762         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1763
1764         max_refresh_rate = 0;
1765         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1766                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1767
1768                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1769                         refresh_rate_type &= 0x7F;
1770                         switch (refresh_rate_type) {
1771                         case 0:
1772                                 refresh_rate =  15625;
1773                                 break;
1774                         case 1:
1775                                 refresh_rate =   3906;
1776                                 break;
1777                         case 2:
1778                                 refresh_rate =   7812;
1779                                 break;
1780                         case 3:
1781                                 refresh_rate =  31250;
1782                                 break;
1783                         case 4:
1784                                 refresh_rate =  62500;
1785                                 break;
1786                         case 5:
1787                                 refresh_rate = 125000;
1788                                 break;
1789                         default:
1790                                 refresh_rate = 0;
1791                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1792                                        (unsigned int)dimm_num);
1793                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1794                                 spd_ddr_init_hang ();
1795                                 break;
1796                         }
1797
1798                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1799                 }
1800         }
1801
1802         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1803         mfsdram(SDRAM_RTR, val);
1804         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1805                 (SDRAM_RTR_RINT_ENCODE(rint)));
1806 }
1807
1808 /*------------------------------------------------------------------
1809  * This routine programs the SDRAM_TRx registers.
1810  *-----------------------------------------------------------------*/
1811 static void program_tr(unsigned long *dimm_populated,
1812                        unsigned char *iic0_dimm_addr,
1813                        unsigned long num_dimm_banks)
1814 {
1815         unsigned long dimm_num;
1816         unsigned long sdram_ddr1;
1817         unsigned long t_rp_ns;
1818         unsigned long t_rcd_ns;
1819         unsigned long t_rrd_ns;
1820         unsigned long t_ras_ns;
1821         unsigned long t_rc_ns;
1822         unsigned long t_rfc_ns;
1823         unsigned long t_wpc_ns;
1824         unsigned long t_wtr_ns;
1825         unsigned long t_rpc_ns;
1826         unsigned long t_rp_clk;
1827         unsigned long t_rcd_clk;
1828         unsigned long t_rrd_clk;
1829         unsigned long t_ras_clk;
1830         unsigned long t_rc_clk;
1831         unsigned long t_rfc_clk;
1832         unsigned long t_wpc_clk;
1833         unsigned long t_wtr_clk;
1834         unsigned long t_rpc_clk;
1835         unsigned long sdtr1, sdtr2, sdtr3;
1836         unsigned long ddr_check;
1837         unsigned long sdram_freq;
1838         unsigned long sdr_ddrpll;
1839
1840         PPC4xx_SYS_INFO board_cfg;
1841
1842         /*------------------------------------------------------------------
1843          * Get the board configuration info.
1844          *-----------------------------------------------------------------*/
1845         get_sys_info(&board_cfg);
1846
1847         mfsdr(SDR0_DDR0, sdr_ddrpll);
1848         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1849
1850         /*------------------------------------------------------------------
1851          * Handle the timing.  We need to find the worst case timing of all
1852          * the dimm modules installed.
1853          *-----------------------------------------------------------------*/
1854         t_rp_ns = 0;
1855         t_rrd_ns = 0;
1856         t_rcd_ns = 0;
1857         t_ras_ns = 0;
1858         t_rc_ns = 0;
1859         t_rfc_ns = 0;
1860         t_wpc_ns = 0;
1861         t_wtr_ns = 0;
1862         t_rpc_ns = 0;
1863         sdram_ddr1 = TRUE;
1864
1865         /* loop through all the DIMM slots on the board */
1866         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1867                 /* If a dimm is installed in a particular slot ... */
1868                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1869                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1870                                 sdram_ddr1 = TRUE;
1871                         else
1872                                 sdram_ddr1 = FALSE;
1873
1874                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1875                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1876                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1877                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1878                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1879                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1880                 }
1881         }
1882
1883         /*------------------------------------------------------------------
1884          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1885          *-----------------------------------------------------------------*/
1886         mfsdram(SDRAM_SDTR1, sdtr1);
1887         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1888                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1889
1890         /* default values */
1891         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1892         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1893
1894         /* normal operations */
1895         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1896         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1897
1898         mtsdram(SDRAM_SDTR1, sdtr1);
1899
1900         /*------------------------------------------------------------------
1901          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1902          *-----------------------------------------------------------------*/
1903         mfsdram(SDRAM_SDTR2, sdtr2);
1904         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1905                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1906                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1907                    SDRAM_SDTR2_RRD_MASK);
1908
1909         /*
1910          * convert t_rcd from nanoseconds to ddr clocks
1911          * round up if necessary
1912          */
1913         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1914         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1915         if (sdram_freq != ddr_check)
1916                 t_rcd_clk++;
1917
1918         switch (t_rcd_clk) {
1919         case 0:
1920         case 1:
1921                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1922                 break;
1923         case 2:
1924                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1925                 break;
1926         case 3:
1927                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1928                 break;
1929         case 4:
1930                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1931                 break;
1932         default:
1933                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1934                 break;
1935         }
1936
1937         if (sdram_ddr1 == TRUE) { /* DDR1 */
1938                 if (sdram_freq < 200000000) {
1939                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1940                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1941                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1942                 } else {
1943                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1944                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1945                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1946                 }
1947         } else { /* DDR2 */
1948                 /* loop through all the DIMM slots on the board */
1949                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1950                         /* If a dimm is installed in a particular slot ... */
1951                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1952                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1953                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1954                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1955                         }
1956                 }
1957
1958                 /*
1959                  * convert from nanoseconds to ddr clocks
1960                  * round up if necessary
1961                  */
1962                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1963                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1964                 if (sdram_freq != ddr_check)
1965                         t_wpc_clk++;
1966
1967                 switch (t_wpc_clk) {
1968                 case 0:
1969                 case 1:
1970                 case 2:
1971                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1972                         break;
1973                 case 3:
1974                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1975                         break;
1976                 case 4:
1977                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1978                         break;
1979                 case 5:
1980                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1981                         break;
1982                 default:
1983                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1984                         break;
1985                 }
1986
1987                 /*
1988                  * convert from nanoseconds to ddr clocks
1989                  * round up if necessary
1990                  */
1991                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1992                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1993                 if (sdram_freq != ddr_check)
1994                         t_wtr_clk++;
1995
1996                 switch (t_wtr_clk) {
1997                 case 0:
1998                 case 1:
1999                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
2000                         break;
2001                 case 2:
2002                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
2003                         break;
2004                 case 3:
2005                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
2006                         break;
2007                 default:
2008                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
2009                         break;
2010                 }
2011
2012                 /*
2013                  * convert from nanoseconds to ddr clocks
2014                  * round up if necessary
2015                  */
2016                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2017                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2018                 if (sdram_freq != ddr_check)
2019                         t_rpc_clk++;
2020
2021                 switch (t_rpc_clk) {
2022                 case 0:
2023                 case 1:
2024                 case 2:
2025                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2026                         break;
2027                 case 3:
2028                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2029                         break;
2030                 default:
2031                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2032                         break;
2033                 }
2034         }
2035
2036         /* default value */
2037         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2038
2039         /*
2040          * convert t_rrd from nanoseconds to ddr clocks
2041          * round up if necessary
2042          */
2043         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2044         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2045         if (sdram_freq != ddr_check)
2046                 t_rrd_clk++;
2047
2048         if (t_rrd_clk == 3)
2049                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2050         else
2051                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2052
2053         /*
2054          * convert t_rp from nanoseconds to ddr clocks
2055          * round up if necessary
2056          */
2057         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2058         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2059         if (sdram_freq != ddr_check)
2060                 t_rp_clk++;
2061
2062         switch (t_rp_clk) {
2063         case 0:
2064         case 1:
2065         case 2:
2066         case 3:
2067                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2068                 break;
2069         case 4:
2070                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2071                 break;
2072         case 5:
2073                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2074                 break;
2075         case 6:
2076                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2077                 break;
2078         default:
2079                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2080                 break;
2081         }
2082
2083         mtsdram(SDRAM_SDTR2, sdtr2);
2084
2085         /*------------------------------------------------------------------
2086          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2087          *-----------------------------------------------------------------*/
2088         mfsdram(SDRAM_SDTR3, sdtr3);
2089         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2090                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2091
2092         /*
2093          * convert t_ras from nanoseconds to ddr clocks
2094          * round up if necessary
2095          */
2096         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2097         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2098         if (sdram_freq != ddr_check)
2099                 t_ras_clk++;
2100
2101         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2102
2103         /*
2104          * convert t_rc from nanoseconds to ddr clocks
2105          * round up if necessary
2106          */
2107         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2108         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2109         if (sdram_freq != ddr_check)
2110                 t_rc_clk++;
2111
2112         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2113
2114         /* default xcs value */
2115         sdtr3 |= SDRAM_SDTR3_XCS;
2116
2117         /*
2118          * convert t_rfc from nanoseconds to ddr clocks
2119          * round up if necessary
2120          */
2121         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2122         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2123         if (sdram_freq != ddr_check)
2124                 t_rfc_clk++;
2125
2126         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2127
2128         mtsdram(SDRAM_SDTR3, sdtr3);
2129 }
2130
2131 /*-----------------------------------------------------------------------------+
2132  * program_bxcf.
2133  *-----------------------------------------------------------------------------*/
2134 static void program_bxcf(unsigned long *dimm_populated,
2135                          unsigned char *iic0_dimm_addr,
2136                          unsigned long num_dimm_banks)
2137 {
2138         unsigned long dimm_num;
2139         unsigned long num_col_addr;
2140         unsigned long num_ranks;
2141         unsigned long num_banks;
2142         unsigned long mode;
2143         unsigned long ind_rank;
2144         unsigned long ind;
2145         unsigned long ind_bank;
2146         unsigned long bank_0_populated;
2147
2148         /*------------------------------------------------------------------
2149          * Set the BxCF regs.  First, wipe out the bank config registers.
2150          *-----------------------------------------------------------------*/
2151         mtsdram(SDRAM_MB0CF, 0x00000000);
2152         mtsdram(SDRAM_MB1CF, 0x00000000);
2153         mtsdram(SDRAM_MB2CF, 0x00000000);
2154         mtsdram(SDRAM_MB3CF, 0x00000000);
2155
2156         mode = SDRAM_BXCF_M_BE_ENABLE;
2157
2158         bank_0_populated = 0;
2159
2160         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2161                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2162                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2163                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2164                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2165                                 num_ranks = (num_ranks & 0x0F) +1;
2166                         else
2167                                 num_ranks = num_ranks & 0x0F;
2168
2169                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2170
2171                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2172                                 if (num_banks == 4)
2173                                         ind = 0;
2174                                 else
2175                                         ind = 5 << 8;
2176                                 switch (num_col_addr) {
2177                                 case 0x08:
2178                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2179                                         break;
2180                                 case 0x09:
2181                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2182                                         break;
2183                                 case 0x0A:
2184                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2185                                         break;
2186                                 case 0x0B:
2187                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2188                                         break;
2189                                 case 0x0C:
2190                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2191                                         break;
2192                                 default:
2193                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2194                                                (unsigned int)dimm_num);
2195                                         printf("ERROR: Unsupported value for number of "
2196                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2197                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2198                                         spd_ddr_init_hang ();
2199                                 }
2200                         }
2201
2202                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2203                                 bank_0_populated = 1;
2204
2205                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2206                                 mtsdram(SDRAM_MB0CF +
2207                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2208                                         mode);
2209                         }
2210                 }
2211         }
2212 }
2213
2214 /*------------------------------------------------------------------
2215  * program memory queue.
2216  *-----------------------------------------------------------------*/
2217 static void program_memory_queue(unsigned long *dimm_populated,
2218                                  unsigned char *iic0_dimm_addr,
2219                                  unsigned long num_dimm_banks)
2220 {
2221         unsigned long dimm_num;
2222         phys_size_t rank_base_addr;
2223         unsigned long rank_reg;
2224         phys_size_t rank_size_bytes;
2225         unsigned long rank_size_id;
2226         unsigned long num_ranks;
2227         unsigned long baseadd_size;
2228         unsigned long i;
2229         unsigned long bank_0_populated = 0;
2230         phys_size_t total_size = 0;
2231
2232         /*------------------------------------------------------------------
2233          * Reset the rank_base_address.
2234          *-----------------------------------------------------------------*/
2235         rank_reg   = SDRAM_R0BAS;
2236
2237         rank_base_addr = 0x00000000;
2238
2239         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2240                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2241                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2242                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2243                                 num_ranks = (num_ranks & 0x0F) + 1;
2244                         else
2245                                 num_ranks = num_ranks & 0x0F;
2246
2247                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2248
2249                         /*------------------------------------------------------------------
2250                          * Set the sizes
2251                          *-----------------------------------------------------------------*/
2252                         baseadd_size = 0;
2253                         switch (rank_size_id) {
2254                         case 0x01:
2255                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2256                                 total_size = 1024;
2257                                 break;
2258                         case 0x02:
2259                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2260                                 total_size = 2048;
2261                                 break;
2262                         case 0x04:
2263                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2264                                 total_size = 4096;
2265                                 break;
2266                         case 0x08:
2267                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2268                                 total_size = 32;
2269                                 break;
2270                         case 0x10:
2271                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2272                                 total_size = 64;
2273                                 break;
2274                         case 0x20:
2275                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2276                                 total_size = 128;
2277                                 break;
2278                         case 0x40:
2279                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2280                                 total_size = 256;
2281                                 break;
2282                         case 0x80:
2283                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2284                                 total_size = 512;
2285                                 break;
2286                         default:
2287                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2288                                        (unsigned int)dimm_num);
2289                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2290                                        (unsigned int)rank_size_id);
2291                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2292                                 spd_ddr_init_hang ();
2293                         }
2294                         rank_size_bytes = total_size << 20;
2295
2296                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2297                                 bank_0_populated = 1;
2298
2299                         for (i = 0; i < num_ranks; i++) {
2300                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2301                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2302                                            baseadd_size));
2303                                 rank_base_addr += rank_size_bytes;
2304                         }
2305                 }
2306         }
2307
2308 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2309     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2310     defined(CONFIG_460SX)
2311         /*
2312          * Enable high bandwidth access
2313          * This is currently not used, but with this setup
2314          * it is possible to use it later on in e.g. the Linux
2315          * EMAC driver for performance gain.
2316          */
2317         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2318         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2319
2320         /*
2321          * Set optimal value for Memory Queue HB/LL Configuration registers
2322          */
2323         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2324               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2325               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2326         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2327               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2328               SDRAM_CONF1LL_RPLM);
2329         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2330 #endif
2331 }
2332
2333 #ifdef CONFIG_DDR_ECC
2334 /*-----------------------------------------------------------------------------+
2335  * program_ecc.
2336  *-----------------------------------------------------------------------------*/
2337 static void program_ecc(unsigned long *dimm_populated,
2338                         unsigned char *iic0_dimm_addr,
2339                         unsigned long num_dimm_banks,
2340                         unsigned long tlb_word2_i_value)
2341 {
2342         unsigned long dimm_num;
2343         unsigned long ecc;
2344
2345         ecc = 0;
2346         /* loop through all the DIMM slots on the board */
2347         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2348                 /* If a dimm is installed in a particular slot ... */
2349                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2350                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2351         }
2352         if (ecc == 0)
2353                 return;
2354
2355         do_program_ecc(tlb_word2_i_value);
2356 }
2357 #endif
2358
2359 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2360 /*-----------------------------------------------------------------------------+
2361  * program_DQS_calibration.
2362  *-----------------------------------------------------------------------------*/
2363 static void program_DQS_calibration(unsigned long *dimm_populated,
2364                                     unsigned char *iic0_dimm_addr,
2365                                     unsigned long num_dimm_banks)
2366 {
2367         unsigned long val;
2368
2369 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2370         mtsdram(SDRAM_RQDC, 0x80000037);
2371         mtsdram(SDRAM_RDCC, 0x40000000);
2372         mtsdram(SDRAM_RFDC, 0x000001DF);
2373
2374         test();
2375 #else
2376         /*------------------------------------------------------------------
2377          * Program RDCC register
2378          * Read sample cycle auto-update enable
2379          *-----------------------------------------------------------------*/
2380
2381         mfsdram(SDRAM_RDCC, val);
2382         mtsdram(SDRAM_RDCC,
2383                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2384                 | SDRAM_RDCC_RSAE_ENABLE);
2385
2386         /*------------------------------------------------------------------
2387          * Program RQDC register
2388          * Internal DQS delay mechanism enable
2389          *-----------------------------------------------------------------*/
2390         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2391
2392         /*------------------------------------------------------------------
2393          * Program RFDC register
2394          * Set Feedback Fractional Oversample
2395          * Auto-detect read sample cycle enable
2396          * Set RFOS to 1/4 of memclk cycle (0x3f)
2397          *-----------------------------------------------------------------*/
2398         mfsdram(SDRAM_RFDC, val);
2399         mtsdram(SDRAM_RFDC,
2400                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2401                          SDRAM_RFDC_RFFD_MASK))
2402                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2403                    SDRAM_RFDC_RFFD_ENCODE(0)));
2404
2405         DQS_calibration_process();
2406 #endif
2407 }
2408
2409 static int short_mem_test(void)
2410 {
2411         u32 *membase;
2412         u32 bxcr_num;
2413         u32 bxcf;
2414         int i;
2415         int j;
2416         phys_size_t base_addr;
2417         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2418                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2419                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2420                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2421                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2422                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2423                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2424                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2425                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2426                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2427                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2428                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2429                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2430                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2431                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2432                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2433                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2434         int l;
2435
2436         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2437                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2438
2439                 /* Banks enabled */
2440                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2441                         /* Bank is enabled */
2442
2443                         /*
2444                          * Only run test on accessable memory (below 2GB)
2445                          */
2446                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2447                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2448                                 continue;
2449
2450                         /*------------------------------------------------------------------
2451                          * Run the short memory test.
2452                          *-----------------------------------------------------------------*/
2453                         membase = (u32 *)(u32)base_addr;
2454
2455                         for (i = 0; i < NUMMEMTESTS; i++) {
2456                                 for (j = 0; j < NUMMEMWORDS; j++) {
2457                                         membase[j] = test[i][j];
2458                                         ppcDcbf((u32)&(membase[j]));
2459                                 }
2460                                 sync();
2461                                 for (l=0; l<NUMLOOPS; l++) {
2462                                         for (j = 0; j < NUMMEMWORDS; j++) {
2463                                                 if (membase[j] != test[i][j]) {
2464                                                         ppcDcbf((u32)&(membase[j]));
2465                                                         return 0;
2466                                                 }
2467                                                 ppcDcbf((u32)&(membase[j]));
2468                                         }
2469                                         sync();
2470                                 }
2471                         }
2472                 }       /* if bank enabled */
2473         }               /* for bxcf_num */
2474
2475         return 1;
2476 }
2477
2478 #ifndef HARD_CODED_DQS
2479 /*-----------------------------------------------------------------------------+
2480  * DQS_calibration_process.
2481  *-----------------------------------------------------------------------------*/
2482 static void DQS_calibration_process(void)
2483 {
2484         unsigned long rfdc_reg;
2485         unsigned long rffd;
2486         unsigned long val;
2487         long rffd_average;
2488         long max_start;
2489         long min_end;
2490         unsigned long begin_rqfd[MAXRANKS];
2491         unsigned long begin_rffd[MAXRANKS];
2492         unsigned long end_rqfd[MAXRANKS];
2493         unsigned long end_rffd[MAXRANKS];
2494         char window_found;
2495         unsigned long dlycal;
2496         unsigned long dly_val;
2497         unsigned long max_pass_length;
2498         unsigned long current_pass_length;
2499         unsigned long current_fail_length;
2500         unsigned long current_start;
2501         long max_end;
2502         unsigned char fail_found;
2503         unsigned char pass_found;
2504 #if !defined(CONFIG_DDR_RQDC_FIXED)
2505         u32 rqdc_reg;
2506         u32 rqfd;
2507         u32 rqfd_start;
2508         u32 rqfd_average;
2509         int loopi = 0;
2510         char str[] = "Auto calibration -";
2511         char slash[] = "\\|/-\\|/-";
2512
2513         /*------------------------------------------------------------------
2514          * Test to determine the best read clock delay tuning bits.
2515          *
2516          * Before the DDR controller can be used, the read clock delay needs to be
2517          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2518          * This value cannot be hardcoded into the program because it changes
2519          * depending on the board's setup and environment.
2520          * To do this, all delay values are tested to see if they
2521          * work or not.  By doing this, you get groups of fails with groups of
2522          * passing values.  The idea is to find the start and end of a passing
2523          * window and take the center of it to use as the read clock delay.
2524          *
2525          * A failure has to be seen first so that when we hit a pass, we know
2526          * that it is truely the start of the window.  If we get passing values
2527          * to start off with, we don't know if we are at the start of the window.
2528          *
2529          * The code assumes that a failure will always be found.
2530          * If a failure is not found, there is no easy way to get the middle
2531          * of the passing window.  I guess we can pretty much pick any value
2532          * but some values will be better than others.  Since the lowest speed
2533          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2534          * from experimentation it is safe to say you will always have a failure.
2535          *-----------------------------------------------------------------*/
2536
2537         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2538         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2539
2540         puts(str);
2541
2542 calibration_loop:
2543         mfsdram(SDRAM_RQDC, rqdc_reg);
2544         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2545                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2546 #else /* CONFIG_DDR_RQDC_FIXED */
2547         /*
2548          * On Katmai the complete auto-calibration somehow doesn't seem to
2549          * produce the best results, meaning optimal values for RQFD/RFFD.
2550          * This was discovered by GDA using a high bandwidth scope,
2551          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2552          * so now on Katmai "only" RFFD is auto-calibrated.
2553          */
2554         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2555 #endif /* CONFIG_DDR_RQDC_FIXED */
2556
2557         max_start = 0;
2558         min_end = 0;
2559         begin_rqfd[0] = 0;
2560         begin_rffd[0] = 0;
2561         begin_rqfd[1] = 0;
2562         begin_rffd[1] = 0;
2563         end_rqfd[0] = 0;
2564         end_rffd[0] = 0;
2565         end_rqfd[1] = 0;
2566         end_rffd[1] = 0;
2567         window_found = FALSE;
2568
2569         max_pass_length = 0;
2570         max_start = 0;
2571         max_end = 0;
2572         current_pass_length = 0;
2573         current_fail_length = 0;
2574         current_start = 0;
2575         window_found = FALSE;
2576         fail_found = FALSE;
2577         pass_found = FALSE;
2578
2579         /*
2580          * get the delay line calibration register value
2581          */
2582         mfsdram(SDRAM_DLCR, dlycal);
2583         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2584
2585         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2586                 mfsdram(SDRAM_RFDC, rfdc_reg);
2587                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2588
2589                 /*------------------------------------------------------------------
2590                  * Set the timing reg for the test.
2591                  *-----------------------------------------------------------------*/
2592                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2593
2594                 /*------------------------------------------------------------------
2595                  * See if the rffd value passed.
2596                  *-----------------------------------------------------------------*/
2597                 if (short_mem_test()) {
2598                         if (fail_found == TRUE) {
2599                                 pass_found = TRUE;
2600                                 if (current_pass_length == 0)
2601                                         current_start = rffd;
2602
2603                                 current_fail_length = 0;
2604                                 current_pass_length++;
2605
2606                                 if (current_pass_length > max_pass_length) {
2607                                         max_pass_length = current_pass_length;
2608                                         max_start = current_start;
2609                                         max_end = rffd;
2610                                 }
2611                         }
2612                 } else {
2613                         current_pass_length = 0;
2614                         current_fail_length++;
2615
2616                         if (current_fail_length >= (dly_val >> 2)) {
2617                                 if (fail_found == FALSE) {
2618                                         fail_found = TRUE;
2619                                 } else if (pass_found == TRUE) {
2620                                         window_found = TRUE;
2621                                         break;
2622                                 }
2623                         }
2624                 }
2625         }               /* for rffd */
2626
2627         /*------------------------------------------------------------------
2628          * Set the average RFFD value
2629          *-----------------------------------------------------------------*/
2630         rffd_average = ((max_start + max_end) >> 1);
2631
2632         if (rffd_average < 0)
2633                 rffd_average = 0;
2634
2635         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2636                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2637         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2638         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2639
2640 #if !defined(CONFIG_DDR_RQDC_FIXED)
2641         max_pass_length = 0;
2642         max_start = 0;
2643         max_end = 0;
2644         current_pass_length = 0;
2645         current_fail_length = 0;
2646         current_start = 0;
2647         window_found = FALSE;
2648         fail_found = FALSE;
2649         pass_found = FALSE;
2650
2651         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2652                 mfsdram(SDRAM_RQDC, rqdc_reg);
2653                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2654
2655                 /*------------------------------------------------------------------
2656                  * Set the timing reg for the test.
2657                  *-----------------------------------------------------------------*/
2658                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2659
2660                 /*------------------------------------------------------------------
2661                  * See if the rffd value passed.
2662                  *-----------------------------------------------------------------*/
2663                 if (short_mem_test()) {
2664                         if (fail_found == TRUE) {
2665                                 pass_found = TRUE;
2666                                 if (current_pass_length == 0)
2667                                         current_start = rqfd;
2668
2669                                 current_fail_length = 0;
2670                                 current_pass_length++;
2671
2672                                 if (current_pass_length > max_pass_length) {
2673                                         max_pass_length = current_pass_length;
2674                                         max_start = current_start;
2675                                         max_end = rqfd;
2676                                 }
2677                         }
2678                 } else {
2679                         current_pass_length = 0;
2680                         current_fail_length++;
2681
2682                         if (fail_found == FALSE) {
2683                                 fail_found = TRUE;
2684                         } else if (pass_found == TRUE) {
2685                                 window_found = TRUE;
2686                                 break;
2687                         }
2688                 }
2689         }
2690
2691         rqfd_average = ((max_start + max_end) >> 1);
2692
2693         /*------------------------------------------------------------------
2694          * Make sure we found the valid read passing window.  Halt if not
2695          *-----------------------------------------------------------------*/
2696         if (window_found == FALSE) {
2697                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2698                         putc('\b');
2699                         putc(slash[loopi++ % 8]);
2700
2701                         /* try again from with a different RQFD start value */
2702                         rqfd_start++;
2703                         goto calibration_loop;
2704                 }
2705
2706                 printf("\nERROR: Cannot determine a common read delay for the "
2707                        "DIMM(s) installed.\n");
2708                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2709                 ppc4xx_ibm_ddr2_register_dump();
2710                 spd_ddr_init_hang ();
2711         }
2712
2713         if (rqfd_average < 0)
2714                 rqfd_average = 0;
2715
2716         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2717                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2718
2719         mtsdram(SDRAM_RQDC,
2720                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2721                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2722
2723         blank_string(strlen(str));
2724 #endif /* CONFIG_DDR_RQDC_FIXED */
2725
2726         mfsdram(SDRAM_DLCR, val);
2727         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2728         mfsdram(SDRAM_RQDC, val);
2729         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2730         mfsdram(SDRAM_RFDC, val);
2731         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2732         mfsdram(SDRAM_RDCC, val);
2733         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2734 }
2735 #else /* calibration test with hardvalues */
2736 /*-----------------------------------------------------------------------------+
2737  * DQS_calibration_process.
2738  *-----------------------------------------------------------------------------*/
2739 static void test(void)
2740 {
2741         unsigned long dimm_num;
2742         unsigned long ecc_temp;
2743         unsigned long i, j;
2744         unsigned long *membase;
2745         unsigned long bxcf[MAXRANKS];
2746         unsigned long val;
2747         char window_found;
2748         char begin_found[MAXDIMMS];
2749         char end_found[MAXDIMMS];
2750         char search_end[MAXDIMMS];
2751         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2752                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2753                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2754                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2755                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2756                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2757                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2758                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2759                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2760                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2761                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2762                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2763                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2764                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2765                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2766                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2767                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2768
2769         /*------------------------------------------------------------------
2770          * Test to determine the best read clock delay tuning bits.
2771          *
2772          * Before the DDR controller can be used, the read clock delay needs to be
2773          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2774          * This value cannot be hardcoded into the program because it changes
2775          * depending on the board's setup and environment.
2776          * To do this, all delay values are tested to see if they
2777          * work or not.  By doing this, you get groups of fails with groups of
2778          * passing values.  The idea is to find the start and end of a passing
2779          * window and take the center of it to use as the read clock delay.
2780          *
2781          * A failure has to be seen first so that when we hit a pass, we know
2782          * that it is truely the start of the window.  If we get passing values
2783          * to start off with, we don't know if we are at the start of the window.
2784          *
2785          * The code assumes that a failure will always be found.
2786          * If a failure is not found, there is no easy way to get the middle
2787          * of the passing window.  I guess we can pretty much pick any value
2788          * but some values will be better than others.  Since the lowest speed
2789          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2790          * from experimentation it is safe to say you will always have a failure.
2791          *-----------------------------------------------------------------*/
2792         mfsdram(SDRAM_MCOPT1, ecc_temp);
2793         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2794         mfsdram(SDRAM_MCOPT1, val);
2795         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2796                 SDRAM_MCOPT1_MCHK_NON);
2797
2798         window_found = FALSE;
2799         begin_found[0] = FALSE;
2800         end_found[0] = FALSE;
2801         search_end[0] = FALSE;
2802         begin_found[1] = FALSE;
2803         end_found[1] = FALSE;
2804         search_end[1] = FALSE;
2805
2806         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2807                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2808
2809                 /* Banks enabled */
2810                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2811
2812                         /* Bank is enabled */
2813                         membase =
2814                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2815
2816                         /*------------------------------------------------------------------
2817                          * Run the short memory test.
2818                          *-----------------------------------------------------------------*/
2819                         for (i = 0; i < NUMMEMTESTS; i++) {
2820                                 for (j = 0; j < NUMMEMWORDS; j++) {
2821                                         membase[j] = test[i][j];
2822                                         ppcDcbf((u32)&(membase[j]));
2823                                 }
2824                                 sync();
2825                                 for (j = 0; j < NUMMEMWORDS; j++) {
2826                                         if (membase[j] != test[i][j]) {
2827                                                 ppcDcbf((u32)&(membase[j]));
2828                                                 break;
2829                                         }
2830                                         ppcDcbf((u32)&(membase[j]));
2831                                 }
2832                                 sync();
2833                                 if (j < NUMMEMWORDS)
2834                                         break;
2835                         }
2836
2837                         /*------------------------------------------------------------------
2838                          * See if the rffd value passed.
2839                          *-----------------------------------------------------------------*/
2840                         if (i < NUMMEMTESTS) {
2841                                 if ((end_found[dimm_num] == FALSE) &&
2842                                     (search_end[dimm_num] == TRUE)) {
2843                                         end_found[dimm_num] = TRUE;
2844                                 }
2845                                 if ((end_found[0] == TRUE) &&
2846                                     (end_found[1] == TRUE))
2847                                         break;
2848                         } else {
2849                                 if (begin_found[dimm_num] == FALSE) {
2850                                         begin_found[dimm_num] = TRUE;
2851                                         search_end[dimm_num] = TRUE;
2852                                 }
2853                         }
2854                 } else {
2855                         begin_found[dimm_num] = TRUE;
2856                         end_found[dimm_num] = TRUE;
2857                 }
2858         }
2859
2860         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2861                 window_found = TRUE;
2862
2863         /*------------------------------------------------------------------
2864          * Make sure we found the valid read passing window.  Halt if not
2865          *-----------------------------------------------------------------*/
2866         if (window_found == FALSE) {
2867                 printf("ERROR: Cannot determine a common read delay for the "
2868                        "DIMM(s) installed.\n");
2869                 spd_ddr_init_hang ();
2870         }
2871
2872         /*------------------------------------------------------------------
2873          * Restore the ECC variable to what it originally was
2874          *-----------------------------------------------------------------*/
2875         mtsdram(SDRAM_MCOPT1,
2876                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2877                 | ecc_temp);
2878 }
2879 #endif /* !HARD_CODED_DQS */
2880 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2881
2882 #else /* CONFIG_SPD_EEPROM */
2883
2884 /*-----------------------------------------------------------------------------
2885  * Function:    initdram
2886  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2887  *              The configuration is performed using static, compile-
2888  *              time parameters.
2889  *              Configures the PPC405EX(r) and PPC460EX/GT
2890  *---------------------------------------------------------------------------*/
2891 phys_size_t initdram(int board_type)
2892 {
2893         /*
2894          * Only run this SDRAM init code once. For NAND booting
2895          * targets like Kilauea, we call initdram() early from the
2896          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2897          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2898          * which calls initdram() again. This time the controller
2899          * mustn't be reconfigured again since we're already running
2900          * from SDRAM.
2901          */
2902 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2903         unsigned long val;
2904
2905 #if defined(CONFIG_440)
2906         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2907         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2908         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2909         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2910         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2911         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2912         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2913         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2914         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2915 #endif
2916
2917         /* Set Memory Bank Configuration Registers */
2918
2919         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2920         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2921         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2922         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2923
2924         /* Set Memory Clock Timing Register */
2925
2926         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2927
2928         /* Set Refresh Time Register */
2929
2930         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2931
2932         /* Set SDRAM Timing Registers */
2933
2934         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2935         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2936         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2937
2938         /* Set Mode and Extended Mode Registers */
2939
2940         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2941         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2942
2943         /* Set Memory Controller Options 1 Register */
2944
2945         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2946
2947         /* Set Manual Initialization Control Registers */
2948
2949         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2950         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2951         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2952         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2953         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2954         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2955         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2956         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2957         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2958         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2959         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2960         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2961         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2962         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2963         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2964         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2965
2966         /* Set On-Die Termination Registers */
2967
2968         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2969         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2970         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2971
2972         /* Set Write Timing Register */
2973
2974         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2975
2976         /*
2977          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2978          * SDRAM0_MCOPT2[IPTR] = 1
2979          */
2980
2981         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2982                                SDRAM_MCOPT2_IPTR_EXECUTE));
2983
2984         /*
2985          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2986          * completion of initialization.
2987          */
2988
2989         do {
2990                 mfsdram(SDRAM_MCSTAT, val);
2991         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2992
2993         /* Set Delay Control Registers */
2994
2995         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
2996
2997 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2998         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2999         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3000         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3001 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3002
3003         /*
3004          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3005          */
3006
3007         mfsdram(SDRAM_MCOPT2, val);
3008         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3009
3010 #if defined(CONFIG_440)
3011         /*
3012          * Program TLB entries with caches enabled, for best performace
3013          * while auto-calibrating and ECC generation
3014          */
3015         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3016 #endif
3017
3018 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3019 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3020         /*------------------------------------------------------------------
3021          | DQS calibration.
3022          +-----------------------------------------------------------------*/
3023         DQS_autocalibration();
3024 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3025 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3026
3027         /*
3028          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
3029          * PowerPC440SP/SPe DDR2 application note:
3030          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
3031          */
3032         update_rdcc();
3033
3034 #if defined(CONFIG_DDR_ECC)
3035         do_program_ecc(0);
3036 #endif /* defined(CONFIG_DDR_ECC) */
3037
3038 #if defined(CONFIG_440)
3039         /*
3040          * Now after initialization (auto-calibration and ECC generation)
3041          * remove the TLB entries with caches enabled and program again with
3042          * desired cache functionality
3043          */
3044         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3045         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3046 #endif
3047
3048         ppc4xx_ibm_ddr2_register_dump();
3049
3050 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3051         /*
3052          * Clear potential errors resulting from auto-calibration.
3053          * If not done, then we could get an interrupt later on when
3054          * exceptions are enabled.
3055          */
3056         set_mcsr(get_mcsr());
3057 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3058
3059 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3060
3061         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3062 }
3063 #endif /* CONFIG_SPD_EEPROM */
3064
3065 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3066 #if defined(CONFIG_440)
3067 u32 mfdcr_any(u32 dcr)
3068 {
3069         u32 val;
3070
3071         switch (dcr) {
3072         case SDRAM_R0BAS + 0:
3073                 val = mfdcr(SDRAM_R0BAS + 0);
3074                 break;
3075         case SDRAM_R0BAS + 1:
3076                 val = mfdcr(SDRAM_R0BAS + 1);
3077                 break;
3078         case SDRAM_R0BAS + 2:
3079                 val = mfdcr(SDRAM_R0BAS + 2);
3080                 break;
3081         case SDRAM_R0BAS + 3:
3082                 val = mfdcr(SDRAM_R0BAS + 3);
3083                 break;
3084         default:
3085                 printf("DCR %d not defined in case statement!!!\n", dcr);
3086                 val = 0; /* just to satisfy the compiler */
3087         }
3088
3089         return val;
3090 }
3091
3092 void mtdcr_any(u32 dcr, u32 val)
3093 {
3094         switch (dcr) {
3095         case SDRAM_R0BAS + 0:
3096                 mtdcr(SDRAM_R0BAS + 0, val);
3097                 break;
3098         case SDRAM_R0BAS + 1:
3099                 mtdcr(SDRAM_R0BAS + 1, val);
3100                 break;
3101         case SDRAM_R0BAS + 2:
3102                 mtdcr(SDRAM_R0BAS + 2, val);
3103                 break;
3104         case SDRAM_R0BAS + 3:
3105                 mtdcr(SDRAM_R0BAS + 3, val);
3106                 break;
3107         default:
3108                 printf("DCR %d not defined in case statement!!!\n", dcr);
3109         }
3110 }
3111 #endif /* defined(CONFIG_440) */
3112 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3113
3114 inline void ppc4xx_ibm_ddr2_register_dump(void)
3115 {
3116 #if defined(DEBUG)
3117         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3118
3119 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3120      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3121         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3122         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3123         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3124         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3125 #endif /* (defined(CONFIG_440SP) || ... */
3126 #if defined(CONFIG_405EX)
3127         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3128         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3129         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3130         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3131         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3132         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3133 #endif /* defined(CONFIG_405EX) */
3134         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3135         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3137         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3139         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3140         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3141         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3142         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3146 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3147      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3148         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3149         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3150         /*
3151          * OPART is only used as a trigger register.
3152          *
3153          * No data is contained in this register, and reading or writing
3154          * to is can cause bad things to happen (hangs). Just skip it and
3155          * report "N/A".
3156          */
3157         printf("%20s = N/A\n", "SDRAM_OPART");
3158 #endif /* defined(CONFIG_440SP) || ... */
3159         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3160         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3161         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3162         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3163         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3164         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3165         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3166         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3167         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3168         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3169         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3170         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3171         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3172         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3173         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3174         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3175         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3176         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3177         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3178         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3179         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3180         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3181         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3182         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3183         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3184         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3185         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3186         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3187         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3188 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3189      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3190         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3191 #endif /* defined(CONFIG_440SP) || ... */
3192         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3193         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3194         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3195 #endif /* defined(DEBUG) */
3196 }
3197
3198 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */