arch/x86/lib/pci_type1.c

   1 /*
   2  * (C) Copyright 2002
   3  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Support for type PCI configuration cycles.
  10  * based on pci_indirect.c
  11  */
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <pci.h>
  15 #include <asm/pci.h>
  16
  17 #define cfg_read(val, addr, op)         (*val = op((int)(addr)))
  18 #define cfg_write(val, addr, op)        op((val), (int)(addr))
  19
  20 #define TYPE1_PCI_OP(rw, size, type, op, mask)                          \
  21 static int                                                              \
  22 type1_##rw##_config_##size(struct pci_controller *hose,                 \
  23                               pci_dev_t dev, int offset, type val)      \
  24 {                                                                       \
  25         outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr);  \
  26         cfg_##rw(val, hose->cfg_data + (offset & mask), op);            \
  27         return 0;                                                       \
  28 }
  29
  30 TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
  31 TYPE1_PCI_OP(read, word, u16 *, inw, 2)
  32 TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
  33
  34 TYPE1_PCI_OP(write, byte, u8, outb, 3)
  35 TYPE1_PCI_OP(write, word, u16, outw, 2)
  36 TYPE1_PCI_OP(write, dword, u32, outl, 0)
  37
  38 void pci_setup_type1(struct pci_controller *hose)
  39 {
  40         pci_set_ops(hose,
  41                     type1_read_config_byte,
  42                     type1_read_config_word,
  43                     type1_read_config_dword,
  44                     type1_write_config_byte,
  45                     type1_write_config_word,
  46                     type1_write_config_dword);
  47
  48         hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
  49         hose->cfg_data = (unsigned char *)PCI_REG_DATA;
  50 }