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1 /*
2  * (C) Copyright 2003
3  * Ingo Assmus <ingo.assmus@keymile.com>
4  *
5  * based on - Driver for MV64360X ethernet ports
6  * Copyright (C) 2002 rabeeh@galileo.co.il
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26
27 /*
28  * mv_eth.h - header file for the polled mode GT ethernet driver
29  */
30
31 #ifndef __DB64360_ETH_H__
32 #define __DB64360_ETH_H__
33
34 #include <asm/types.h>
35 #include <asm/io.h>
36 #include <asm/byteorder.h>
37 #include <common.h>
38 #include <net.h>
39 #include "mv_regs.h"
40 #include <asm/errno.h>
41
42 /*************************************************************************
43 **************************************************************************
44 **************************************************************************
45 *  The first part is the high level driver of the gigE ethernet ports.   *
46 **************************************************************************
47 **************************************************************************
48 *************************************************************************/
49 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
50 #ifndef MAX_SKB_FRAGS
51 #define MAX_SKB_FRAGS 0
52 #endif
53
54 /* Port attributes */
55 /*#define MAX_RX_QUEUE_NUM      8*/
56 /*#define MAX_TX_QUEUE_NUM      8*/
57 #define MAX_RX_QUEUE_NUM        1
58 #define MAX_TX_QUEUE_NUM        1
59
60
61 /* Use one TX queue and one RX queue */
62 #define MV64360_TX_QUEUE_NUM 1
63 #define MV64360_RX_QUEUE_NUM 1
64
65 /*
66  * Number of RX / TX descriptors on RX / TX rings.
67  * Note that allocating RX descriptors is done by allocating the RX
68  * ring AND a preallocated RX buffers (skb's) for each descriptor.
69  * The TX descriptors only allocates the TX descriptors ring,
70  * with no pre allocated TX buffers (skb's are allocated by higher layers.
71  */
72
73 /* Default TX ring size is 10 descriptors */
74 #ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
75 #define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
76 #else
77 #define MV64360_TX_QUEUE_SIZE 4
78 #endif
79
80 /* Default RX ring size is 4 descriptors */
81 #ifdef  CONFIG_MV64360_ETH_RXQUEUE_SIZE
82 #define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
83 #else
84 #define MV64360_RX_QUEUE_SIZE 4
85 #endif
86
87 #ifdef CONFIG_RX_BUFFER_SIZE
88 #define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
89 #else
90 #define MV64360_RX_BUFFER_SIZE 1600
91 #endif
92
93 #ifdef CONFIG_TX_BUFFER_SIZE
94 #define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
95 #else
96 #define MV64360_TX_BUFFER_SIZE 1600
97 #endif
98
99
100 /*
101  *      Network device statistics. Akin to the 2.0 ether stats but
102  *      with byte counters.
103  */
104
105 struct net_device_stats
106 {
107         unsigned long   rx_packets;             /* total packets received       */
108         unsigned long   tx_packets;             /* total packets transmitted    */
109         unsigned long   rx_bytes;               /* total bytes received         */
110         unsigned long   tx_bytes;               /* total bytes transmitted      */
111         unsigned long   rx_errors;              /* bad packets received         */
112         unsigned long   tx_errors;              /* packet transmit problems     */
113         unsigned long   rx_dropped;             /* no space in linux buffers    */
114         unsigned long   tx_dropped;             /* no space available in linux  */
115         unsigned long   multicast;              /* multicast packets received   */
116         unsigned long   collisions;
117
118         /* detailed rx_errors: */
119         unsigned long   rx_length_errors;
120         unsigned long   rx_over_errors;         /* receiver ring buff overflow  */
121         unsigned long   rx_crc_errors;          /* recved pkt with crc error    */
122         unsigned long   rx_frame_errors;        /* recv'd frame alignment error */
123         unsigned long   rx_fifo_errors;         /* recv'r fifo overrun          */
124         unsigned long   rx_missed_errors;       /* receiver missed packet       */
125
126         /* detailed tx_errors */
127         unsigned long   tx_aborted_errors;
128         unsigned long   tx_carrier_errors;
129         unsigned long   tx_fifo_errors;
130         unsigned long   tx_heartbeat_errors;
131         unsigned long   tx_window_errors;
132
133         /* for cslip etc */
134         unsigned long   rx_compressed;
135         unsigned long   tx_compressed;
136 };
137
138
139 /* Private data structure used for ethernet device */
140 struct mv64360_eth_priv {
141     unsigned int port_num;
142     struct net_device_stats *stats;
143
144 /* to buffer area aligned */
145     char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];    /*pointers to alligned tx buffs in memory space */
146     char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];    /*pointers to allinged rx buffs in memory space */
147
148     /* Size of Tx Ring per queue */
149     unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
150
151
152     /* Size of Rx Ring per queue */
153     unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
154
155     /* Magic Number for Ethernet running */
156     unsigned int eth_running;
157
158 };
159
160
161 int mv64360_eth_init (struct eth_device *dev);
162 int mv64360_eth_stop (struct eth_device *dev);
163 int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
164 int mv64360_eth_open (struct eth_device *dev);
165
166
167 /*************************************************************************
168 **************************************************************************
169 **************************************************************************
170 *  The second part is the low level driver of the gigE ethernet ports.   *
171 **************************************************************************
172 **************************************************************************
173 *************************************************************************/
174
175
176 /********************************************************************************
177  * Header File for : MV-643xx network interface header
178  *
179  * DESCRIPTION:
180  *       This header file contains macros typedefs and function declaration for
181  *       the Marvell Gig Bit Ethernet Controller.
182  *
183  * DEPENDENCIES:
184  *       None.
185  *
186  *******************************************************************************/
187
188
189 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
190 #ifdef CONFIG_MV64360_SRAM_CACHEABLE
191 /* In case SRAM is cacheable but not cache coherent */
192 #define D_CACHE_FLUSH_LINE(addr, offset)       \
193 {                   \
194   __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
195 }
196 #else
197 /* In case SRAM is cache coherent or non-cacheable */
198 #define D_CACHE_FLUSH_LINE(addr, offset) ;
199 #endif
200 #else
201 #ifdef CONFIG_NOT_COHERENT_CACHE
202 /* In case of descriptors on DDR but not cache coherent */
203 #define D_CACHE_FLUSH_LINE(addr, offset)       \
204 {                   \
205   __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
206 }
207 #else
208 /* In case of descriptors on DDR and cache coherent */
209 #define D_CACHE_FLUSH_LINE(addr, offset) ;
210 #endif /* CONFIG_NOT_COHERENT_CACHE */
211 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
212
213
214 #define CPU_PIPE_FLUSH             \
215 {                 \
216   __asm__ __volatile__ ("eieio");         \
217 }
218
219
220 /* defines  */
221
222 /* Default port configuration value */
223 #define PORT_CONFIG_VALUE                       \
224              ETH_UNICAST_NORMAL_MODE            |   \
225              ETH_DEFAULT_RX_QUEUE_0             |   \
226              ETH_DEFAULT_RX_ARP_QUEUE_0         |   \
227              ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP    |   \
228              ETH_RECEIVE_BC_IF_IP               |   \
229              ETH_RECEIVE_BC_IF_ARP              |   \
230              ETH_CAPTURE_TCP_FRAMES_DIS         |   \
231              ETH_CAPTURE_UDP_FRAMES_DIS         |   \
232              ETH_DEFAULT_RX_TCP_QUEUE_0         |   \
233              ETH_DEFAULT_RX_UDP_QUEUE_0         |   \
234              ETH_DEFAULT_RX_BPDU_QUEUE_0
235
236 /* Default port extend configuration value */
237 #define PORT_CONFIG_EXTEND_VALUE                \
238              ETH_SPAN_BPDU_PACKETS_AS_NORMAL    |   \
239              ETH_PARTITION_DISABLE
240
241
242 /* Default sdma control value */
243 #ifdef CONFIG_NOT_COHERENT_CACHE
244 #define PORT_SDMA_CONFIG_VALUE                          \
245                          ETH_RX_BURST_SIZE_16_64BIT     |       \
246                          GT_ETH_IPG_INT_RX(0)                   |       \
247                          ETH_TX_BURST_SIZE_16_64BIT;
248 #else
249 #define PORT_SDMA_CONFIG_VALUE                  \
250                          ETH_RX_BURST_SIZE_4_64BIT      |       \
251                          GT_ETH_IPG_INT_RX(0)                   |       \
252                          ETH_TX_BURST_SIZE_4_64BIT;
253 #endif
254
255 #define GT_ETH_IPG_INT_RX(value)                \
256             ((value & 0x3fff) << 8)
257
258 /* Default port serial control value */
259 #define PORT_SERIAL_CONTROL_VALUE                           \
260                         ETH_FORCE_LINK_PASS                     |       \
261                         ETH_ENABLE_AUTO_NEG_FOR_DUPLX           |       \
262                         ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL      |       \
263                         ETH_ADV_SYMMETRIC_FLOW_CTRL             |       \
264                         ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX       |       \
265                         ETH_FORCE_BP_MODE_NO_JAM                |       \
266                         BIT9                                    |       \
267                         ETH_DO_NOT_FORCE_LINK_FAIL              |       \
268                         ETH_RETRANSMIT_16_ETTEMPTS              |       \
269                         ETH_ENABLE_AUTO_NEG_SPEED_GMII          |       \
270                         ETH_DTE_ADV_0                           |       \
271                         ETH_DISABLE_AUTO_NEG_BYPASS             |       \
272                         ETH_AUTO_NEG_NO_CHANGE                  |       \
273                         ETH_MAX_RX_PACKET_1552BYTE              |       \
274                         ETH_CLR_EXT_LOOPBACK                    |       \
275                         ETH_SET_FULL_DUPLEX_MODE                |       \
276                         ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
277
278 #define RX_BUFFER_MAX_SIZE  0xFFFF
279 #define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
280
281 #define RX_BUFFER_MIN_SIZE  0x8
282 #define TX_BUFFER_MIN_SIZE  0x8
283
284 /* Tx WRR confoguration macros */
285 #define PORT_MAX_TRAN_UNIT          0x24    /* MTU register (default) 9KByte */
286 #define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
287 #define PORT_TOKEN_RATE             1023    /* PTTBRC register (default)     */
288
289 /* MAC accepet/reject macros */
290 #define ACCEPT_MAC_ADDR     0
291 #define REJECT_MAC_ADDR     1
292
293 /* Size of a Tx/Rx descriptor used in chain list data structure */
294 #define RX_DESC_ALIGNED_SIZE            0x20
295 #define TX_DESC_ALIGNED_SIZE            0x20
296
297 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
298 #define TX_BUF_OFFSET_IN_DESC       0x18
299 /* Buffer offset from buffer pointer */
300 #define RX_BUF_OFFSET                           0x2
301
302 /* Gap define */
303 #define ETH_BAR_GAP                                     0x8
304 #define ETH_SIZE_REG_GAP                                0x8
305 #define ETH_HIGH_ADDR_REMAP_REG_GAP                     0x4
306 #define ETH_PORT_ACCESS_CTRL_GAP                        0x4
307
308 /* Gigabit Ethernet Unit Global Registers */
309
310 /* MIB Counters register definitions */
311 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
312 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
313 #define ETH_MIB_BAD_OCTETS_RECEIVED        0x8
314 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
315 #define ETH_MIB_GOOD_FRAMES_RECEIVED       0x10
316 #define ETH_MIB_BAD_FRAMES_RECEIVED        0x14
317 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
318 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
319 #define ETH_MIB_FRAMES_64_OCTETS           0x20
320 #define ETH_MIB_FRAMES_65_TO_127_OCTETS    0x24
321 #define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
322 #define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
323 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
324 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
325 #define ETH_MIB_GOOD_OCTETS_SENT_LOW       0x38
326 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH      0x3c
327 #define ETH_MIB_GOOD_FRAMES_SENT           0x40
328 #define ETH_MIB_EXCESSIVE_COLLISION        0x44
329 #define ETH_MIB_MULTICAST_FRAMES_SENT      0x48
330 #define ETH_MIB_BROADCAST_FRAMES_SENT      0x4c
331 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
332 #define ETH_MIB_FC_SENT                    0x54
333 #define ETH_MIB_GOOD_FC_RECEIVED           0x58
334 #define ETH_MIB_BAD_FC_RECEIVED            0x5c
335 #define ETH_MIB_UNDERSIZE_RECEIVED         0x60
336 #define ETH_MIB_FRAGMENTS_RECEIVED         0x64
337 #define ETH_MIB_OVERSIZE_RECEIVED          0x68
338 #define ETH_MIB_JABBER_RECEIVED            0x6c
339 #define ETH_MIB_MAC_RECEIVE_ERROR          0x70
340 #define ETH_MIB_BAD_CRC_EVENT              0x74
341 #define ETH_MIB_COLLISION                  0x78
342 #define ETH_MIB_LATE_COLLISION             0x7c
343
344 /* Port serial status reg (PSR) */
345 #define ETH_INTERFACE_GMII_MII                          0
346 #define ETH_INTERFACE_PCM                               BIT0
347 #define ETH_LINK_IS_DOWN                                0
348 #define ETH_LINK_IS_UP                                  BIT1
349 #define ETH_PORT_AT_HALF_DUPLEX                         0
350 #define ETH_PORT_AT_FULL_DUPLEX                         BIT2
351 #define ETH_RX_FLOW_CTRL_DISABLED                       0
352 #define ETH_RX_FLOW_CTRL_ENBALED                        BIT3
353 #define ETH_GMII_SPEED_100_10                           0
354 #define ETH_GMII_SPEED_1000                             BIT4
355 #define ETH_MII_SPEED_10                                0
356 #define ETH_MII_SPEED_100                               BIT5
357 #define ETH_NO_TX                                       0
358 #define ETH_TX_IN_PROGRESS                              BIT7
359 #define ETH_BYPASS_NO_ACTIVE                            0
360 #define ETH_BYPASS_ACTIVE                               BIT8
361 #define ETH_PORT_NOT_AT_PARTITION_STATE                 0
362 #define ETH_PORT_AT_PARTITION_STATE                     BIT9
363 #define ETH_PORT_TX_FIFO_NOT_EMPTY                      0
364 #define ETH_PORT_TX_FIFO_EMPTY                          BIT10
365
366
367 /* These macros describes the Port configuration reg (Px_cR) bits */
368 #define ETH_UNICAST_NORMAL_MODE                         0
369 #define ETH_UNICAST_PROMISCUOUS_MODE                    BIT0
370 #define ETH_DEFAULT_RX_QUEUE_0                          0
371 #define ETH_DEFAULT_RX_QUEUE_1                          BIT1
372 #define ETH_DEFAULT_RX_QUEUE_2                          BIT2
373 #define ETH_DEFAULT_RX_QUEUE_3                          (BIT2 | BIT1)
374 #define ETH_DEFAULT_RX_QUEUE_4                          BIT3
375 #define ETH_DEFAULT_RX_QUEUE_5                          (BIT3 | BIT1)
376 #define ETH_DEFAULT_RX_QUEUE_6                          (BIT3 | BIT2)
377 #define ETH_DEFAULT_RX_QUEUE_7                          (BIT3 | BIT2 | BIT1)
378 #define ETH_DEFAULT_RX_ARP_QUEUE_0                      0
379 #define ETH_DEFAULT_RX_ARP_QUEUE_1                      BIT4
380 #define ETH_DEFAULT_RX_ARP_QUEUE_2                      BIT5
381 #define ETH_DEFAULT_RX_ARP_QUEUE_3                      (BIT5 | BIT4)
382 #define ETH_DEFAULT_RX_ARP_QUEUE_4                      BIT6
383 #define ETH_DEFAULT_RX_ARP_QUEUE_5                      (BIT6 | BIT4)
384 #define ETH_DEFAULT_RX_ARP_QUEUE_6                      (BIT6 | BIT5)
385 #define ETH_DEFAULT_RX_ARP_QUEUE_7                      (BIT6 | BIT5 | BIT4)
386 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP                 0
387 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP                  BIT7
388 #define ETH_RECEIVE_BC_IF_IP                            0
389 #define ETH_REJECT_BC_IF_IP                             BIT8
390 #define ETH_RECEIVE_BC_IF_ARP                           0
391 #define ETH_REJECT_BC_IF_ARP                            BIT9
392 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY               BIT12
393 #define ETH_CAPTURE_TCP_FRAMES_DIS                      0
394 #define ETH_CAPTURE_TCP_FRAMES_EN                       BIT14
395 #define ETH_CAPTURE_UDP_FRAMES_DIS                      0
396 #define ETH_CAPTURE_UDP_FRAMES_EN                       BIT15
397 #define ETH_DEFAULT_RX_TCP_QUEUE_0                      0
398 #define ETH_DEFAULT_RX_TCP_QUEUE_1                      BIT16
399 #define ETH_DEFAULT_RX_TCP_QUEUE_2                      BIT17
400 #define ETH_DEFAULT_RX_TCP_QUEUE_3                      (BIT17 | BIT16)
401 #define ETH_DEFAULT_RX_TCP_QUEUE_4                      BIT18
402 #define ETH_DEFAULT_RX_TCP_QUEUE_5                      (BIT18 | BIT16)
403 #define ETH_DEFAULT_RX_TCP_QUEUE_6                      (BIT18 | BIT17)
404 #define ETH_DEFAULT_RX_TCP_QUEUE_7                      (BIT18 | BIT17 | BIT16)
405 #define ETH_DEFAULT_RX_UDP_QUEUE_0                      0
406 #define ETH_DEFAULT_RX_UDP_QUEUE_1                      BIT19
407 #define ETH_DEFAULT_RX_UDP_QUEUE_2                      BIT20
408 #define ETH_DEFAULT_RX_UDP_QUEUE_3                      (BIT20 | BIT19)
409 #define ETH_DEFAULT_RX_UDP_QUEUE_4                      (BIT21
410 #define ETH_DEFAULT_RX_UDP_QUEUE_5                      (BIT21 | BIT19)
411 #define ETH_DEFAULT_RX_UDP_QUEUE_6                      (BIT21 | BIT20)
412 #define ETH_DEFAULT_RX_UDP_QUEUE_7                      (BIT21 | BIT20 | BIT19)
413 #define ETH_DEFAULT_RX_BPDU_QUEUE_0                      0
414 #define ETH_DEFAULT_RX_BPDU_QUEUE_1                     BIT22
415 #define ETH_DEFAULT_RX_BPDU_QUEUE_2                     BIT23
416 #define ETH_DEFAULT_RX_BPDU_QUEUE_3                     (BIT23 | BIT22)
417 #define ETH_DEFAULT_RX_BPDU_QUEUE_4                     BIT24
418 #define ETH_DEFAULT_RX_BPDU_QUEUE_5                     (BIT24 | BIT22)
419 #define ETH_DEFAULT_RX_BPDU_QUEUE_6                     (BIT24 | BIT23)
420 #define ETH_DEFAULT_RX_BPDU_QUEUE_7                     (BIT24 | BIT23 | BIT22)
421
422
423 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
424 #define ETH_CLASSIFY_EN                                 BIT0
425 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL                 0
426 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7             BIT1
427 #define ETH_PARTITION_DISABLE                           0
428 #define ETH_PARTITION_ENABLE                            BIT2
429
430
431 /* Tx/Rx queue command reg (RQCR/TQCR)*/
432 #define ETH_QUEUE_0_ENABLE                              BIT0
433 #define ETH_QUEUE_1_ENABLE                              BIT1
434 #define ETH_QUEUE_2_ENABLE                              BIT2
435 #define ETH_QUEUE_3_ENABLE                              BIT3
436 #define ETH_QUEUE_4_ENABLE                              BIT4
437 #define ETH_QUEUE_5_ENABLE                              BIT5
438 #define ETH_QUEUE_6_ENABLE                              BIT6
439 #define ETH_QUEUE_7_ENABLE                              BIT7
440 #define ETH_QUEUE_0_DISABLE                             BIT8
441 #define ETH_QUEUE_1_DISABLE                             BIT9
442 #define ETH_QUEUE_2_DISABLE                             BIT10
443 #define ETH_QUEUE_3_DISABLE                             BIT11
444 #define ETH_QUEUE_4_DISABLE                             BIT12
445 #define ETH_QUEUE_5_DISABLE                             BIT13
446 #define ETH_QUEUE_6_DISABLE                             BIT14
447 #define ETH_QUEUE_7_DISABLE                             BIT15
448
449
450 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
451 #define ETH_RIFB                                        BIT0
452 #define ETH_RX_BURST_SIZE_1_64BIT                       0
453 #define ETH_RX_BURST_SIZE_2_64BIT                       BIT1
454 #define ETH_RX_BURST_SIZE_4_64BIT                       BIT2
455 #define ETH_RX_BURST_SIZE_8_64BIT                       (BIT2 | BIT1)
456 #define ETH_RX_BURST_SIZE_16_64BIT                      BIT3
457 #define ETH_BLM_RX_NO_SWAP                              BIT4
458 #define ETH_BLM_RX_BYTE_SWAP                            0
459 #define ETH_BLM_TX_NO_SWAP                              BIT5
460 #define ETH_BLM_TX_BYTE_SWAP                            0
461 #define ETH_DESCRIPTORS_BYTE_SWAP                       BIT6
462 #define ETH_DESCRIPTORS_NO_SWAP                         0
463 #define ETH_TX_BURST_SIZE_1_64BIT                       0
464 #define ETH_TX_BURST_SIZE_2_64BIT                       BIT22
465 #define ETH_TX_BURST_SIZE_4_64BIT                       BIT23
466 #define ETH_TX_BURST_SIZE_8_64BIT                       (BIT23 | BIT22)
467 #define ETH_TX_BURST_SIZE_16_64BIT                      BIT24
468
469
470 /* These macros describes the Port serial control reg (PSCR) bits */
471 #define ETH_SERIAL_PORT_DISABLE                         0
472 #define ETH_SERIAL_PORT_ENABLE                          BIT0
473 #define ETH_FORCE_LINK_PASS                             BIT1
474 #define ETH_DO_NOT_FORCE_LINK_PASS                      0
475 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX                   0
476 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX                  BIT2
477 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL               0
478 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL              BIT3
479 #define ETH_ADV_NO_FLOW_CTRL                            0
480 #define ETH_ADV_SYMMETRIC_FLOW_CTRL                     BIT4
481 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX               0
482 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS                  BIT5
483 #define ETH_FORCE_BP_MODE_NO_JAM                        0
484 #define ETH_FORCE_BP_MODE_JAM_TX                        BIT7
485 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR              BIT8
486 #define ETH_FORCE_LINK_FAIL                             0
487 #define ETH_DO_NOT_FORCE_LINK_FAIL                      BIT10
488 #define ETH_RETRANSMIT_16_ETTEMPTS                      0
489 #define ETH_RETRANSMIT_FOREVER                          BIT11
490 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII                 BIT13
491 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII                  0
492 #define ETH_DTE_ADV_0                                   0
493 #define ETH_DTE_ADV_1                                   BIT14
494 #define ETH_DISABLE_AUTO_NEG_BYPASS                     0
495 #define ETH_ENABLE_AUTO_NEG_BYPASS                      BIT15
496 #define ETH_AUTO_NEG_NO_CHANGE                          0
497 #define ETH_RESTART_AUTO_NEG                            BIT16
498 #define ETH_MAX_RX_PACKET_1518BYTE                      0
499 #define ETH_MAX_RX_PACKET_1522BYTE                      BIT17
500 #define ETH_MAX_RX_PACKET_1552BYTE                      BIT18
501 #define ETH_MAX_RX_PACKET_9022BYTE                      (BIT18 | BIT17)
502 #define ETH_MAX_RX_PACKET_9192BYTE                      BIT19
503 #define ETH_MAX_RX_PACKET_9700BYTE                      (BIT19 | BIT17)
504 #define ETH_SET_EXT_LOOPBACK                            BIT20
505 #define ETH_CLR_EXT_LOOPBACK                            0
506 #define ETH_SET_FULL_DUPLEX_MODE                        BIT21
507 #define ETH_SET_HALF_DUPLEX_MODE                        0
508 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX       BIT22
509 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX      0
510 #define ETH_SET_GMII_SPEED_TO_10_100                    0
511 #define ETH_SET_GMII_SPEED_TO_1000                      BIT23
512 #define ETH_SET_MII_SPEED_TO_10                         0
513 #define ETH_SET_MII_SPEED_TO_100                        BIT24
514
515
516 /* SMI reg */
517 #define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
518 #define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
519 #define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
520 #define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress             */
521
522 /* SDMA command status fields macros */
523
524 /* Tx & Rx descriptors status */
525 #define ETH_ERROR_SUMMARY                   (BIT0)
526
527 /* Tx & Rx descriptors command */
528 #define ETH_BUFFER_OWNED_BY_DMA             (BIT31)
529
530 /* Tx descriptors status */
531 #define ETH_LC_ERROR                        (0    )
532 #define ETH_UR_ERROR                        (BIT1 )
533 #define ETH_RL_ERROR                        (BIT2 )
534 #define ETH_LLC_SNAP_FORMAT                 (BIT9 )
535
536 /* Rx descriptors status */
537 #define ETH_CRC_ERROR                       (0    )
538 #define ETH_OVERRUN_ERROR                   (BIT1 )
539 #define ETH_MAX_FRAME_LENGTH_ERROR          (BIT2 )
540 #define ETH_RESOURCE_ERROR                  ((BIT2 | BIT1))
541 #define ETH_VLAN_TAGGED                     (BIT19)
542 #define ETH_BPDU_FRAME                      (BIT20)
543 #define ETH_TCP_FRAME_OVER_IP_V_4           (0    )
544 #define ETH_UDP_FRAME_OVER_IP_V_4           (BIT21)
545 #define ETH_OTHER_FRAME_TYPE                (BIT22)
546 #define ETH_LAYER_2_IS_ETH_V_2              (BIT23)
547 #define ETH_FRAME_TYPE_IP_V_4               (BIT24)
548 #define ETH_FRAME_HEADER_OK                 (BIT25)
549 #define ETH_RX_LAST_DESC                    (BIT26)
550 #define ETH_RX_FIRST_DESC                   (BIT27)
551 #define ETH_UNKNOWN_DESTINATION_ADDR        (BIT28)
552 #define ETH_RX_ENABLE_INTERRUPT             (BIT29)
553 #define ETH_LAYER_4_CHECKSUM_OK             (BIT30)
554
555 /* Rx descriptors byte count */
556 #define ETH_FRAME_FRAGMENTED                (BIT2)
557
558 /* Tx descriptors command */
559 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
560 #define ETH_FRAME_SET_TO_VLAN               (BIT15)
561 #define ETH_TCP_FRAME                       (0    )
562 #define ETH_UDP_FRAME                       (BIT16)
563 #define ETH_GEN_TCP_UDP_CHECKSUM            (BIT17)
564 #define ETH_GEN_IP_V_4_CHECKSUM             (BIT18)
565 #define ETH_ZERO_PADDING                    (BIT19)
566 #define ETH_TX_LAST_DESC                    (BIT20)
567 #define ETH_TX_FIRST_DESC                   (BIT21)
568 #define ETH_GEN_CRC                         (BIT22)
569 #define ETH_TX_ENABLE_INTERRUPT             (BIT23)
570 #define ETH_AUTO_MODE                       (BIT30)
571
572 /* Address decode parameters */
573 /* Ethernet Base Address Register bits */
574 #define EBAR_TARGET_DRAM                                        0x00000000
575 #define EBAR_TARGET_DEVICE                                      0x00000001
576 #define EBAR_TARGET_CBS                                         0x00000002
577 #define EBAR_TARGET_PCI0                                        0x00000003
578 #define EBAR_TARGET_PCI1                                        0x00000004
579 #define EBAR_TARGET_CUNIT                                       0x00000005
580 #define EBAR_TARGET_AUNIT                                       0x00000006
581 #define EBAR_TARGET_GUNIT                                       0x00000007
582
583 /* Window attributes */
584 #define EBAR_ATTR_DRAM_CS0                                      0x00000E00
585 #define EBAR_ATTR_DRAM_CS1                                      0x00000D00
586 #define EBAR_ATTR_DRAM_CS2                                      0x00000B00
587 #define EBAR_ATTR_DRAM_CS3                                      0x00000700
588
589 /* DRAM Target interface */
590 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY       0x00000000
591 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT       0x00001000
592 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB       0x00002000
593
594 /* Device Bus Target interface */
595 #define EBAR_ATTR_DEVICE_DEVCS0                         0x00001E00
596 #define EBAR_ATTR_DEVICE_DEVCS1                         0x00001D00
597 #define EBAR_ATTR_DEVICE_DEVCS2                         0x00001B00
598 #define EBAR_ATTR_DEVICE_DEVCS3                         0x00001700
599 #define EBAR_ATTR_DEVICE_BOOTCS3                        0x00000F00
600
601 /* PCI Target interface */
602 #define EBAR_ATTR_PCI_BYTE_SWAP                         0x00000000
603 #define EBAR_ATTR_PCI_NO_SWAP                           0x00000100
604 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP            0x00000200
605 #define EBAR_ATTR_PCI_WORD_SWAP                         0x00000300
606 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT       0x00000000
607 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT           0x00000400
608 #define EBAR_ATTR_PCI_IO_SPACE                          0x00000000
609 #define EBAR_ATTR_PCI_MEMORY_SPACE                      0x00000800
610 #define EBAR_ATTR_PCI_REQ64_FORCE                       0x00000000
611 #define EBAR_ATTR_PCI_REQ64_SIZE                        0x00001000
612
613 /* CPU 60x bus or internal SRAM interface */
614 #define EBAR_ATTR_CBS_SRAM_BLOCK0                       0x00000000
615 #define EBAR_ATTR_CBS_SRAM_BLOCK1                       0x00000100
616 #define EBAR_ATTR_CBS_SRAM                                      0x00000000
617 #define EBAR_ATTR_CBS_CPU_BUS                           0x00000800
618
619 /* Window access control */
620 #define EWIN_ACCESS_NOT_ALLOWED 0
621 #define EWIN_ACCESS_READ_ONLY   BIT0
622 #define EWIN_ACCESS_FULL        (BIT1 | BIT0)
623 #define EWIN0_ACCESS_MASK               0x0003
624 #define EWIN1_ACCESS_MASK               0x000C
625 #define EWIN2_ACCESS_MASK               0x0030
626 #define EWIN3_ACCESS_MASK               0x00C0
627
628 /* typedefs */
629
630 typedef enum _eth_port
631 {
632     ETH_0 = 0,
633         ETH_1 = 1,
634         ETH_2 = 2
635 }ETH_PORT;
636
637 typedef enum _eth_func_ret_status
638 {
639     ETH_OK,                     /* Returned as expected.                    */
640     ETH_ERROR,                  /* Fundamental error.                       */
641     ETH_RETRY,                  /* Could not process request. Try later.    */
642     ETH_END_OF_JOB,             /* Ring has nothing to process.             */
643     ETH_QUEUE_FULL,             /* Ring resource error.                     */
644     ETH_QUEUE_LAST_RESOURCE     /* Ring resources about to exhaust.         */
645 }ETH_FUNC_RET_STATUS;
646
647 typedef enum _eth_queue
648 {
649         ETH_Q0 = 0,
650         ETH_Q1 = 1,
651         ETH_Q2 = 2,
652         ETH_Q3 = 3,
653         ETH_Q4 = 4,
654         ETH_Q5 = 5,
655         ETH_Q6 = 6,
656     ETH_Q7 = 7
657 } ETH_QUEUE;
658
659 typedef enum _addr_win
660 {
661         ETH_WIN0,
662         ETH_WIN1,
663         ETH_WIN2,
664         ETH_WIN3,
665         ETH_WIN4,
666     ETH_WIN5
667 } ETH_ADDR_WIN;
668
669 typedef enum _eth_target
670 {
671         ETH_TARGET_DRAM  ,
672         ETH_TARGET_DEVICE,
673         ETH_TARGET_CBS   ,
674         ETH_TARGET_PCI0  ,
675         ETH_TARGET_PCI1
676 }ETH_TARGET;
677
678 typedef struct _eth_rx_desc
679 {
680         unsigned short  byte_cnt           ;    /* Descriptor buffer byte count     */
681         unsigned short  buf_size           ;    /* Buffer size                      */
682         unsigned int    cmd_sts    ;    /* Descriptor command status        */
683         unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
684         unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
685     unsigned int    return_info ;    /* User resource return information */
686 } ETH_RX_DESC;
687
688
689 typedef struct _eth_tx_desc
690 {
691     unsigned short  byte_cnt       ;    /* Descriptor buffer byte count     */
692     unsigned short  l4i_chk        ;    /* CPU provided TCP Checksum        */
693     unsigned int    cmd_sts        ;    /* Descriptor command status        */
694     unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
695     unsigned int    buf_ptr        ;    /* Descriptor buffer pointer        */
696     unsigned int    return_info ;    /* User resource return information */
697 } ETH_TX_DESC;
698
699 /* Unified struct for Rx and Tx operations. The user is not required to */
700 /* be familier with neither Tx nor Rx descriptors.                       */
701 typedef struct _pkt_info
702 {
703         unsigned short  byte_cnt   ;    /* Descriptor buffer byte count     */
704         unsigned short  l4i_chk    ;    /* Tx CPU provided TCP Checksum     */
705         unsigned int    cmd_sts    ;    /* Descriptor command status        */
706         unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
707     unsigned int    return_info ;    /* User resource return information */
708 } PKT_INFO;
709
710
711 typedef struct _eth_win_param
712 {
713     ETH_ADDR_WIN win;   /* Window number. See ETH_ADDR_WIN enum */
714     ETH_TARGET  target;    /* System targets. See ETH_TARGET enum */
715     unsigned short attributes;  /* BAR attributes. See above macros. */
716     unsigned int base_addr; /* Window base address in unsigned int form */
717     unsigned int high_addr; /* Window high address in unsigned int form */
718     unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
719     bool enable; /* Enable/disable access to the window. */
720     unsigned short access_ctrl; /* Access ctrl register. see above macros */
721 } ETH_WIN_PARAM;
722
723
724 /* Ethernet port specific infomation */
725
726 typedef struct _eth_port_ctrl
727 {
728     ETH_PORT  port_num; /* User Ethernet port number */
729     int port_phy_addr;  /* User phy address of Ethrnet port */
730     unsigned char port_mac_addr[6]; /* User defined port MAC address. */
731     unsigned int  port_config; /* User port configuration value */
732     unsigned int  port_config_extend; /* User port config extend value */
733     unsigned int  port_sdma_config; /* User port SDMA config value */
734     unsigned int  port_serial_control; /* User port serial control value */
735     unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
736     unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
737
738     /* User function to cast virtual address to CPU bus address */
739     unsigned int  (*port_virt_to_phys)(unsigned int addr);
740     /* User scratch pad for user specific data structures */
741     void *port_private;
742
743     bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
744     bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
745
746     /* Tx/Rx rings managment indexes fields. For driver use */
747
748     /* Next available Rx resource */
749     volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
750     /* Returning Rx resource */
751     volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
752
753     /* Next available Tx resource */
754     volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
755     /* Returning Tx resource */
756     volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
757     /* An extra Tx index to support transmit of multiple buffers per packet */
758     volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
759
760     /* Tx/Rx rings size and base variables fields. For driver use */
761
762     volatile ETH_RX_DESC        *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
763     unsigned int                 rx_desc_area_size[MAX_RX_QUEUE_NUM];
764     char                        *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
765
766     volatile ETH_TX_DESC        *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
767     unsigned int                 tx_desc_area_size[MAX_TX_QUEUE_NUM];
768     char                        *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
769
770 } ETH_PORT_INFO;
771
772
773 /* ethernet.h API list */
774
775 /* Port operation control routines */
776 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
777 static void eth_port_reset(ETH_PORT     eth_port_num);
778 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
779
780
781 /* Port MAC address routines */
782 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
783                                   unsigned char *p_addr,
784                                   ETH_QUEUE queue);
785 #if 0   /* FIXME */
786 static void eth_port_mc_addr    (ETH_PORT eth_port_num,
787                                  unsigned char *p_addr,
788                                  ETH_QUEUE queue,
789                                  int option);
790 #endif
791
792 /* PHY and MIB routines */
793 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
794
795 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
796                                    unsigned int phy_reg,
797                                    unsigned int value);
798
799 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
800                                   unsigned int phy_reg,
801                                   unsigned int* value);
802
803 static void eth_clear_mib_counters(ETH_PORT     eth_port_num);
804
805 /* Port data flow control routines */
806 static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
807                                              ETH_QUEUE tx_queue,
808                                              PKT_INFO *p_pkt_info);
809 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
810                                               ETH_QUEUE tx_queue,
811                                               PKT_INFO *p_pkt_info);
812 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
813                                              ETH_QUEUE rx_queue,
814                                              PKT_INFO *p_pkt_info);
815 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
816                                               ETH_QUEUE rx_queue,
817                                               PKT_INFO *p_pkt_info);
818
819
820 static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
821                                     ETH_QUEUE   tx_queue,
822                                     int                         tx_desc_num,
823                                     int                         tx_buff_size,
824                                     unsigned int        tx_desc_base_addr,
825                                     unsigned int        tx_buff_base_addr);
826
827 static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
828                                     ETH_QUEUE   rx_queue,
829                                     int                         rx_desc_num,
830                                     int                         rx_buff_size,
831                                     unsigned int        rx_desc_base_addr,
832                                     unsigned int        rx_buff_base_addr);
833
834 #endif /* MV64360_ETH_ */