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ddr: altera: sdram: Make sdram_start and sdram_end into u32
[karo-tx-uboot.git] / board / altera / socfpga / qts / sequencer_auto_ac_init.h
1 /*
2  * Copyright Altera Corporation (C) 2012-2015
3  *
4  * SPDX-License-Identifier:    BSD-3-Clause
5  */
6
7 const uint32_t ac_rom_init[] = {
8 #ifdef CONFIG_SOCFPGA_ARRIA5
9 /* The if..else... is not required if generated by tools */
10         0x20700000,
11         0x20780000,
12         0x10080831,
13         0x10080930,
14         0x10090004,
15         0x100a0008,
16         0x100b0000,
17         0x10380400,
18         0x10080849,
19         0x100808c8,
20         0x100a0004,
21         0x10090010,
22         0x100b0000,
23         0x30780000,
24         0x38780000,
25         0x30780000,
26         0x10680000,
27         0x106b0000,
28         0x10280400,
29         0x10480000,
30         0x1c980000,
31         0x1c9b0000,
32         0x1c980008,
33         0x1c9b0008,
34         0x38f80000,
35         0x3cf80000,
36         0x38780000,
37         0x18180000,
38         0x18980000,
39         0x13580000,
40         0x135b0000,
41         0x13580008,
42         0x135b0008,
43         0x33780000,
44         0x10580008,
45         0x10780000
46 #else
47         0x20700000,
48         0x20780000,
49         0x10080431,
50         0x10080530,
51         0x10090004,
52         0x100a0008,
53         0x100b0000,
54         0x10380400,
55         0x10080449,
56         0x100804c8,
57         0x100a0004,
58         0x10090010,
59         0x100b0000,
60         0x30780000,
61         0x38780000,
62         0x30780000,
63         0x10680000,
64         0x106b0000,
65         0x10280400,
66         0x10480000,
67         0x1c980000,
68         0x1c9b0000,
69         0x1c980008,
70         0x1c9b0008,
71         0x38f80000,
72         0x3cf80000,
73         0x38780000,
74         0x18180000,
75         0x18980000,
76         0x13580000,
77         0x135b0000,
78         0x13580008,
79         0x135b0008,
80         0x33780000,
81         0x10580008,
82         0x10780000
83 #endif /* CONFIG_SOCFPGA_ARRIA5 */
84 };