board/altera/socfpga/wrap_sdram_config.c

   1 /*
   2  * Copyright (C) 2015 Marek Vasut <marex@denx.de>
   3  *
   4  * SPDX-License-Identifier:    GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <asm/arch/sdram.h>
  10 /* QTS output file. */
  11 #include "qts/sdram_config.h"
  12
  13 static const struct socfpga_sdram_config sdram_config = {
  14         .ctrl_cfg =
  15                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
  16                         SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)                |
  17                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
  18                         SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)                  |
  19                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
  20                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)              |
  21                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
  22                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)                  |
  23                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
  24                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)              |
  25                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
  26                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)              |
  27                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
  28                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)            |
  29                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
  30                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)               |
  31                 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
  32                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
  33         .dram_timing1 =
  34                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
  35                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)               |
  36                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
  37                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)                |
  38                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
  39                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)                |
  40                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
  41                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)               |
  42                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
  43                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)               |
  44                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
  45                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
  46         .dram_timing2 =
  47                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
  48                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)              |
  49                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
  50                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)               |
  51                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
  52                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)                |
  53                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
  54                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)                |
  55                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
  56                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
  57         .dram_timing3 =
  58                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
  59                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)               |
  60                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
  61                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)               |
  62                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
  63                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)                |
  64                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
  65                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)               |
  66                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
  67                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
  68         .dram_timing4 =
  69                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
  70                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
  71                 (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
  72                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
  73         .lowpwr_timing =
  74                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
  75                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
  76                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
  77                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
  78         .dram_odt =
  79                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
  80                         SDR_CTRLGRP_DRAMODT_READ_LSB)                   |
  81                 (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
  82                         SDR_CTRLGRP_DRAMODT_WRITE_LSB),
  83         .dram_addrw =
  84                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
  85                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)              |
  86                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
  87                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)              |
  88                 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
  89                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)             |
  90                 ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
  91                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
  92         .dram_if_width =
  93                 (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
  94                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
  95         .dram_dev_width =
  96                 (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
  97                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
  98         .dram_intr =
  99                 (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 100                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
 101         .lowpwr_eq =
 102                 (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 103                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
 104         .static_cfg =
 105                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 106                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB)                |
 107                 (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 108                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
 109         .ctrl_width =
 110                 (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 111                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
 112         .cport_width =
 113                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 114                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
 115         .cport_wmap =
 116                 (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 117                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
 118         .cport_rmap =
 119                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 120                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
 121         .rfifo_cmap =
 122                 (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 123                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
 124         .wfifo_cmap =
 125                 (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 126                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
 127         .cport_rdwr =
 128                 (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 129                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
 130         .port_cfg =
 131                 (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 132                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
 133         .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 134         .fifo_cfg =
 135                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 136                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)               |
 137                 (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 138                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
 139         .mp_priority =
 140                 (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 141                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
 142         .mp_weight0 =
 143                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 144                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
 145         .mp_weight1 =
 146                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 147                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
 148                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 149                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
 150         .mp_weight2 =
 151                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 152                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
 153         .mp_weight3 =
 154                 (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 155                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
 156         .mp_pacing0 =
 157                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 158                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
 159         .mp_pacing1 =
 160                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 161                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
 162                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 163                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
 164         .mp_pacing2 =
 165                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 166                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
 167         .mp_pacing3 =
 168                 (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 169                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
 170         .mp_threshold0 =
 171                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 172                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
 173         .mp_threshold1 =
 174                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
 175                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
 176         .mp_threshold2 =
 177                 (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 178                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
 179         .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
 180 };
 181
 182 const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
 183 {
 184         return &sdram_config;
 185 }