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rename CFG_ macros to CONFIG_SYS
[karo-tx-uboot.git] / board / amcc / ocotea / ocotea.c
1 /*
2  *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
3  *
4  * (C) Copyright 2005
5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26
27 #include <common.h>
28 #include "ocotea.h"
29 #include <asm/processor.h>
30 #include <spd_sdram.h>
31 #include <ppc4xx_enet.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define BOOT_SMALL_FLASH        32      /* 00100000 */
36 #define FLASH_ONBD_N            2       /* 00000010 */
37 #define FLASH_SRAM_SEL          1       /* 00000001 */
38
39 long int fixed_sdram (void);
40 void fpga_init (void);
41
42 int board_early_init_f (void)
43 {
44         unsigned long mfr;
45         unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
46         unsigned char switch_status;
47         unsigned long cs0_base;
48         unsigned long cs0_size;
49         unsigned long cs0_twt;
50         unsigned long cs2_base;
51         unsigned long cs2_size;
52         unsigned long cs2_twt;
53
54         /*-------------------------------------------------------------------------+
55           | Initialize EBC CONFIG
56           +-------------------------------------------------------------------------*/
57         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
58               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
59               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
60               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
61               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
62
63         /*-------------------------------------------------------------------------+
64           | FPGA. Initialize bank 7 with default values.
65           +-------------------------------------------------------------------------*/
66         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
67               EBC_BXAP_BCE_DISABLE|
68               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
69               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
70               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
71               EBC_BXAP_BEM_WRITEONLY|
72               EBC_BXAP_PEN_DISABLED);
73         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
74               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
75
76         /* read FPGA base register FPGA_REG0 */
77         switch_status = *fpga_base;
78
79         if (switch_status & 0x40) {
80                 cs0_base = 0xFFE00000;
81                 cs0_size = EBC_BXCR_BS_2MB;
82                 cs0_twt = 8;
83                 cs2_base = 0xFF800000;
84                 cs2_size = EBC_BXCR_BS_4MB;
85                 cs2_twt = 10;
86         } else {
87                 cs0_base = 0xFFC00000;
88                 cs0_size = EBC_BXCR_BS_4MB;
89                 cs0_twt = 10;
90                 cs2_base = 0xFF800000;
91                 cs2_size = EBC_BXCR_BS_2MB;
92                 cs2_twt = 8;
93         }
94
95         /*-------------------------------------------------------------------------+
96           | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
97           +-------------------------------------------------------------------------*/
98         mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
99               EBC_BXAP_BCE_DISABLE|
100               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
101               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
102               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
103               EBC_BXAP_BEM_WRITEONLY|
104               EBC_BXAP_PEN_DISABLED);
105         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
106               cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
107
108         /*-------------------------------------------------------------------------+
109           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
110           +-------------------------------------------------------------------------*/
111         mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
112               EBC_BXAP_BCE_DISABLE|
113               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
114               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
115               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
116               EBC_BXAP_BEM_WRITEONLY|
117               EBC_BXAP_PEN_DISABLED);
118         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
119               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
120
121         /*-------------------------------------------------------------------------+
122           | 4 MB FLASH. Initialize bank 2 with default values.
123           +-------------------------------------------------------------------------*/
124         mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
125               EBC_BXAP_BCE_DISABLE|
126               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
127               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
128               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
129               EBC_BXAP_BEM_WRITEONLY|
130               EBC_BXAP_PEN_DISABLED);
131         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
132               cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
133
134         /*-------------------------------------------------------------------------+
135           | FPGA. Initialize bank 7 with default values.
136           +-------------------------------------------------------------------------*/
137         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
138               EBC_BXAP_BCE_DISABLE|
139               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
140               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
141               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
142               EBC_BXAP_BEM_WRITEONLY|
143               EBC_BXAP_PEN_DISABLED);
144         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
145               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
146
147         /*--------------------------------------------------------------------
148          * Setup the interrupt controller polarities, triggers, etc.
149          *-------------------------------------------------------------------*/
150         /*
151          * Because of the interrupt handling rework to handle 440GX interrupts
152          * with the common code, we needed to change names of the UIC registers.
153          * Here the new relationship:
154          *
155          * U-Boot name  440GX name
156          * -----------------------
157          * UIC0         UICB0
158          * UIC1         UIC0
159          * UIC2         UIC1
160          * UIC3         UIC2
161          */
162         mtdcr (uic1sr, 0xffffffff);     /* clear all */
163         mtdcr (uic1er, 0x00000000);     /* disable all */
164         mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
165         mtdcr (uic1pr, 0xfffffe13);     /* per ref-board manual */
166         mtdcr (uic1tr, 0x01c00008);     /* per ref-board manual */
167         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
168         mtdcr (uic1sr, 0xffffffff);     /* clear all */
169
170         mtdcr (uic2sr, 0xffffffff);     /* clear all */
171         mtdcr (uic2er, 0x00000000);     /* disable all */
172         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
173         mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
174         mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
175         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
176         mtdcr (uic2sr, 0xffffffff);     /* clear all */
177
178         mtdcr (uic3sr, 0xffffffff);     /* clear all */
179         mtdcr (uic3er, 0x00000000);     /* disable all */
180         mtdcr (uic3cr, 0x00000000);     /* all non-critical */
181         mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
182         mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
183         mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
184         mtdcr (uic3sr, 0xffffffff);     /* clear all */
185
186         mtdcr (uic0sr, 0xfc000000); /* clear all */
187         mtdcr (uic0er, 0x00000000); /* disable all */
188         mtdcr (uic0cr, 0x00000000); /* all non-critical */
189         mtdcr (uic0pr, 0xfc000000); /* */
190         mtdcr (uic0tr, 0x00000000); /* */
191         mtdcr (uic0vr, 0x00000001); /* */
192         mfsdr (sdr_mfr, mfr);
193         mfr &= ~SDR0_MFR_ECS_MASK;
194 /*      mtsdr(sdr_mfr, mfr); */
195         fpga_init();
196
197         return 0;
198 }
199
200
201 int checkboard (void)
202 {
203         char *s = getenv ("serial#");
204
205         printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
206         if (s != NULL) {
207                 puts (", serial# ");
208                 puts (s);
209         }
210         putc ('\n');
211
212         return (0);
213 }
214
215
216 phys_size_t initdram (int board_type)
217 {
218         long dram_size = 0;
219
220 #if defined(CONFIG_SPD_EEPROM)
221         dram_size = spd_sdram ();
222 #else
223         dram_size = fixed_sdram ();
224 #endif
225         return dram_size;
226 }
227
228
229 #if !defined(CONFIG_SPD_EEPROM)
230 /*************************************************************************
231  *  fixed sdram init -- doesn't use serial presence detect.
232  *
233  *  Assumes:    128 MB, non-ECC, non-registered
234  *              PLB @ 133 MHz
235  *
236  ************************************************************************/
237 long int fixed_sdram (void)
238 {
239         uint reg;
240
241         /*--------------------------------------------------------------------
242          * Setup some default
243          *------------------------------------------------------------------*/
244         mtsdram (mem_uabba, 0x00000000);        /* ubba=0 (default)             */
245         mtsdram (mem_slio, 0x00000000);         /* rdre=0 wrre=0 rarw=0         */
246         mtsdram (mem_devopt, 0x00000000);       /* dll=0 ds=0 (normal)          */
247         mtsdram (mem_wddctr, 0x00000000);       /* wrcp=0 dcd=0                 */
248         mtsdram (mem_clktr, 0x40000000);        /* clkp=1 (90 deg wr) dcdt=0    */
249
250         /*--------------------------------------------------------------------
251          * Setup for board-specific specific mem
252          *------------------------------------------------------------------*/
253         /*
254          * Following for CAS Latency = 2.5 @ 133 MHz PLB
255          */
256         mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
257         mtsdram (mem_tr0, 0x410a4012);  /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
258         /* RA=10 RD=3                       */
259         mtsdram (mem_tr1, 0x8080082f);  /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
260         mtsdram (mem_rtr, 0x08200000);  /* Rate 15.625 ns @ 133 MHz PLB     */
261         mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
262         udelay (400);                   /* Delay 200 usecs (min)            */
263
264         /*--------------------------------------------------------------------
265          * Enable the controller, then wait for DCEN to complete
266          *------------------------------------------------------------------*/
267         mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit           */
268         for (;;) {
269                 mfsdram (mem_mcsts, reg);
270                 if (reg & 0x80000000)
271                         break;
272         }
273
274         return (128 * 1024 * 1024);     /* 128 MB                           */
275 }
276 #endif  /* !defined(CONFIG_SPD_EEPROM) */
277
278
279 /*************************************************************************
280  *  pci_pre_init
281  *
282  *  This routine is called just prior to registering the hose and gives
283  *  the board the opportunity to check things. Returning a value of zero
284  *  indicates that things are bad & PCI initialization should be aborted.
285  *
286  *      Different boards may wish to customize the pci controller structure
287  *      (add regions, override default access routines, etc) or perform
288  *      certain pre-initialization actions.
289  *
290  ************************************************************************/
291 #if defined(CONFIG_PCI)
292 int pci_pre_init(struct pci_controller * hose )
293 {
294         unsigned long strap;
295
296         /*--------------------------------------------------------------------------+
297          *      The ocotea board is always configured as the host & requires the
298          *      PCI arbiter to be enabled.
299          *--------------------------------------------------------------------------*/
300         mfsdr(sdr_sdstp1, strap);
301         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
302                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
303                 return 0;
304         }
305
306         return 1;
307 }
308 #endif /* defined(CONFIG_PCI) */
309
310 /*************************************************************************
311  *  pci_target_init
312  *
313  *      The bootstrap configuration provides default settings for the pci
314  *      inbound map (PIM). But the bootstrap config choices are limited and
315  *      may not be sufficient for a given board.
316  *
317  ************************************************************************/
318 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
319 void pci_target_init(struct pci_controller * hose )
320 {
321         /*--------------------------------------------------------------------------+
322          * Disable everything
323          *--------------------------------------------------------------------------*/
324         out32r( PCIX0_PIM0SA, 0 ); /* disable */
325         out32r( PCIX0_PIM1SA, 0 ); /* disable */
326         out32r( PCIX0_PIM2SA, 0 ); /* disable */
327         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
328
329         /*--------------------------------------------------------------------------+
330          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
331          * options to not support sizes such as 128/256 MB.
332          *--------------------------------------------------------------------------*/
333         out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
334         out32r( PCIX0_PIM0LAH, 0 );
335         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
336
337         out32r( PCIX0_BAR0, 0 );
338
339         /*--------------------------------------------------------------------------+
340          * Program the board's subsystem id/vendor id
341          *--------------------------------------------------------------------------*/
342         out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
343         out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
344
345         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
346 }
347 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
348
349
350 /*************************************************************************
351  *  is_pci_host
352  *
353  *      This routine is called to determine if a pci scan should be
354  *      performed. With various hardware environments (especially cPCI and
355  *      PPMC) it's insufficient to depend on the state of the arbiter enable
356  *      bit in the strap register, or generic host/adapter assumptions.
357  *
358  *      Rather than hard-code a bad assumption in the general 440 code, the
359  *      440 pci code requires the board to decide at runtime.
360  *
361  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
362  *
363  *
364  ************************************************************************/
365 #if defined(CONFIG_PCI)
366 int is_pci_host(struct pci_controller *hose)
367 {
368     /* The ocotea board is always configured as host. */
369     return(1);
370 }
371 #endif /* defined(CONFIG_PCI) */
372
373
374 void fpga_init(void)
375 {
376         unsigned long group;
377         unsigned long sdr0_pfc0;
378         unsigned long sdr0_pfc1;
379         unsigned long sdr0_cust0;
380         unsigned long pvr;
381
382         mfsdr (sdr_pfc0, sdr0_pfc0);
383         mfsdr (sdr_pfc1, sdr0_pfc1);
384         group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
385         pvr = get_pvr ();
386
387         sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
388         if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
389                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
390                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
391                 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
392                      FPGA_REG2_EXT_INTFACE_ENABLE);
393                 mtsdr (sdr_pfc0, sdr0_pfc0);
394                 mtsdr (sdr_pfc1, sdr0_pfc1);
395         } else {
396                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
397                 switch (group)
398                 {
399                 case 0:
400                 case 1:
401                 case 2:
402                         /* CPU trace A */
403                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
404                              FPGA_REG2_EXT_INTFACE_ENABLE);
405                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
406                         mtsdr (sdr_pfc0, sdr0_pfc0);
407                         mtsdr (sdr_pfc1, sdr0_pfc1);
408                         break;
409                 case 3:
410                 case 4:
411                 case 5:
412                 case 6:
413                         /* CPU trace B - Over EBMI */
414                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
415                         mtsdr (sdr_pfc0, sdr0_pfc0);
416                         mtsdr (sdr_pfc1, sdr0_pfc1);
417                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
418                              FPGA_REG2_EXT_INTFACE_DISABLE);
419                         break;
420                 }
421         }
422
423         /* Initialize the ethernet specific functions in the fpga */
424         mfsdr(sdr_pfc1, sdr0_pfc1);
425         mfsdr(sdr_cust0, sdr0_cust0);
426         if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
427             ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
428              (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
429         {
430                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
431                 {
432                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
433                              FPGA_REG3_ENET_GROUP7);
434                 }
435                 else
436                 {
437                         if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
438                         {
439                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
440                                      FPGA_REG3_ENET_GROUP7);
441                         }
442                         else
443                         {
444                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
445                                      FPGA_REG3_ENET_GROUP8);
446                         }
447                 }
448         }
449         else
450         {
451                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
452                 {
453                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
454                              FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
455                 }
456                 else
457                 {
458                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
459                              FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
460                 }
461         }
462         out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
463              FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
464              FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
465
466         /* reset the gigabyte phy if necessary */
467         if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
468         {
469                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
470                 {
471                         out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
472                         udelay(10000);
473                         out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
474                 }
475                 else
476                 {
477                         out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
478                         udelay(10000);
479                         out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
480                 }
481         }
482
483         /*
484          * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
485          */
486         if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
487                 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
488                 udelay(10000);
489                 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
490         }
491
492         /* Turn off the LED's */
493         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
494              FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
495              FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
496
497         return;
498 }
499
500 #ifdef CONFIG_POST
501 /*
502  * Returns 1 if keys pressed to start the power-on long-running tests
503  * Called from board_init_f().
504  */
505 int post_hotkeys_pressed(void)
506 {
507
508         return (ctrlc());
509 }
510 #endif