board/amcc/yucca/yucca.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
  24  *
  25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/ppc4xx.h>
  30 #include <i2c.h>
  31 #include <netdev.h>
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34 #include <asm/4xx_pcie.h>
  35 #include <asm/errno.h>
  36
  37 #include "yucca.h"
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 void fpga_init (void);
  42
  43 #define DEBUG_ENV
  44 #ifdef DEBUG_ENV
  45 #define DEBUGF(fmt,args...) printf(fmt ,##args)
  46 #else
  47 #define DEBUGF(fmt,args...)
  48 #endif
  49
  50 int board_early_init_f (void)
  51 {
  52 /*----------------------------------------------------------------------------+
  53 | Define Boot devices
  54 +----------------------------------------------------------------------------*/
  55 #define BOOT_FROM_SMALL_FLASH           0x00
  56 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
  57 #define BOOT_FROM_PCI                   0x02
  58 #define BOOT_DEVICE_UNKNOWN             0x03
  59
  60 /*----------------------------------------------------------------------------+
  61 | EBC Devices Characteristics
  62 |   Peripheral Bank Access Parameters       -   EBC_BxAP
  63 |   Peripheral Bank Configuration Register  -   EBC_BxCR
  64 +----------------------------------------------------------------------------*/
  65
  66 /*
  67  * Small Flash and FRAM
  68  * BU Value
  69  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  70  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
  71  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
  72  */
  73 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
  74                                         EBC_BXAP_TWT_ENCODE(7)  | \
  75                                         EBC_BXAP_BCE_DISABLE    | \
  76                                         EBC_BXAP_BCT_2TRANS     | \
  77                                         EBC_BXAP_CSN_ENCODE(0)  | \
  78                                         EBC_BXAP_OEN_ENCODE(0)  | \
  79                                         EBC_BXAP_WBN_ENCODE(0)  | \
  80                                         EBC_BXAP_WBF_ENCODE(0)  | \
  81                                         EBC_BXAP_TH_ENCODE(0)   | \
  82                                         EBC_BXAP_RE_DISABLED    | \
  83                                         EBC_BXAP_SOR_DELAYED    | \
  84                                         EBC_BXAP_BEM_WRITEONLY  | \
  85                                         EBC_BXAP_PEN_DISABLED
  86
  87 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  88                                         EBC_BXCR_BS_16MB                | \
  89                                         EBC_BXCR_BU_RW                  | \
  90                                         EBC_BXCR_BW_8BIT
  91
  92 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
  93                                         EBC_BXCR_BS_16MB                | \
  94                                         EBC_BXCR_BU_RW                  | \
  95                                         EBC_BXCR_BW_8BIT
  96
  97 /*
  98  * Large Flash and SRAM
  99  * BU Value
 100  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 101  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 102  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
 103 */
 104 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
 105                                         EBC_BXAP_TWT_ENCODE(7)  | \
 106                                         EBC_BXAP_BCE_DISABLE    | \
 107                                         EBC_BXAP_BCT_2TRANS     | \
 108                                         EBC_BXAP_CSN_ENCODE(0)  | \
 109                                         EBC_BXAP_OEN_ENCODE(0)  | \
 110                                         EBC_BXAP_WBN_ENCODE(0)  | \
 111                                         EBC_BXAP_WBF_ENCODE(0)  | \
 112                                         EBC_BXAP_TH_ENCODE(0)   | \
 113                                         EBC_BXAP_RE_DISABLED    | \
 114                                         EBC_BXAP_SOR_DELAYED    | \
 115                                         EBC_BXAP_BEM_WRITEONLY  | \
 116                                         EBC_BXAP_PEN_DISABLED
 117
 118 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
 119                                         EBC_BXCR_BS_16MB                | \
 120                                         EBC_BXCR_BU_RW                  | \
 121                                         EBC_BXCR_BW_16BIT
 122
 123 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
 124                                         EBC_BXCR_BS_16MB                | \
 125                                         EBC_BXCR_BU_RW                  | \
 126                                         EBC_BXCR_BW_16BIT
 127
 128 /*
 129  * FPGA
 130  * BU value :
 131  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
 132  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
 133  */
 134 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
 135                                         EBC_BXAP_TWT_ENCODE(11) | \
 136                                         EBC_BXAP_BCE_DISABLE    | \
 137                                         EBC_BXAP_BCT_2TRANS     | \
 138                                         EBC_BXAP_CSN_ENCODE(10) | \
 139                                         EBC_BXAP_OEN_ENCODE(1)  | \
 140                                         EBC_BXAP_WBN_ENCODE(1)  | \
 141                                         EBC_BXAP_WBF_ENCODE(1)  | \
 142                                         EBC_BXAP_TH_ENCODE(1)   | \
 143                                         EBC_BXAP_RE_DISABLED    | \
 144                                         EBC_BXAP_SOR_DELAYED    | \
 145                                         EBC_BXAP_BEM_RW         | \
 146                                         EBC_BXAP_PEN_DISABLED
 147
 148 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
 149                                         EBC_BXCR_BS_1MB                 | \
 150                                         EBC_BXCR_BU_RW                  | \
 151                                         EBC_BXCR_BW_16BIT
 152
 153          unsigned long mfr;
 154         /*
 155          * Define Variables for EBC initialization depending on BOOTSTRAP option
 156          */
 157         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
 158         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
 159         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
 160
 161         /*-------------------------------------------------------------------+
 162          | Initialize EBC CONFIG -
 163          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 164          | default value :
 165          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 166          |
 167          +-------------------------------------------------------------------*/
 168         mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
 169                         EBC_CFG_PTD_ENABLE |
 170                         EBC_CFG_RTC_16PERCLK |
 171                         EBC_CFG_ATC_PREVIOUS |
 172                         EBC_CFG_DTC_PREVIOUS |
 173                         EBC_CFG_CTC_PREVIOUS |
 174                         EBC_CFG_OEO_PREVIOUS |
 175                         EBC_CFG_EMC_DEFAULT |
 176                         EBC_CFG_PME_DISABLE |
 177                         EBC_CFG_PR_16);
 178
 179         /*-------------------------------------------------------------------+
 180          |
 181          |  PART 1 : Initialize EBC Bank 1
 182          |  ==============================
 183          | Bank1 is always associated to the EPLD.
 184          | It has to be initialized prior to other banks settings computation
 185          | since some board registers values may be needed to determine the
 186          | boot type
 187          |
 188          +-------------------------------------------------------------------*/
 189         mtebc(PB1AP, EBC_BXAP_FPGA);
 190         mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
 191
 192         /*-------------------------------------------------------------------+
 193          |
 194          |  PART 2 : Determine which boot device was selected
 195          |  =================================================
 196          |
 197          |  Read Pin Strap Register in PPC440SPe
 198          |  Result can either be :
 199          |   - Boot strap = boot from EBC 8bits     => Small Flash
 200          |   - Boot strap = boot from PCI
 201          |   - Boot strap = IIC
 202          |  In case of boot from IIC, read Serial Device Strap Register1
 203          |
 204          |  Result can either be :
 205          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
 206          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
 207          |   - Boot from PCI
 208          |
 209          +-------------------------------------------------------------------*/
 210         /* Read Pin Strap Register in PPC440SP */
 211         mfsdr(SDR0_PINSTP, sdr0_pinstp);
 212         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
 213
 214         switch (bootstrap_settings) {
 215                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
 216                         /*
 217                          * Strapping Option A
 218                          * Boot from EBC - 8 bits , Small Flash
 219                          */
 220                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 221                         break;
 222                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
 223                         /*
 224                          * Strappping Option B
 225                          * Boot from PCI
 226                          */
 227                         computed_boot_device = BOOT_FROM_PCI;
 228                         break;
 229                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
 230                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
 231                         /*
 232                          * Strapping Option C or D
 233                          * Boot Settings in IIC EEprom address 0x50 or 0x54
 234                          * Read Serial Device Strap Register1 in PPC440SPe
 235                          */
 236                         mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
 237                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
 238                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
 239
 240                         switch (boot_selection) {
 241                                 case SDR0_SDSTP1_ERPN_EBC:
 242                                         switch (ebc_data_width) {
 243                                                 case SDR0_SDSTP1_EBCW_16_BITS:
 244                                                         computed_boot_device =
 245                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
 246                                                         break;
 247                                                 case SDR0_SDSTP1_EBCW_8_BITS :
 248                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 249                                                         break;
 250                                         }
 251                                         break;
 252
 253                                 case SDR0_SDSTP1_ERPN_PCI:
 254                                         computed_boot_device = BOOT_FROM_PCI;
 255                                         break;
 256                                 default:
 257                                         /* should not occure */
 258                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 259                         }
 260                         break;
 261                 default:
 262                         /* should not be */
 263                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 264                         break;
 265         }
 266
 267         /*-------------------------------------------------------------------+
 268          |
 269          |  PART 3 : Compute EBC settings depending on selected boot device
 270          |  ======   ======================================================
 271          |
 272          | Resulting EBC init will be among following configurations :
 273          |
 274          |  - Boot from EBC 8bits => boot from Small Flash selected
 275          |            EBC-CS0     = Small Flash
 276          |            EBC-CS2     = Large Flash and SRAM
 277          |
 278          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
 279          |            EBC-CS0     = Large Flash or SRAM
 280          |            EBC-CS2     = Small Flash
 281          |
 282          |  - Boot from PCI
 283          |            EBC-CS0     = not initialized to avoid address contention
 284          |            EBC-CS2     = same as boot from Small Flash selected
 285          |
 286          +-------------------------------------------------------------------*/
 287         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
 288         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
 289
 290         switch (computed_boot_device) {
 291                 /*-------------------------------------------------------------------*/
 292                 case BOOT_FROM_PCI:
 293                 /*-------------------------------------------------------------------*/
 294                         /*
 295                          * By Default CS2 is affected to LARGE Flash
 296                          * do not initialize SMALL FLASH to avoid address contention
 297                          * Large Flash
 298                          */
 299                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
 300                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 301                         break;
 302
 303                 /*-------------------------------------------------------------------*/
 304                 case BOOT_FROM_SMALL_FLASH:
 305                 /*-------------------------------------------------------------------*/
 306                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
 307                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
 308
 309                         /*
 310                          * Large Flash or SRAM
 311                          */
 312                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
 313                         ebc0_cs2_bxap_value = 0x048ff240;
 314                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 315                         break;
 316
 317                 /*-------------------------------------------------------------------*/
 318                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 319                 /*-------------------------------------------------------------------*/
 320                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
 321                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
 322
 323                         /* Small flash */
 324                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
 325                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
 326                         break;
 327
 328                 /*-------------------------------------------------------------------*/
 329                 default:
 330                 /*-------------------------------------------------------------------*/
 331                         /* BOOT_DEVICE_UNKNOWN */
 332                         break;
 333         }
 334
 335         mtebc(PB0AP, ebc0_cs0_bxap_value);
 336         mtebc(PB0CR, ebc0_cs0_bxcr_value);
 337         mtebc(PB2AP, ebc0_cs2_bxap_value);
 338         mtebc(PB2CR, ebc0_cs2_bxcr_value);
 339
 340         /*--------------------------------------------------------------------+
 341          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
 342          +--------------------------------------------------------------------+
 343         +---------------------------------------------------------------------+
 344         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
 345         +---------+-----------------------------------+-------+-------+-------+
 346         | IRQ 00  | UART0                             | High  | Level | Non   |
 347         | IRQ 01  | UART1                             | High  | Level | Non   |
 348         | IRQ 02  | IIC0                              | High  | Level | Non   |
 349         | IRQ 03  | IIC1                              | High  | Level | Non   |
 350         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
 351         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
 352         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
 353         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
 354         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
 355         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
 356         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
 357         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
 358         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
 359         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
 360         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
 361         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
 362         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
 363         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
 364         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
 365         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
 366         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
 367         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
 368         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
 369         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
 370         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
 371         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
 372         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
 373         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
 374         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
 375         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
 376         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
 377         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
 378         |----------------------------------------------------------------------
 379         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
 380         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
 381         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
 382         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
 383         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
 384         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
 385         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
 386         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
 387         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
 388         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
 389         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
 390         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
 391         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
 392         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
 393         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
 394         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
 395         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
 396         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
 397         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
 398         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
 399         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 400         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
 401         | IRQ 54  | DMA Error                         | High  | Level | Non   |
 402         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
 403         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
 404         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
 405         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
 406         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
 407         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
 408         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
 409         | IRQ 62  | Reserved                          | High  | Level | Non   |
 410         | IRQ 63  | XOR                               | High  | Level | Non   |
 411         |----------------------------------------------------------------------
 412         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 413         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 414         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 415         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 416         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 417         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 418         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 419         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 420         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 421         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 422         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 423         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 424         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 425         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 426         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 427         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 428         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 429         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 430         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 431         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 432         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 433         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 434         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 435         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 436         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 437         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 438         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 439         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 440         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 441         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 442         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 443         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 444         |---------------------------------------------------------------------
 445         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
 446         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
 447         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
 448         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
 449         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
 450         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
 451         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
 452         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
 453         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
 454         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
 455         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
 456         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
 457         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
 458         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
 459         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
 460         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
 461         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
 462         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
 463         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
 464         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
 465         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
 466         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
 467         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
 468         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
 469         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
 470         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
 471         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
 472         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
 473         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
 474         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
 475         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
 476         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
 477         +---------+-----------------------------------+-------+-------+------*/
 478         /*--------------------------------------------------------------------+
 479          | Put UICs in PowerPC440SPemode.
 480          | Initialise UIC registers.  Clear all interrupts.  Disable all
 481          | interrupts.
 482          | Set critical interrupt values.  Set interrupt polarities.  Set
 483          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 484          | interrupts again.
 485          +-------------------------------------------------------------------*/
 486         mtdcr (UIC3SR, 0xffffffff);     /* Clear all interrupts */
 487         mtdcr (UIC3ER, 0x00000000);     /* disable all interrupts */
 488         mtdcr (UIC3CR, 0x00000000);     /* Set Critical / Non Critical
 489                                          * interrupts */
 490         mtdcr (UIC3PR, 0xffffffff);     /* Set Interrupt Polarities */
 491         mtdcr (UIC3TR, 0x001fffff);     /* Set Interrupt Trigger Levels */
 492         mtdcr (UIC3VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
 493                                          * priority */
 494         mtdcr (UIC3SR, 0x00000000);     /* clear all  interrupts */
 495         mtdcr (UIC3SR, 0xffffffff);     /* clear all  interrupts */
 496
 497         mtdcr (UIC2SR, 0xffffffff);     /* Clear all interrupts */
 498         mtdcr (UIC2ER, 0x00000000);     /* disable all interrupts */
 499         mtdcr (UIC2CR, 0x00000000);     /* Set Critical / Non Critical
 500                                          * interrupts */
 501         mtdcr (UIC2PR, 0xebebebff);     /* Set Interrupt Polarities */
 502         mtdcr (UIC2TR, 0x74747400);     /* Set Interrupt Trigger Levels */
 503         mtdcr (UIC2VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
 504                                          * priority */
 505         mtdcr (UIC2SR, 0x00000000);     /* clear all interrupts */
 506         mtdcr (UIC2SR, 0xffffffff);     /* clear all interrupts */
 507
 508         mtdcr (UIC1SR, 0xffffffff);     /* Clear all interrupts */
 509         mtdcr (UIC1ER, 0x00000000);     /* disable all interrupts */
 510         mtdcr (UIC1CR, 0x00000000);     /* Set Critical / Non Critical
 511                                          * interrupts */
 512         mtdcr (UIC1PR, 0xffffffff);     /* Set Interrupt Polarities */
 513         mtdcr (UIC1TR, 0x001f8040);     /* Set Interrupt Trigger Levels */
 514         mtdcr (UIC1VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
 515                                          * priority */
 516         mtdcr (UIC1SR, 0x00000000);     /* clear all interrupts */
 517         mtdcr (UIC1SR, 0xffffffff);     /* clear all interrupts */
 518
 519         mtdcr (UIC0SR, 0xffffffff);     /* Clear all interrupts */
 520         mtdcr (UIC0ER, 0x00000000);     /* disable all interrupts excepted
 521                                          * cascade to be checked */
 522         mtdcr (UIC0CR, 0x00104001);     /* Set Critical / Non Critical
 523                                          * interrupts */
 524         mtdcr (UIC0PR, 0xffffffff);     /* Set Interrupt Polarities */
 525         mtdcr (UIC0TR, 0x010f0004);     /* Set Interrupt Trigger Levels */
 526         mtdcr (UIC0VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
 527                                          * priority */
 528         mtdcr (UIC0SR, 0x00000000);     /* clear all interrupts */
 529         mtdcr (UIC0SR, 0xffffffff);     /* clear all interrupts */
 530
 531         mfsdr(SDR0_MFR, mfr);
 532         mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
 533         mtsdr(SDR0_MFR, mfr);
 534
 535         fpga_init();
 536
 537         return 0;
 538 }
 539
 540 int checkboard (void)
 541 {
 542         char buf[64];
 543         int i = getenv_f("serial#", buf, sizeof(buf));
 544
 545         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
 546         if (i > 0) {
 547                 puts(", serial# ");
 548                 puts(buf);
 549         }
 550         putc('\n');
 551
 552         return 0;
 553 }
 554
 555 /*
 556  * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
 557  * board specific values.
 558  */
 559 static int ppc440spe_rev_a(void)
 560 {
 561         if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
 562                 return 1;
 563         else
 564                 return 0;
 565 }
 566
 567 u32 ddr_wrdtr(u32 default_val) {
 568         /*
 569          * Yucca boards with 440SPe rev. A need a slightly different setup
 570          * for the MCIF0_WRDTR register.
 571          */
 572         if (ppc440spe_rev_a())
 573                 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
 574
 575         return default_val;
 576 }
 577
 578 u32 ddr_clktr(u32 default_val) {
 579         /*
 580          * Yucca boards with 440SPe rev. A need a slightly different setup
 581          * for the MCIF0_CLKTR register.
 582          */
 583         if (ppc440spe_rev_a())
 584                 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
 585
 586         return default_val;
 587 }
 588
 589 #if defined(CONFIG_PCI)
 590 int board_pcie_card_present(int port)
 591 {
 592         u16 reg;
 593
 594         reg = in_be16((u16 *)FPGA_REG1C);
 595         switch(port) {
 596         case 0:
 597                 return !(reg & FPGA_REG1C_PE0_PRSNT);
 598         case 1:
 599                 return !(reg & FPGA_REG1C_PE1_PRSNT);
 600         case 2:
 601                 return !(reg & FPGA_REG1C_PE2_PRSNT);
 602         default:
 603                 return 0;
 604         }
 605 }
 606
 607 /*
 608  * For the given slot, set endpoint mode, send power to the slot,
 609  * turn on the green LED and turn off the yellow LED, enable the
 610  * clock. In endpoint mode reset bit is read only.
 611  */
 612 void board_pcie_setup_port(int port, int rootpoint)
 613 {
 614         u16 power, clock, green_led, yellow_led,
 615                 reset_off, rp, ep;
 616
 617         switch (port) {
 618         case 0:
 619                 rp = FPGA_REG1C_PE0_ROOTPOINT;
 620                 ep = 0;
 621                 break;
 622         case 1:
 623                 rp = 0;
 624                 ep = FPGA_REG1C_PE1_ENDPOINT;
 625                 break;
 626         case 2:
 627                 rp = 0;
 628                 ep = FPGA_REG1C_PE2_ENDPOINT;
 629                 break;
 630
 631         default:
 632                 return;
 633         }
 634
 635         power = FPGA_REG1A_PWRON_ENCODE(port);
 636         green_led = FPGA_REG1A_GLED_ENCODE(port);
 637         clock = FPGA_REG1A_REFCLK_ENCODE(port);
 638         yellow_led = FPGA_REG1A_YLED_ENCODE(port);
 639         reset_off = FPGA_REG1C_PERST_ENCODE(port);
 640
 641         out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
 642                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 643
 644         out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
 645                  (rp | in_be16((u16 *)FPGA_REG1C)));
 646
 647         if (rootpoint) {
 648                 /*
 649                  * Leave device in reset for a while after powering on the
 650                  * slot to give it a chance to initialize.
 651                  */
 652                 udelay(250 * 1000);
 653
 654                 out_be16((u16 *)FPGA_REG1C,
 655                          reset_off | in_be16((u16 *)FPGA_REG1C));
 656         }
 657 }
 658 #endif  /* defined(CONFIG_PCI) */
 659
 660 int misc_init_f (void)
 661 {
 662         uint reg;
 663
 664         out16(FPGA_REG10, (in16(FPGA_REG10) &
 665                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
 666                                 FPGA_REG10_10MHZ_ENABLE |
 667                                 FPGA_REG10_100MHZ_ENABLE |
 668                                 FPGA_REG10_GIGABIT_ENABLE |
 669                                 FPGA_REG10_FULL_DUPLEX );
 670
 671         udelay(10000);  /* wait 10ms */
 672
 673         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
 674
 675         /* minimal init for PCIe */
 676         /* pci express 0 Endpoint Mode */
 677         mfsdr(SDRN_PESDR_DLPSET(0), reg);
 678         reg &= (~0x00400000);
 679         mtsdr(SDRN_PESDR_DLPSET(0), reg);
 680         /* pci express 1 Rootpoint  Mode */
 681         mfsdr(SDRN_PESDR_DLPSET(1), reg);
 682         reg |= 0x00400000;
 683         mtsdr(SDRN_PESDR_DLPSET(1), reg);
 684         /* pci express 2 Rootpoint  Mode */
 685         mfsdr(SDRN_PESDR_DLPSET(2), reg);
 686         reg |= 0x00400000;
 687         mtsdr(SDRN_PESDR_DLPSET(2), reg);
 688
 689         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
 690                                 ~FPGA_REG1C_PE0_ROOTPOINT &
 691                                 ~FPGA_REG1C_PE1_ENDPOINT  &
 692                                 ~FPGA_REG1C_PE2_ENDPOINT));
 693
 694         return 0;
 695 }
 696
 697 void fpga_init(void)
 698 {
 699         /*
 700          * by default sdram access is disabled by fpga
 701          */
 702         out16(FPGA_REG10, (in16 (FPGA_REG10) |
 703                                 FPGA_REG10_SDRAM_ENABLE |
 704                                 FPGA_REG10_ENABLE_DISPLAY ));
 705
 706         return;
 707 }
 708
 709 /*---------------------------------------------------------------------------+
 710  | onboard_pci_arbiter_selected => from EPLD
 711  +---------------------------------------------------------------------------*/
 712 int onboard_pci_arbiter_selected(int core_pci)
 713 {
 714 #if 0
 715         unsigned long onboard_pci_arbiter_sel;
 716
 717         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
 718
 719         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
 720                 return (BOARD_OPTION_SELECTED);
 721         else
 722 #endif
 723         return (BOARD_OPTION_NOT_SELECTED);
 724 }
 725
 726 int board_eth_init(bd_t *bis)
 727 {
 728         cpu_eth_init(bis);
 729         return pci_eth_init(bis);
 730 }