board/atmel/at91cap9adk/at91cap9adk.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91cap9.h>
  27 #include <asm/arch/at91cap9_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_pmc.h>
  30 #include <asm/arch/at91_rstc.h>
  31 #include <asm/arch/gpio.h>
  32 #include <asm/arch/io.h>
  33 #include <asm/arch/hardware.h>
  34 #include <lcd.h>
  35 #include <atmel_lcdc.h>
  36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  37 #include <net.h>
  38 #endif
  39 #include <netdev.h>
  40
  41 #define MP_BLOCK_3_BASE 0xFDF00000
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /* ------------------------------------------------------------------------- */
  46 /*
  47  * Miscelaneous platform dependent initialisations
  48  */
  49
  50 static void at91cap9_serial_hw_init(void)
  51 {
  52 #ifdef CONFIG_USART0
  53         at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
  54         at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
  55         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
  56 #endif
  57
  58 #ifdef CONFIG_USART1
  59         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
  60         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
  61         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
  62 #endif
  63
  64 #ifdef CONFIG_USART2
  65         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
  66         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
  67         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
  68 #endif
  69
  70 #ifdef CONFIG_USART3    /* DBGU */
  71         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
  72         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
  73         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  74 #endif
  75 }
  76
  77 static void at91cap9_slowclock_hw_init(void)
  78 {
  79         /*
  80          * On AT91CAP9 revC CPUs, the slow clock can be based on an
  81          * internal impreciseRC oscillator or an external 32kHz oscillator.
  82          * Switch to the latter.
  83          */
  84 #define ARCH_ID_AT91CAP9_REVB   0x399
  85 #define ARCH_ID_AT91CAP9_REVC   0x601
  86         if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
  87                 unsigned i, tmp = at91_sys_read(AT91_SCKCR);
  88                 if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
  89                         extern void timer_init(void);
  90                         timer_init();
  91                         tmp |= AT91CAP9_SCKCR_OSC32EN;
  92                         at91_sys_write(AT91_SCKCR, tmp);
  93                         for (i = 0; i < 1200; i++)
  94                                 udelay(1000);
  95                         tmp |= AT91CAP9_SCKCR_OSCSEL_32;
  96                         at91_sys_write(AT91_SCKCR, tmp);
  97                         udelay(200);
  98                         tmp &= ~AT91CAP9_SCKCR_RCEN;
  99                         at91_sys_write(AT91_SCKCR, tmp);
 100                 }
 101         }
 102 }
 103
 104 static void at91cap9_nor_hw_init(void)
 105 {
 106         unsigned long csa;
 107
 108         /* Ensure EBI supply is 3.3V */
 109         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 110         at91_sys_write(AT91_MATRIX_EBICSA,
 111                        csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 112         /* Configure SMC CS0 for parallel flash */
 113         at91_sys_write(AT91_SMC_SETUP(0),
 114                        AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
 115                        AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
 116         at91_sys_write(AT91_SMC_PULSE(0),
 117                        AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
 118                        AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
 119         at91_sys_write(AT91_SMC_CYCLE(0),
 120                        AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
 121         at91_sys_write(AT91_SMC_MODE(0),
 122                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 123                        AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
 124                        AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
 125 }
 126
 127 #ifdef CONFIG_CMD_NAND
 128 static void at91cap9_nand_hw_init(void)
 129 {
 130         unsigned long csa;
 131
 132         /* Enable CS3 */
 133         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 134         at91_sys_write(AT91_MATRIX_EBICSA,
 135                        csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
 136                        AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 137
 138         /* Configure SMC CS3 for NAND/SmartMedia */
 139         at91_sys_write(AT91_SMC_SETUP(3),
 140                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
 141                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
 142         at91_sys_write(AT91_SMC_PULSE(3),
 143                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
 144                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
 145         at91_sys_write(AT91_SMC_CYCLE(3),
 146                        AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
 147         at91_sys_write(AT91_SMC_MODE(3),
 148                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 149                        AT91_SMC_EXNWMODE_DISABLE |
 150 #ifdef CONFIG_SYS_NAND_DBW_16
 151                        AT91_SMC_DBW_16 |
 152 #else /* CONFIG_SYS_NAND_DBW_8 */
 153                        AT91_SMC_DBW_8 |
 154 #endif
 155                        AT91_SMC_TDF_(1));
 156
 157         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 158
 159         /* RDY/BSY is not connected */
 160
 161         /* Enable NandFlash */
 162         at91_set_gpio_output(AT91_PIN_PD15, 1);
 163 }
 164 #endif
 165
 166 #ifdef CONFIG_HAS_DATAFLASH
 167 static void at91cap9_spi_hw_init(void)
 168 {
 169         at91_set_B_periph(AT91_PIN_PA5, 0);     /* SPI0_NPCS0 */
 170
 171         at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 172         at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 173         at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 174
 175         /* Enable clock */
 176         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
 177 }
 178 #endif
 179
 180 #ifdef CONFIG_MACB
 181 static void at91cap9_macb_hw_init(void)
 182 {
 183         /* Enable clock */
 184         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
 185
 186         /*
 187          * Disable pull-up on:
 188          *      RXDV (PB22) => PHY normal mode (not Test mode)
 189          *      ERX0 (PB25) => PHY ADDR0
 190          *      ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
 191          *
 192          * PHY has internal pull-down
 193          */
 194         writel(pin_to_mask(AT91_PIN_PB22) |
 195                pin_to_mask(AT91_PIN_PB25) |
 196                pin_to_mask(AT91_PIN_PB26),
 197                pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 198
 199         /* Need to reset PHY -> 500ms reset */
 200         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 201                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 202                                      AT91_RSTC_URSTEN);
 203
 204         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 205
 206         /* Wait for end hardware reset */
 207         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 208
 209         /* Restore NRST value */
 210         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 211                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
 212                                      AT91_RSTC_URSTEN);
 213
 214         /* Re-enable pull-up */
 215         writel(pin_to_mask(AT91_PIN_PB22) |
 216                pin_to_mask(AT91_PIN_PB25) |
 217                pin_to_mask(AT91_PIN_PB26),
 218                pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 219
 220         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
 221         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
 222         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
 223         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
 224         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
 225         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
 226         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
 227         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
 228         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
 229         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
 230
 231 #ifndef CONFIG_RMII
 232         at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
 233         at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
 234         at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
 235         at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
 236         at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
 237         at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
 238         at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
 239         at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
 240 #endif
 241         /* Unlock EMAC, 3 0 2 1 sequence */
 242 #define MP_MAC_KEY0     0x5969cb2a
 243 #define MP_MAC_KEY1     0xb4a1872e
 244 #define MP_MAC_KEY2     0x05683fbc
 245 #define MP_MAC_KEY3     0x3634fba4
 246 #define UNLOCK_MAC      0x00000008
 247         writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
 248         writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
 249         writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
 250         writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
 251         writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
 252 }
 253 #endif
 254
 255 #ifdef CONFIG_USB_OHCI_NEW
 256 static void at91cap9_uhp_hw_init(void)
 257 {
 258         /* Unlock USB OHCI, 3 2 0 1 sequence */
 259 #define MP_OHCI_KEY0    0x896c11ca
 260 #define MP_OHCI_KEY1    0x68ebca21
 261 #define MP_OHCI_KEY2    0x4823efbc
 262 #define MP_OHCI_KEY3    0x8651aae4
 263 #define UNLOCK_OHCI     0x00000010
 264         writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
 265         writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
 266         writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
 267         writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
 268         writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
 269 }
 270 #endif
 271
 272 #ifdef CONFIG_LCD
 273 vidinfo_t panel_info = {
 274         vl_col:         240,
 275         vl_row:         320,
 276         vl_clk:         4965000,
 277         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 278                         ATMEL_LCDC_INVFRAME_INVERTED,
 279         vl_bpix:        3,
 280         vl_tft:         1,
 281         vl_hsync_len:   5,
 282         vl_left_margin: 1,
 283         vl_right_margin:33,
 284         vl_vsync_len:   1,
 285         vl_upper_margin:1,
 286         vl_lower_margin:0,
 287         mmio:           AT91CAP9_LCDC_BASE,
 288 };
 289
 290 void lcd_enable(void)
 291 {
 292         at91_set_gpio_value(AT91_PIN_PC0, 0);  /* power up */
 293 }
 294
 295 void lcd_disable(void)
 296 {
 297         at91_set_gpio_value(AT91_PIN_PC0, 1);  /* power down */
 298 }
 299
 300 static void at91cap9_lcd_hw_init(void)
 301 {
 302         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 303         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 304         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 305         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 306         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 307         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 308         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 309         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 310         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 311         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 312         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 313         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 314         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 315         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 316         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 317         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 318         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 319         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 320         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 321         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
 322         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 323         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 324
 325         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
 326
 327         gd->fb_base = 0;
 328 }
 329 #endif
 330
 331 int board_init(void)
 332 {
 333         /* Enable Ctrlc */
 334         console_init_f();
 335
 336         /* arch number of AT91CAP9ADK-Board */
 337         gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
 338         /* adress of boot parameters */
 339         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 340
 341         at91cap9_serial_hw_init();
 342         at91cap9_slowclock_hw_init();
 343         at91cap9_nor_hw_init();
 344 #ifdef CONFIG_CMD_NAND
 345         at91cap9_nand_hw_init();
 346 #endif
 347 #ifdef CONFIG_HAS_DATAFLASH
 348         at91cap9_spi_hw_init();
 349 #endif
 350 #ifdef CONFIG_MACB
 351         at91cap9_macb_hw_init();
 352 #endif
 353 #ifdef CONFIG_USB_OHCI_NEW
 354         at91cap9_uhp_hw_init();
 355 #endif
 356 #ifdef CONFIG_LCD
 357         at91cap9_lcd_hw_init();
 358 #endif
 359         return 0;
 360 }
 361
 362 int dram_init(void)
 363 {
 364         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 365         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 366         return 0;
 367 }
 368
 369 #ifdef CONFIG_RESET_PHY_R
 370 void reset_phy(void)
 371 {
 372 #ifdef CONFIG_MACB
 373         /*
 374          * Initialize ethernet HW addr prior to starting Linux,
 375          * needed for nfsroot
 376          */
 377         eth_init(gd->bd);
 378 #endif
 379 }
 380 #endif
 381
 382 int board_eth_init(bd_t *bis)
 383 {
 384         int rc = 0;
 385 #ifdef CONFIG_MACB
 386         rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
 387 #endif
 388         return rc;
 389 }