board/atum8548/atum8548.c

   1 /*
   2  * Copyright 2007
   3  * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
   4  *
   5  * Copyright 2007 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <command.h>
  28 #include <pci.h>
  29 #include <asm/processor.h>
  30 #include <asm/immap_85xx.h>
  31 #include <asm/immap_fsl_pci.h>
  32 #include <asm/io.h>
  33 #include <spd.h>
  34 #include <miiphy.h>
  35 #include <libfdt.h>
  36 #include <fdt_support.h>
  37
  38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  39 extern void ddr_enable_ecc(unsigned int dram_size);
  40 #endif
  41
  42 extern long int spd_sdram(void);
  43 long int fixed_sdram(void);
  44
  45 int board_early_init_f (void)
  46 {
  47         return 0;
  48 }
  49
  50 int checkboard (void)
  51 {
  52         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  53         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  54         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  55
  56         if ((uint)&gur->porpllsr != 0xe00e0000) {
  57                 printf("immap size error %x\n",&gur->porpllsr);
  58         }
  59         printf ("Board: ATUM8548\n");
  60
  61         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  62         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  63         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  64         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  65
  66         return 0;
  67 }
  68
  69 #if !defined(CONFIG_SPD_EEPROM)
  70 /*************************************************************************
  71  *  fixed sdram init -- doesn't use serial presence detect.
  72  ************************************************************************/
  73 long int fixed_sdram (void)
  74 {
  75         volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
  76
  77         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
  78         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
  79         ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
  80         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
  81         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
  82         ddr->sdram_mode = CFG_DDR_MODE;
  83         ddr->sdram_interval = CFG_DDR_INTERVAL;
  84     #if defined (CONFIG_DDR_ECC)
  85         ddr->err_disable = 0x0000000D;
  86         ddr->err_sbe = 0x00ff0000;
  87     #endif
  88         asm("sync;isync;msync");
  89         udelay(500);
  90     #if defined (CONFIG_DDR_ECC)
  91         /* Enable ECC checking */
  92         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
  93     #else
  94         ddr->sdram_cfg = CFG_DDR_CONTROL;
  95     #endif
  96         asm("sync; isync; msync");
  97         udelay(500);
  98         return CFG_SDRAM_SIZE * 1024 * 1024;
  99 }
 100 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 101
 102 long int
 103 initdram(int board_type)
 104 {
 105         long dram_size = 0;
 106
 107         puts("Initializing\n");
 108
 109 #if defined(CONFIG_SPD_EEPROM)
 110         puts("spd_sdram\n");
 111         dram_size = spd_sdram ();
 112 #else
 113         puts("fixed_sdram\n");
 114         dram_size = fixed_sdram ();
 115 #endif
 116
 117 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 118         /*
 119          * Initialize and enable DDR ECC.
 120          */
 121         ddr_enable_ecc(dram_size);
 122 #endif
 123         puts("    DDR: ");
 124         return dram_size;
 125 }
 126
 127 #if defined(CFG_DRAM_TEST)
 128 int
 129 testdram(void)
 130 {
 131         uint *pstart = (uint *) CFG_MEMTEST_START;
 132         uint *pend = (uint *) CFG_MEMTEST_END;
 133         uint *p;
 134
 135         printf("Testing DRAM from 0x%08x to 0x%08x\n",
 136                CFG_MEMTEST_START,
 137                CFG_MEMTEST_END);
 138
 139         printf("DRAM test phase 1:\n");
 140         for (p = pstart; p < pend; p++) {
 141                 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
 142                 *p = 0xaaaaaaaa;
 143         }
 144
 145         for (p = pstart; p < pend; p++) {
 146                 if (*p != 0xaaaaaaaa) {
 147                         printf ("DRAM test fails at: %08x\n", (uint) p);
 148                         return 1;
 149                 }
 150         }
 151
 152         printf("DRAM test phase 2:\n");
 153         for (p = pstart; p < pend; p++)
 154                 *p = 0x55555555;
 155
 156         for (p = pstart; p < pend; p++) {
 157                 if (*p != 0x55555555) {
 158                         printf ("DRAM test fails at: %08x\n", (uint) p);
 159                         return 1;
 160                 }
 161         }
 162
 163         printf("DRAM test passed.\n");
 164         return 0;
 165 }
 166 #endif
 167
 168 #ifdef CONFIG_PCI1
 169 static struct pci_controller pci1_hose;
 170 #endif
 171
 172 #ifdef CONFIG_PCI2
 173 static struct pci_controller pci2_hose;
 174 #endif
 175
 176 #ifdef CONFIG_PCIE1
 177 static struct pci_controller pcie1_hose;
 178 #endif
 179
 180 int first_free_busno=0;
 181
 182 void
 183 pci_init_board(void)
 184 {
 185         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 186
 187         uint devdisr = gur->devdisr;
 188         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 189         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 190
 191         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 192                 devdisr, io_sel, host_agent);
 193
 194         /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
 195         gur->clkocr  |= MPC85xx_ATUM_CLKOCR;
 196
 197         if (io_sel & 1) {
 198                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 199                         printf ("    eTSEC1 is in sgmii mode.\n");
 200                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 201                         printf ("    eTSEC2 is in sgmii mode.\n");
 202                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 203                         printf ("    eTSEC3 is in sgmii mode.\n");
 204                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 205                         printf ("    eTSEC4 is in sgmii mode.\n");
 206         }
 207
 208 #ifdef CONFIG_PCIE1
 209  {
 210         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 211         extern void fsl_pci_init(struct pci_controller *hose);
 212         struct pci_controller *hose = &pcie1_hose;
 213         int pcie_ep = (host_agent == 5);
 214         int pcie_configured  = io_sel & 6;
 215
 216         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 217                 printf ("\n    PCIE1 connected to slot as %s (base address %x)",
 218                         pcie_ep ? "End Point" : "Root Complex",
 219                         (uint)pci);
 220                 if (pci->pme_msg_det) {
 221                         pci->pme_msg_det = 0xffffffff;
 222                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 223                 }
 224                 printf ("\n");
 225
 226                 /* inbound */
 227                 pci_set_region(hose->regions + 0,
 228                                CFG_PCI_MEMORY_BUS,
 229                                CFG_PCI_MEMORY_PHYS,
 230                                CFG_PCI_MEMORY_SIZE,
 231                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 232
 233                 /* outbound memory */
 234                 pci_set_region(hose->regions + 1,
 235                                CFG_PCIE1_MEM_BASE,
 236                                CFG_PCIE1_MEM_PHYS,
 237                                CFG_PCIE1_MEM_SIZE,
 238                                PCI_REGION_MEM);
 239
 240                 /* outbound io */
 241                 pci_set_region(hose->regions + 2,
 242                                CFG_PCIE1_IO_BASE,
 243                                CFG_PCIE1_IO_PHYS,
 244                                CFG_PCIE1_IO_SIZE,
 245                                PCI_REGION_IO);
 246
 247                 hose->region_count = 3;
 248 #ifdef CFG_PCIE1_MEM_BASE2
 249                 /* outbound memory */
 250                 pci_set_region(hose->regions + 3,
 251                                CFG_PCIE1_MEM_BASE2,
 252                                CFG_PCIE1_MEM_PHYS2,
 253                                CFG_PCIE1_MEM_SIZE2,
 254                                PCI_REGION_MEM);
 255                 hose->region_count++;
 256 #endif
 257                 hose->first_busno=first_free_busno;
 258
 259                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 260
 261                 fsl_pci_init(hose);
 262
 263                 first_free_busno=hose->last_busno+1;
 264                 printf("    PCIE1 on bus %02x - %02x\n",
 265                        hose->first_busno,hose->last_busno);
 266
 267         } else {
 268                 printf ("    PCIE1: disabled\n");
 269         }
 270
 271  }
 272 #else
 273         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 274 #endif
 275
 276 #ifdef CONFIG_PCI1
 277 {
 278         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 279         extern void fsl_pci_init(struct pci_controller *hose);
 280         struct pci_controller *hose = &pci1_hose;
 281
 282         uint pci_agent = (host_agent == 6);
 283         uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 284         uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;      /* PORDEVSR[15] */
 285         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 286         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 287
 288         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 289                 printf ("\n    PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 290                         (pci_32) ? 32 : 64,
 291                         (pci_speed == 33333000) ? "33" :
 292                         (pci_speed == 66666000) ? "66" : "unknown",
 293                         pci_clk_sel ? "sync" : "async",
 294                         pci_agent ? "agent" : "host",
 295                         pci_arb ? "arbiter" : "external-arbiter",
 296                         (uint)pci
 297                         );
 298
 299                 /* inbound */
 300                 pci_set_region(hose->regions + 0,
 301                                CFG_PCI_MEMORY_BUS,
 302                                CFG_PCI_MEMORY_PHYS,
 303                                CFG_PCI_MEMORY_SIZE,
 304                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 305
 306                 /* outbound memory */
 307                 pci_set_region(hose->regions + 1,
 308                                CFG_PCI1_MEM_BASE,
 309                                CFG_PCI1_MEM_PHYS,
 310                                CFG_PCI1_MEM_SIZE,
 311                                PCI_REGION_MEM);
 312
 313                 /* outbound io */
 314                 pci_set_region(hose->regions + 2,
 315                                CFG_PCI1_IO_BASE,
 316                                CFG_PCI1_IO_PHYS,
 317                                CFG_PCI1_IO_SIZE,
 318                                PCI_REGION_IO);
 319                 hose->region_count = 3;
 320                 hose->first_busno=first_free_busno;
 321                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 322
 323                 fsl_pci_init(hose);
 324                 first_free_busno=hose->last_busno+1;
 325                 printf ("PCI1 on bus %02x - %02x\n",
 326                         hose->first_busno,hose->last_busno);
 327         } else {
 328                 printf ("    PCI1: disabled\n");
 329         }
 330 }
 331 #else
 332         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 333 #endif
 334
 335 #ifdef CONFIG_PCI2
 336 {
 337         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
 338         extern void fsl_pci_init(struct pci_controller *hose);
 339         struct pci_controller *hose = &pci2_hose;
 340
 341         if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
 342                 pci_set_region(hose->regions + 0,
 343                                CFG_PCI_MEMORY_BUS,
 344                                CFG_PCI_MEMORY_PHYS,
 345                                CFG_PCI_MEMORY_SIZE,
 346                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 347
 348                 pci_set_region(hose->regions + 1,
 349                                CFG_PCI2_MEM_BASE,
 350                                CFG_PCI2_MEM_PHYS,
 351                                CFG_PCI2_MEM_SIZE,
 352                                PCI_REGION_MEM);
 353
 354                 pci_set_region(hose->regions + 2,
 355                                CFG_PCI2_IO_BASE,
 356                                CFG_PCI2_IO_PHYS,
 357                                CFG_PCI2_IO_SIZE,
 358                                PCI_REGION_IO);
 359                 hose->region_count = 3;
 360                 hose->first_busno=first_free_busno;
 361                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 362
 363                 fsl_pci_init(hose);
 364                 first_free_busno=hose->last_busno+1;
 365                 printf ("PCI2 on bus %02x - %02x\n",
 366                         hose->first_busno,hose->last_busno);
 367         } else {
 368                 printf ("    PCI2: disabled\n");
 369         }
 370 }
 371 #else
 372         gur->devdisr |= MPC85xx_DEVDISR_PCI2;
 373 #endif
 374 }
 375
 376
 377 int last_stage_init(void)
 378 {
 379         int ic = icache_status ();
 380         printf ("icache_status: %d\n", ic);
 381         return 0;
 382 }
 383
 384 #if defined(CONFIG_OF_BOARD_SETUP)
 385
 386 void
 387 ft_board_setup(void *blob, bd_t *bd)
 388 {
 389         int node, tmp[2];
 390         const char *path;
 391
 392         ft_cpu_setup(blob, bd);
 393
 394         node = fdt_path_offset(blob, "/aliases");
 395         tmp[0] = 0;
 396         if (node >= 0) {
 397 #ifdef CONFIG_PCI1
 398                 path = fdt_getprop(blob, node, "pci0", NULL);
 399                 if (path) {
 400                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 401                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 402                 }
 403 #endif
 404 #ifdef CONFIG_PCI2
 405                 path = fdt_getprop(blob, node, "pci1", NULL);
 406                 if (path) {
 407                         tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
 408                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 409                 }
 410 #endif
 411 #ifdef CONFIG_PCIE1
 412                 path = fdt_getprop(blob, node, "pci2", NULL);
 413                 if (path) {
 414                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 415                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 416                 }
 417 #endif
 418         }
 419 }
 420 #endif