]> git.kernelconcepts.de Git - karo-tx-uboot.git/blob - board/bf548-ezkit/bf548-ezkit.c
imported Ka-Ro specific additions to U-Boot 2009.08 for TX28
[karo-tx-uboot.git] / board / bf548-ezkit / bf548-ezkit.c
1 /*
2  * U-boot - main board file
3  *
4  * Copyright (c) 2005-2008 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2 or later.
7  */
8
9 #include <common.h>
10 #include <netdev.h>
11 #include <config.h>
12 #include <command.h>
13 #include <asm/blackfin.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 int checkboard(void)
18 {
19         printf("Board: ADI BF548 EZ-Kit board\n");
20         printf("       Support: http://blackfin.uclinux.org/\n");
21         return 0;
22 }
23
24 phys_size_t initdram(int board_type)
25 {
26         gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
27         gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
28         return gd->bd->bi_memsize;
29 }
30
31 int board_early_init_f(void)
32 {
33         /* Port H: PH8 - PH13 == A4 - A9
34          * address lines of the parallel asynchronous memory interface
35          */
36
37         /************************************************
38         * configure GPIO                                *
39         * set port H function enable register           *
40         *  configure PH8-PH13 as peripheral (not GPIO)  *
41         *************************************************/
42         bfin_write_PORTH_FER(0x3F03);
43
44         /************************************************
45         * set port H MUX to configure PH8-PH13          *
46         *  1st Function (MUX = 00) (bits 16-27 == 0)    *
47         *  Set to address signals A4-A9                 *
48         *************************************************/
49         bfin_write_PORTH_MUX(0);
50
51         /************************************************
52         * set port H direction register                 *
53         *  enable PH8-PH13 as outputs                   *
54         *************************************************/
55         bfin_write_PORTH_DIR_SET(0x3F00);
56
57         /* Port I: PI0 - PH14 == A10 - A24
58          * address lines of the parallel asynchronous memory interface
59          */
60
61         /************************************************
62         * set port I function enable register           *
63         *  configure PI0-PI14 as peripheral (not GPIO)  *
64         *************************************************/
65         bfin_write_PORTI_FER(0x7fff);
66
67         /**************************************************
68         * set PORT I MUX to configure PI14-PI0 as         *
69         * 1st Function (MUX=00) - address signals A10-A24 *
70         ***************************************************/
71         bfin_write_PORTI_MUX(0);
72
73         /****************************************
74         * set PORT I direction register         *
75         *  enable PI0 - PI14 as outputs         *
76         *****************************************/
77         bfin_write_PORTI_DIR_SET(0x7fff);
78
79         return 0;
80 }
81
82 #ifdef CONFIG_SMC911X
83 int board_eth_init(bd_t *bis)
84 {
85         return smc911x_initialize(0, CONFIG_SMC911X_BASE);
86 }
87 #endif