board/boundary/nitrogen6x/nitrogen6x.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <malloc.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/imx-common/iomux-v3.h>
  19 #include <asm/imx-common/mxc_i2c.h>
  20 #include <asm/imx-common/sata.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/video.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <micrel.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <i2c.h>
  31 #include <input.h>
  32 #include <netdev.h>
  33 #include <usb/ehci-fsl.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  50         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  51
  52 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  58
  59 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  65         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  66
  67 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  72
  73         return 0;
  74 }
  75
  76 static iomux_v3_cfg_t const uart1_pads[] = {
  77         MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const uart2_pads[] = {
  82         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84 };
  85
  86 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  87
  88 /* I2C1, SGTL5000 */
  89 static struct i2c_pads_info i2c_pad_info0 = {
  90         .scl = {
  91                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  92                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  93                 .gp = IMX_GPIO_NR(3, 21)
  94         },
  95         .sda = {
  96                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  97                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  98                 .gp = IMX_GPIO_NR(3, 28)
  99         }
 100 };
 101
 102 /* I2C2 Camera, MIPI */
 103 static struct i2c_pads_info i2c_pad_info1 = {
 104         .scl = {
 105                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 106                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 107                 .gp = IMX_GPIO_NR(4, 12)
 108         },
 109         .sda = {
 110                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 111                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 112                 .gp = IMX_GPIO_NR(4, 13)
 113         }
 114 };
 115
 116 /* I2C3, J15 - RGB connector */
 117 static struct i2c_pads_info i2c_pad_info2 = {
 118         .scl = {
 119                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
 120                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
 121                 .gp = IMX_GPIO_NR(1, 5)
 122         },
 123         .sda = {
 124                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
 125                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
 126                 .gp = IMX_GPIO_NR(7, 11)
 127         }
 128 };
 129
 130 static iomux_v3_cfg_t const usdhc2_pads[] = {
 131         MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137 };
 138
 139 static iomux_v3_cfg_t const usdhc3_pads[] = {
 140         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 147 };
 148
 149 static iomux_v3_cfg_t const usdhc4_pads[] = {
 150         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 157 };
 158
 159 static iomux_v3_cfg_t const enet_pads1[] = {
 160         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         /* pin 35 - 1 (PHY_AD2) on reset */
 170         MX6_PAD_RGMII_RXC__GPIO6_IO30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         /* pin 32 - 1 - (MODE0) all */
 172         MX6_PAD_RGMII_RD0__GPIO6_IO25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 173         /* pin 31 - 1 - (MODE1) all */
 174         MX6_PAD_RGMII_RD1__GPIO6_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         /* pin 28 - 1 - (MODE2) all */
 176         MX6_PAD_RGMII_RD2__GPIO6_IO28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 177         /* pin 27 - 1 - (MODE3) all */
 178         MX6_PAD_RGMII_RD3__GPIO6_IO29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 179         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 180         MX6_PAD_RGMII_RX_CTL__GPIO6_IO24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 181         /* pin 42 PHY nRST */
 182         MX6_PAD_EIM_D23__GPIO3_IO23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 183         MX6_PAD_ENET_RXD0__GPIO1_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 184 };
 185
 186 static iomux_v3_cfg_t const enet_pads2[] = {
 187         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 189         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 190         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 192         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 193 };
 194
 195 static iomux_v3_cfg_t const misc_pads[] = {
 196         MX6_PAD_GPIO_1__USB_OTG_ID              | MUX_PAD_CTRL(WEAK_PULLUP),
 197         MX6_PAD_KEY_COL4__USB_OTG_OC            | MUX_PAD_CTRL(WEAK_PULLUP),
 198         MX6_PAD_EIM_D30__USB_H1_OC              | MUX_PAD_CTRL(WEAK_PULLUP),
 199         /* OTG Power enable */
 200         MX6_PAD_EIM_D22__GPIO3_IO22             | MUX_PAD_CTRL(OUTPUT_40OHM),
 201 };
 202
 203 /* wl1271 pads on nitrogen6x */
 204 static iomux_v3_cfg_t const wl12xx_pads[] = {
 205         (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
 206                 | MUX_PAD_CTRL(WEAK_PULLDOWN),
 207         (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
 208                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 209         (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
 210                 | MUX_PAD_CTRL(OUTPUT_40OHM),
 211 };
 212 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 213 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 214 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 215
 216 /* Button assignments for J14 */
 217 static iomux_v3_cfg_t const button_pads[] = {
 218         /* Menu */
 219         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 220         /* Back */
 221         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 222         /* Labelled Search (mapped to Power under Android) */
 223         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 224         /* Home */
 225         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 226         /* Volume Down */
 227         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 228         /* Volume Up */
 229         MX6_PAD_GPIO_18__GPIO7_IO13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 230 };
 231
 232 static void setup_iomux_enet(void)
 233 {
 234         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 235         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 236         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 237         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 238         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 239         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 240         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 241         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 242         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 243
 244         /* Need delay 10ms according to KSZ9021 spec */
 245         udelay(1000 * 10);
 246         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 247         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 248
 249         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 250         udelay(100);    /* Wait 100 us before using mii interface */
 251 }
 252
 253 static iomux_v3_cfg_t const usb_pads[] = {
 254         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 255 };
 256
 257 static void setup_iomux_uart(void)
 258 {
 259         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 260         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 261 }
 262
 263 #ifdef CONFIG_USB_EHCI_MX6
 264 int board_ehci_hcd_init(int port)
 265 {
 266         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 267
 268         /* Reset USB hub */
 269         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 270         mdelay(2);
 271         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 272
 273         return 0;
 274 }
 275
 276 int board_ehci_power(int port, int on)
 277 {
 278         if (port)
 279                 return 0;
 280         gpio_set_value(GP_USB_OTG_PWR, on);
 281         return 0;
 282 }
 283
 284 #endif
 285
 286 #ifdef CONFIG_FSL_ESDHC
 287 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 288         {USDHC3_BASE_ADDR},
 289         {USDHC4_BASE_ADDR},
 290 };
 291
 292 int board_mmc_getcd(struct mmc *mmc)
 293 {
 294         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 295         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 296                         IMX_GPIO_NR(2, 6);
 297
 298         gpio_direction_input(gp_cd);
 299         return !gpio_get_value(gp_cd);
 300 }
 301
 302 int board_mmc_init(bd_t *bis)
 303 {
 304         s32 status = 0;
 305         u32 index = 0;
 306
 307         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 308         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 309
 310         usdhc_cfg[0].max_bus_width = 4;
 311         usdhc_cfg[1].max_bus_width = 4;
 312
 313         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 314                 switch (index) {
 315                 case 0:
 316                         imx_iomux_v3_setup_multiple_pads(
 317                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 318                         break;
 319                 case 1:
 320                        imx_iomux_v3_setup_multiple_pads(
 321                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 322                        break;
 323                 default:
 324                        printf("Warning: you configured more USDHC controllers"
 325                                "(%d) then supported by the board (%d)\n",
 326                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 327                        return status;
 328                 }
 329
 330                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 331         }
 332
 333         return status;
 334 }
 335 #endif
 336
 337 #ifdef CONFIG_MXC_SPI
 338 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 339 {
 340         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 341 }
 342
 343 static iomux_v3_cfg_t const ecspi1_pads[] = {
 344         /* SS1 */
 345         MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
 346         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 347         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 348         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 349 };
 350
 351 static void setup_spi(void)
 352 {
 353         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 354                                          ARRAY_SIZE(ecspi1_pads));
 355 }
 356 #endif
 357
 358 int board_phy_config(struct phy_device *phydev)
 359 {
 360         /* min rx data delay */
 361         ksz9021_phy_extended_write(phydev,
 362                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 363         /* min tx data delay */
 364         ksz9021_phy_extended_write(phydev,
 365                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 366         /* max rx/tx clock delay, min rx/tx control */
 367         ksz9021_phy_extended_write(phydev,
 368                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 369         if (phydev->drv->config)
 370                 phydev->drv->config(phydev);
 371
 372         return 0;
 373 }
 374
 375 int board_eth_init(bd_t *bis)
 376 {
 377         uint32_t base = IMX_FEC_BASE;
 378         struct mii_dev *bus = NULL;
 379         struct phy_device *phydev = NULL;
 380         int ret;
 381
 382         setup_iomux_enet();
 383
 384 #ifdef CONFIG_FEC_MXC
 385         bus = fec_get_miibus(base, -1);
 386         if (!bus)
 387                 return 0;
 388         /* scan phy 4,5,6,7 */
 389         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 390         if (!phydev) {
 391                 free(bus);
 392                 return 0;
 393         }
 394         printf("using phy at %d\n", phydev->addr);
 395         ret  = fec_probe(bis, -1, base, bus, phydev);
 396         if (ret) {
 397                 printf("FEC MXC: %s:failed\n", __func__);
 398                 free(phydev);
 399                 free(bus);
 400         }
 401 #endif
 402
 403 #ifdef CONFIG_CI_UDC
 404         /* For otg ethernet*/
 405         usb_eth_initialize(bis);
 406 #endif
 407         return 0;
 408 }
 409
 410 static void setup_buttons(void)
 411 {
 412         imx_iomux_v3_setup_multiple_pads(button_pads,
 413                                          ARRAY_SIZE(button_pads));
 414 }
 415
 416 #if defined(CONFIG_VIDEO_IPUV3)
 417
 418 static iomux_v3_cfg_t const backlight_pads[] = {
 419         /* Backlight on RGB connector: J15 */
 420         MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 421 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 422
 423         /* Backlight on LVDS connector: J6 */
 424         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 425 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 426 };
 427
 428 static iomux_v3_cfg_t const rgb_pads[] = {
 429         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 430         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 431         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 432         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 433         MX6_PAD_DI0_PIN4__GPIO4_IO20,
 434         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 435         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 436         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 437         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 438         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 439         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 440         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 441         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 442         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 443         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 444         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 445         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 446         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 447         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 448         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 449         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 450         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 451         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 452         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 453         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 454         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 455         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 456         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 457         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 458 };
 459
 460 static void do_enable_hdmi(struct display_info_t const *dev)
 461 {
 462         imx_enable_hdmi_phy();
 463 }
 464
 465 static int detect_i2c(struct display_info_t const *dev)
 466 {
 467         return ((0 == i2c_set_bus_num(dev->bus))
 468                 &&
 469                 (0 == i2c_probe(dev->addr)));
 470 }
 471
 472 static void enable_lvds(struct display_info_t const *dev)
 473 {
 474         struct iomuxc *iomux = (struct iomuxc *)
 475                                 IOMUXC_BASE_ADDR;
 476         u32 reg = readl(&iomux->gpr[2]);
 477         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 478         writel(reg, &iomux->gpr[2]);
 479         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 480 }
 481
 482 static void enable_lvds_jeida(struct display_info_t const *dev)
 483 {
 484         struct iomuxc *iomux = (struct iomuxc *)
 485                                 IOMUXC_BASE_ADDR;
 486         u32 reg = readl(&iomux->gpr[2]);
 487         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 488              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 489         writel(reg, &iomux->gpr[2]);
 490         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 491 }
 492
 493 static void enable_rgb(struct display_info_t const *dev)
 494 {
 495         imx_iomux_v3_setup_multiple_pads(
 496                 rgb_pads,
 497                  ARRAY_SIZE(rgb_pads));
 498         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 499 }
 500
 501 struct display_info_t const displays[] = {{
 502         .bus    = 1,
 503         .addr   = 0x50,
 504         .pixfmt = IPU_PIX_FMT_RGB24,
 505         .detect = detect_i2c,
 506         .enable = do_enable_hdmi,
 507         .mode   = {
 508                 .name           = "HDMI",
 509                 .refresh        = 60,
 510                 .xres           = 1024,
 511                 .yres           = 768,
 512                 .pixclock       = 15385,
 513                 .left_margin    = 220,
 514                 .right_margin   = 40,
 515                 .upper_margin   = 21,
 516                 .lower_margin   = 7,
 517                 .hsync_len      = 60,
 518                 .vsync_len      = 10,
 519                 .sync           = FB_SYNC_EXT,
 520                 .vmode          = FB_VMODE_NONINTERLACED
 521 } }, {
 522         .bus    = 0,
 523         .addr   = 0,
 524         .pixfmt = IPU_PIX_FMT_RGB24,
 525         .detect = NULL,
 526         .enable = enable_lvds_jeida,
 527         .mode   = {
 528                 .name           = "LDB-WXGA",
 529                 .refresh        = 60,
 530                 .xres           = 1280,
 531                 .yres           = 800,
 532                 .pixclock       = 14065,
 533                 .left_margin    = 40,
 534                 .right_margin   = 40,
 535                 .upper_margin   = 3,
 536                 .lower_margin   = 80,
 537                 .hsync_len      = 10,
 538                 .vsync_len      = 10,
 539                 .sync           = FB_SYNC_EXT,
 540                 .vmode          = FB_VMODE_NONINTERLACED
 541 } }, {
 542         .bus    = 0,
 543         .addr   = 0,
 544         .pixfmt = IPU_PIX_FMT_RGB24,
 545         .detect = NULL,
 546         .enable = enable_lvds,
 547         .mode   = {
 548                 .name           = "LDB-WXGA-S",
 549                 .refresh        = 60,
 550                 .xres           = 1280,
 551                 .yres           = 800,
 552                 .pixclock       = 14065,
 553                 .left_margin    = 40,
 554                 .right_margin   = 40,
 555                 .upper_margin   = 3,
 556                 .lower_margin   = 80,
 557                 .hsync_len      = 10,
 558                 .vsync_len      = 10,
 559                 .sync           = FB_SYNC_EXT,
 560                 .vmode          = FB_VMODE_NONINTERLACED
 561 } }, {
 562         .bus    = 2,
 563         .addr   = 0x4,
 564         .pixfmt = IPU_PIX_FMT_LVDS666,
 565         .detect = detect_i2c,
 566         .enable = enable_lvds,
 567         .mode   = {
 568                 .name           = "Hannstar-XGA",
 569                 .refresh        = 60,
 570                 .xres           = 1024,
 571                 .yres           = 768,
 572                 .pixclock       = 15385,
 573                 .left_margin    = 220,
 574                 .right_margin   = 40,
 575                 .upper_margin   = 21,
 576                 .lower_margin   = 7,
 577                 .hsync_len      = 60,
 578                 .vsync_len      = 10,
 579                 .sync           = FB_SYNC_EXT,
 580                 .vmode          = FB_VMODE_NONINTERLACED
 581 } }, {
 582         .bus    = 0,
 583         .addr   = 0,
 584         .pixfmt = IPU_PIX_FMT_LVDS666,
 585         .detect = NULL,
 586         .enable = enable_lvds,
 587         .mode   = {
 588                 .name           = "LG-9.7",
 589                 .refresh        = 60,
 590                 .xres           = 1024,
 591                 .yres           = 768,
 592                 .pixclock       = 15385, /* ~65MHz */
 593                 .left_margin    = 480,
 594                 .right_margin   = 260,
 595                 .upper_margin   = 16,
 596                 .lower_margin   = 6,
 597                 .hsync_len      = 250,
 598                 .vsync_len      = 10,
 599                 .sync           = FB_SYNC_EXT,
 600                 .vmode          = FB_VMODE_NONINTERLACED
 601 } }, {
 602         .bus    = 2,
 603         .addr   = 0x38,
 604         .pixfmt = IPU_PIX_FMT_LVDS666,
 605         .detect = detect_i2c,
 606         .enable = enable_lvds,
 607         .mode   = {
 608                 .name           = "wsvga-lvds",
 609                 .refresh        = 60,
 610                 .xres           = 1024,
 611                 .yres           = 600,
 612                 .pixclock       = 15385,
 613                 .left_margin    = 220,
 614                 .right_margin   = 40,
 615                 .upper_margin   = 21,
 616                 .lower_margin   = 7,
 617                 .hsync_len      = 60,
 618                 .vsync_len      = 10,
 619                 .sync           = FB_SYNC_EXT,
 620                 .vmode          = FB_VMODE_NONINTERLACED
 621 } }, {
 622         .bus    = 2,
 623         .addr   = 0x10,
 624         .pixfmt = IPU_PIX_FMT_RGB666,
 625         .detect = detect_i2c,
 626         .enable = enable_rgb,
 627         .mode   = {
 628                 .name           = "fusion7",
 629                 .refresh        = 60,
 630                 .xres           = 800,
 631                 .yres           = 480,
 632                 .pixclock       = 33898,
 633                 .left_margin    = 96,
 634                 .right_margin   = 24,
 635                 .upper_margin   = 3,
 636                 .lower_margin   = 10,
 637                 .hsync_len      = 72,
 638                 .vsync_len      = 7,
 639                 .sync           = 0x40000002,
 640                 .vmode          = FB_VMODE_NONINTERLACED
 641 } }, {
 642         .bus    = 0,
 643         .addr   = 0,
 644         .pixfmt = IPU_PIX_FMT_RGB666,
 645         .detect = NULL,
 646         .enable = enable_rgb,
 647         .mode   = {
 648                 .name           = "svga",
 649                 .refresh        = 60,
 650                 .xres           = 800,
 651                 .yres           = 600,
 652                 .pixclock       = 15385,
 653                 .left_margin    = 220,
 654                 .right_margin   = 40,
 655                 .upper_margin   = 21,
 656                 .lower_margin   = 7,
 657                 .hsync_len      = 60,
 658                 .vsync_len      = 10,
 659                 .sync           = 0,
 660                 .vmode          = FB_VMODE_NONINTERLACED
 661 } }, {
 662         .bus    = 2,
 663         .addr   = 0x41,
 664         .pixfmt = IPU_PIX_FMT_LVDS666,
 665         .detect = detect_i2c,
 666         .enable = enable_lvds,
 667         .mode   = {
 668                 .name           = "amp1024x600",
 669                 .refresh        = 60,
 670                 .xres           = 1024,
 671                 .yres           = 600,
 672                 .pixclock       = 15385,
 673                 .left_margin    = 220,
 674                 .right_margin   = 40,
 675                 .upper_margin   = 21,
 676                 .lower_margin   = 7,
 677                 .hsync_len      = 60,
 678                 .vsync_len      = 10,
 679                 .sync           = FB_SYNC_EXT,
 680                 .vmode          = FB_VMODE_NONINTERLACED
 681 } }, {
 682         .bus    = 0,
 683         .addr   = 0,
 684         .pixfmt = IPU_PIX_FMT_LVDS666,
 685         .detect = 0,
 686         .enable = enable_lvds,
 687         .mode   = {
 688                 .name           = "wvga-lvds",
 689                 .refresh        = 57,
 690                 .xres           = 800,
 691                 .yres           = 480,
 692                 .pixclock       = 15385,
 693                 .left_margin    = 220,
 694                 .right_margin   = 40,
 695                 .upper_margin   = 21,
 696                 .lower_margin   = 7,
 697                 .hsync_len      = 60,
 698                 .vsync_len      = 10,
 699                 .sync           = FB_SYNC_EXT,
 700                 .vmode          = FB_VMODE_NONINTERLACED
 701 } }, {
 702         .bus    = 2,
 703         .addr   = 0x48,
 704         .pixfmt = IPU_PIX_FMT_RGB666,
 705         .detect = detect_i2c,
 706         .enable = enable_rgb,
 707         .mode   = {
 708                 .name           = "wvga-rgb",
 709                 .refresh        = 57,
 710                 .xres           = 800,
 711                 .yres           = 480,
 712                 .pixclock       = 37037,
 713                 .left_margin    = 40,
 714                 .right_margin   = 60,
 715                 .upper_margin   = 10,
 716                 .lower_margin   = 10,
 717                 .hsync_len      = 20,
 718                 .vsync_len      = 10,
 719                 .sync           = 0,
 720                 .vmode          = FB_VMODE_NONINTERLACED
 721 } }, {
 722         .bus    = 0,
 723         .addr   = 0,
 724         .pixfmt = IPU_PIX_FMT_RGB24,
 725         .detect = NULL,
 726         .enable = enable_rgb,
 727         .mode   = {
 728                 .name           = "qvga",
 729                 .refresh        = 60,
 730                 .xres           = 320,
 731                 .yres           = 240,
 732                 .pixclock       = 37037,
 733                 .left_margin    = 38,
 734                 .right_margin   = 37,
 735                 .upper_margin   = 16,
 736                 .lower_margin   = 15,
 737                 .hsync_len      = 30,
 738                 .vsync_len      = 3,
 739                 .sync           = 0,
 740                 .vmode          = FB_VMODE_NONINTERLACED
 741 } } };
 742 size_t display_count = ARRAY_SIZE(displays);
 743
 744 int board_cfb_skip(void)
 745 {
 746         return NULL != getenv("novideo");
 747 }
 748
 749 static void setup_display(void)
 750 {
 751         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 752         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 753         int reg;
 754
 755         enable_ipu_clock();
 756         imx_setup_hdmi();
 757         /* Turn on LDB0,IPU,IPU DI0 clocks */
 758         reg = __raw_readl(&mxc_ccm->CCGR3);
 759         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 760         writel(reg, &mxc_ccm->CCGR3);
 761
 762         /* set LDB0, LDB1 clk select to 011/011 */
 763         reg = readl(&mxc_ccm->cs2cdr);
 764         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 765                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 766         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 767               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 768         writel(reg, &mxc_ccm->cs2cdr);
 769
 770         reg = readl(&mxc_ccm->cscmr2);
 771         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 772         writel(reg, &mxc_ccm->cscmr2);
 773
 774         reg = readl(&mxc_ccm->chsccdr);
 775         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 776                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 777         writel(reg, &mxc_ccm->chsccdr);
 778
 779         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 780              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 781              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 782              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 783              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 784              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 785              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 786              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 787              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 788         writel(reg, &iomux->gpr[2]);
 789
 790         reg = readl(&iomux->gpr[3]);
 791         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 792                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 793             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 794                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 795         writel(reg, &iomux->gpr[3]);
 796
 797         /* backlights off until needed */
 798         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 799                                          ARRAY_SIZE(backlight_pads));
 800         gpio_direction_input(LVDS_BACKLIGHT_GP);
 801         gpio_direction_input(RGB_BACKLIGHT_GP);
 802 }
 803 #endif
 804
 805 static iomux_v3_cfg_t const init_pads[] = {
 806         /* SGTL5000 sys_mclk */
 807         NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 808
 809         /* J5 - Camera MCLK */
 810         NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 811
 812         /* wl1271 pads on nitrogen6x */
 813         /* WL12XX_WL_IRQ_GP */
 814         NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 815         /* WL12XX_WL_ENABLE_GP */
 816         NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 817         /* WL12XX_BT_ENABLE_GP */
 818         NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 819         /* USB otg power */
 820         NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 821         NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 822         NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 823         NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 824         NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 825 };
 826
 827 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 828
 829 static unsigned gpios_out_low[] = {
 830         /* Disable wl1271 */
 831         IMX_GPIO_NR(6, 15),     /* disable wireless */
 832         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 833         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 834         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 835         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 836 };
 837
 838 static unsigned gpios_out_high[] = {
 839         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 840         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 841 };
 842
 843 static void set_gpios(unsigned *p, int cnt, int val)
 844 {
 845         int i;
 846
 847         for (i = 0; i < cnt; i++)
 848                 gpio_direction_output(*p++, val);
 849 }
 850
 851 int board_early_init_f(void)
 852 {
 853         setup_iomux_uart();
 854
 855         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 856         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 857         gpio_direction_input(WL12XX_WL_IRQ_GP);
 858
 859         imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
 860         imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
 861         setup_buttons();
 862
 863 #if defined(CONFIG_VIDEO_IPUV3)
 864         setup_display();
 865 #endif
 866         return 0;
 867 }
 868
 869 /*
 870  * Do not overwrite the console
 871  * Use always serial for U-Boot console
 872  */
 873 int overwrite_console(void)
 874 {
 875         return 1;
 876 }
 877
 878 int board_init(void)
 879 {
 880         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 881
 882         clrsetbits_le32(&iomuxc_regs->gpr[1],
 883                         IOMUXC_GPR1_OTG_ID_MASK,
 884                         IOMUXC_GPR1_OTG_ID_GPIO1);
 885
 886         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 887
 888         /* address of boot parameters */
 889         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 890
 891 #ifdef CONFIG_MXC_SPI
 892         setup_spi();
 893 #endif
 894         imx_iomux_v3_setup_multiple_pads(
 895                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 896         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 897         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 898         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 899
 900 #ifdef CONFIG_CMD_SATA
 901         setup_sata();
 902 #endif
 903
 904         return 0;
 905 }
 906
 907 int checkboard(void)
 908 {
 909         if (gpio_get_value(WL12XX_WL_IRQ_GP))
 910                 puts("Board: Nitrogen6X\n");
 911         else
 912                 puts("Board: SABRE Lite\n");
 913
 914         return 0;
 915 }
 916
 917 struct button_key {
 918         char const      *name;
 919         unsigned        gpnum;
 920         char            ident;
 921 };
 922
 923 static struct button_key const buttons[] = {
 924         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 925         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 926         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 927         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 928         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 929         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 930 };
 931
 932 /*
 933  * generate a null-terminated string containing the buttons pressed
 934  * returns number of keys pressed
 935  */
 936 static int read_keys(char *buf)
 937 {
 938         int i, numpressed = 0;
 939         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 940                 if (!gpio_get_value(buttons[i].gpnum))
 941                         buf[numpressed++] = buttons[i].ident;
 942         }
 943         buf[numpressed] = '\0';
 944         return numpressed;
 945 }
 946
 947 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 948 {
 949         char envvalue[ARRAY_SIZE(buttons)+1];
 950         int numpressed = read_keys(envvalue);
 951         setenv("keybd", envvalue);
 952         return numpressed == 0;
 953 }
 954
 955 U_BOOT_CMD(
 956         kbd, 1, 1, do_kbd,
 957         "Tests for keypresses, sets 'keybd' environment variable",
 958         "Returns 0 (true) to shell if key is pressed."
 959 );
 960
 961 #ifdef CONFIG_PREBOOT
 962 static char const kbd_magic_prefix[] = "key_magic";
 963 static char const kbd_command_prefix[] = "key_cmd";
 964
 965 static void preboot_keys(void)
 966 {
 967         int numpressed;
 968         char keypress[ARRAY_SIZE(buttons)+1];
 969         numpressed = read_keys(keypress);
 970         if (numpressed) {
 971                 char *kbd_magic_keys = getenv("magic_keys");
 972                 char *suffix;
 973                 /*
 974                  * loop over all magic keys
 975                  */
 976                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 977                         char *keys;
 978                         char magic[sizeof(kbd_magic_prefix) + 1];
 979                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 980                         keys = getenv(magic);
 981                         if (keys) {
 982                                 if (!strcmp(keys, keypress))
 983                                         break;
 984                         }
 985                 }
 986                 if (*suffix) {
 987                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 988                         char *cmd;
 989                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 990                         cmd = getenv(cmd_name);
 991                         if (cmd) {
 992                                 setenv("preboot", cmd);
 993                                 return;
 994                         }
 995                 }
 996         }
 997 }
 998 #endif
 999
1000 #ifdef CONFIG_CMD_BMODE
1001 static const struct boot_mode board_boot_modes[] = {
1002         /* 4 bit bus width */
1003         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1004         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1005         {NULL,          0},
1006 };
1007 #endif
1008
1009 int misc_init_r(void)
1010 {
1011 #ifdef CONFIG_PREBOOT
1012         preboot_keys();
1013 #endif
1014
1015 #ifdef CONFIG_CMD_BMODE
1016         add_board_boot_modes(board_boot_modes);
1017 #endif
1018         return 0;
1019 }