board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <fsl_esdhc.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <fdt_support.h>
  16 #include <sata.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/sata.h>
  22 #include <asm/io.h>
  23 #include <asm/gpio.h>
  24 #include "common.h"
  25 #include "../common/eeprom.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_DWC_AHSATA
  30 static int cm_fx6_issd_gpios[] = {
  31         /* The order of the GPIOs in the array is important! */
  32         CM_FX6_SATA_PHY_SLP,
  33         CM_FX6_SATA_NRSTDLY,
  34         CM_FX6_SATA_PWREN,
  35         CM_FX6_SATA_NSTANDBY1,
  36         CM_FX6_SATA_NSTANDBY2,
  37         CM_FX6_SATA_LDO_EN,
  38 };
  39
  40 static void cm_fx6_sata_power(int on)
  41 {
  42         int i;
  43
  44         if (!on) { /* tell the iSSD that the power will be removed */
  45                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
  46                 mdelay(10);
  47         }
  48
  49         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  50                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
  51                 udelay(100);
  52         }
  53
  54         if (!on) /* for compatibility lower the power loss interrupt */
  55                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  56 }
  57
  58 static iomux_v3_cfg_t const sata_pads[] = {
  59         /* SATA PWR */
  60         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  61         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  62         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  63         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  64         /* SATA CTRL */
  65         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  66         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  67         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  68         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  70 };
  71
  72 static int cm_fx6_setup_issd(void)
  73 {
  74         int ret, i;
  75
  76         SETUP_IOMUX_PADS(sata_pads);
  77
  78         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
  79                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
  80                 if (ret)
  81                         return ret;
  82         }
  83
  84         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
  85         if (ret)
  86                 return ret;
  87
  88         return 0;
  89 }
  90
  91 #define CM_FX6_SATA_INIT_RETRIES        10
  92 int sata_initialize(void)
  93 {
  94         int err, i;
  95
  96         /* Make sure this gpio has logical 0 value */
  97         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
  98         udelay(100);
  99
 100         cm_fx6_sata_power(0);
 101         mdelay(250);
 102         cm_fx6_sata_power(1);
 103
 104         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 105                 err = setup_sata();
 106                 if (err) {
 107                         printf("SATA setup failed: %d\n", err);
 108                         return err;
 109                 }
 110
 111                 udelay(100);
 112
 113                 err = __sata_initialize();
 114                 if (!err)
 115                         break;
 116
 117                 /* There is no device on the SATA port */
 118                 if (sata_port_status(0, 0) == 0)
 119                         break;
 120
 121                 /* There's a device, but link not established. Retry */
 122         }
 123
 124         return err;
 125 }
 126 #else
 127 static int cm_fx6_setup_issd(void) { return 0; }
 128 #endif
 129
 130 #ifdef CONFIG_SYS_I2C_MXC
 131 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 132                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 133                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 134
 135 I2C_PADS(i2c0_pads,
 136          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 137          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 138          IMX_GPIO_NR(3, 21),
 139          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 140          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 141          IMX_GPIO_NR(3, 28));
 142
 143 I2C_PADS(i2c1_pads,
 144          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 145          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 146          IMX_GPIO_NR(4, 12),
 147          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 148          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 149          IMX_GPIO_NR(4, 13));
 150
 151 I2C_PADS(i2c2_pads,
 152          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 153          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 154          IMX_GPIO_NR(1, 3),
 155          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 156          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 157          IMX_GPIO_NR(1, 6));
 158
 159
 160 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 161 {
 162         int ret;
 163
 164         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 165         if (ret)
 166                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 167
 168         return ret;
 169 }
 170
 171 static int cm_fx6_setup_i2c(void)
 172 {
 173         int ret = 0, err;
 174
 175         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 176         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 177         if (err)
 178                 ret = err;
 179         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 180         if (err)
 181                 ret = err;
 182         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 183         if (err)
 184                 ret = err;
 185
 186         return ret;
 187 }
 188 #else
 189 static int cm_fx6_setup_i2c(void) { return 0; }
 190 #endif
 191
 192 #ifdef CONFIG_USB_EHCI_MX6
 193 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 194                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 195                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 196 #define MX6_USBNC_BASEADDR      0x2184800
 197 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 198
 199 static int cm_fx6_setup_usb_host(void)
 200 {
 201         int err;
 202
 203         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 204         if (err)
 205                 return err;
 206
 207         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 208         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 209
 210         return 0;
 211 }
 212
 213 static int cm_fx6_setup_usb_otg(void)
 214 {
 215         int err;
 216         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 217
 218         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 219         if (err) {
 220                 printf("USB OTG pwr gpio request failed: %d\n", err);
 221                 return err;
 222         }
 223
 224         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 225         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 226                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 227         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 228         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 229         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 230 }
 231
 232 int board_ehci_hcd_init(int port)
 233 {
 234         int ret;
 235         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 236
 237         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 238         if (port != 1)
 239                 return 0;
 240
 241         /* Set PWR polarity to match power switch's enable polarity */
 242         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 243         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 244         if (ret)
 245                 return ret;
 246
 247         udelay(10);
 248         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 249         if (ret)
 250                 return ret;
 251
 252         mdelay(1);
 253
 254         return 0;
 255 }
 256
 257 int board_ehci_power(int port, int on)
 258 {
 259         if (port == 0)
 260                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 261
 262         return 0;
 263 }
 264 #else
 265 static int cm_fx6_setup_usb_otg(void) { return 0; }
 266 static int cm_fx6_setup_usb_host(void) { return 0; }
 267 #endif
 268
 269 #ifdef CONFIG_FEC_MXC
 270 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 271                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 272
 273 static int mx6_rgmii_rework(struct phy_device *phydev)
 274 {
 275         unsigned short val;
 276
 277         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 278          * which cause ethernet link down/up issue, so disable SmartEEE
 279          */
 280         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 281         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 282         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 283         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 284         val &= ~(0x1 << 8);
 285         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 286
 287         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 288         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 289         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 290         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 291
 292         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 293         val &= 0xffe3;
 294         val |= 0x18;
 295         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 296
 297         /* introduce tx clock delay */
 298         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 299         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 300         val |= 0x0100;
 301         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 302
 303         return 0;
 304 }
 305
 306 int board_phy_config(struct phy_device *phydev)
 307 {
 308         mx6_rgmii_rework(phydev);
 309
 310         if (phydev->drv->config)
 311                 return phydev->drv->config(phydev);
 312
 313         return 0;
 314 }
 315
 316 static iomux_v3_cfg_t const enet_pads[] = {
 317         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 318         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 319         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 320         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 321         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 322         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 323         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 324         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 325         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 326         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 327         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 328         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 329         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 330         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 331         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 332         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 333                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 334         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 335                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 336         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 337                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 338 };
 339
 340 static int handle_mac_address(void)
 341 {
 342         unsigned char enetaddr[6];
 343         int rc;
 344
 345         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 346         if (rc)
 347                 return 0;
 348
 349         rc = cl_eeprom_read_mac_addr(enetaddr);
 350         if (rc)
 351                 return rc;
 352
 353         if (!is_valid_ether_addr(enetaddr))
 354                 return -1;
 355
 356         return eth_setenv_enetaddr("ethaddr", enetaddr);
 357 }
 358
 359 int board_eth_init(bd_t *bis)
 360 {
 361         int err;
 362
 363         err = handle_mac_address();
 364         if (err)
 365                 puts("No MAC address found\n");
 366
 367         SETUP_IOMUX_PADS(enet_pads);
 368         /* phy reset */
 369         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 370         if (err)
 371                 printf("Etnernet NRST gpio request failed: %d\n", err);
 372         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 373         udelay(500);
 374         gpio_set_value(CM_FX6_ENET_NRST, 1);
 375         enable_enet_clk(1);
 376         return cpu_eth_init(bis);
 377 }
 378 #endif
 379
 380 #ifdef CONFIG_NAND_MXS
 381 static iomux_v3_cfg_t const nand_pads[] = {
 382         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 383         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 384         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 385         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 386         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 387         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 388         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 389         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 390         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 391         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 392         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 393         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 394         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 395         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 396 };
 397
 398 static void cm_fx6_setup_gpmi_nand(void)
 399 {
 400         SETUP_IOMUX_PADS(nand_pads);
 401         /* Enable clock roots */
 402         enable_usdhc_clk(1, 3);
 403         enable_usdhc_clk(1, 4);
 404
 405         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 406                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 407                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 408 }
 409 #else
 410 static void cm_fx6_setup_gpmi_nand(void) {}
 411 #endif
 412
 413 #ifdef CONFIG_FSL_ESDHC
 414 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 415         {USDHC1_BASE_ADDR},
 416         {USDHC2_BASE_ADDR},
 417         {USDHC3_BASE_ADDR},
 418 };
 419
 420 static enum mxc_clock usdhc_clk[3] = {
 421         MXC_ESDHC_CLK,
 422         MXC_ESDHC2_CLK,
 423         MXC_ESDHC3_CLK,
 424 };
 425
 426 int board_mmc_init(bd_t *bis)
 427 {
 428         int i;
 429
 430         cm_fx6_set_usdhc_iomux();
 431         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 432                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 433                 usdhc_cfg[i].max_bus_width = 4;
 434                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 435                 enable_usdhc_clk(1, i);
 436         }
 437
 438         return 0;
 439 }
 440 #endif
 441
 442 #ifdef CONFIG_MXC_SPI
 443 int cm_fx6_setup_ecspi(void)
 444 {
 445         cm_fx6_set_ecspi_iomux();
 446         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 447 }
 448 #else
 449 int cm_fx6_setup_ecspi(void) { return 0; }
 450 #endif
 451
 452 #ifdef CONFIG_OF_BOARD_SETUP
 453 void ft_board_setup(void *blob, bd_t *bd)
 454 {
 455         uint8_t enetaddr[6];
 456
 457         /* MAC addr */
 458         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 459                 fdt_find_and_setprop(blob, "/fec", "local-mac-address",
 460                                      enetaddr, 6, 1);
 461         }
 462 }
 463 #endif
 464
 465 int board_init(void)
 466 {
 467         int ret;
 468
 469         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 470         cm_fx6_setup_gpmi_nand();
 471
 472         ret = cm_fx6_setup_ecspi();
 473         if (ret)
 474                 printf("Warning: ECSPI setup failed: %d\n", ret);
 475
 476         ret = cm_fx6_setup_usb_otg();
 477         if (ret)
 478                 printf("Warning: USB OTG setup failed: %d\n", ret);
 479
 480         ret = cm_fx6_setup_usb_host();
 481         if (ret)
 482                 printf("Warning: USB host setup failed: %d\n", ret);
 483
 484         /*
 485          * cm-fx6 may have iSSD not assembled and in this case it has
 486          * bypasses for a (m)SATA socket on the baseboard. The socketed
 487          * device is not controlled by those GPIOs. So just print a warning
 488          * if the setup fails.
 489          */
 490         ret = cm_fx6_setup_issd();
 491         if (ret)
 492                 printf("Warning: iSSD setup failed: %d\n", ret);
 493
 494         /* Warn on failure but do not abort boot */
 495         ret = cm_fx6_setup_i2c();
 496         if (ret)
 497                 printf("Warning: I2C setup failed: %d\n", ret);
 498
 499         return 0;
 500 }
 501
 502 int checkboard(void)
 503 {
 504         puts("Board: CM-FX6\n");
 505         return 0;
 506 }
 507
 508 void dram_init_banksize(void)
 509 {
 510         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 511         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 512
 513         switch (gd->ram_size) {
 514         case 0x10000000: /* DDR_16BIT_256MB */
 515                 gd->bd->bi_dram[0].size = 0x10000000;
 516                 gd->bd->bi_dram[1].size = 0;
 517                 break;
 518         case 0x20000000: /* DDR_32BIT_512MB */
 519                 gd->bd->bi_dram[0].size = 0x20000000;
 520                 gd->bd->bi_dram[1].size = 0;
 521                 break;
 522         case 0x40000000:
 523                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 524                         gd->bd->bi_dram[0].size = 0x20000000;
 525                         gd->bd->bi_dram[1].size = 0x20000000;
 526                 } else { /* DDR_64BIT_1GB */
 527                         gd->bd->bi_dram[0].size = 0x40000000;
 528                         gd->bd->bi_dram[1].size = 0;
 529                 }
 530                 break;
 531         case 0x80000000: /* DDR_64BIT_2GB */
 532                 gd->bd->bi_dram[0].size = 0x40000000;
 533                 gd->bd->bi_dram[1].size = 0x40000000;
 534                 break;
 535         case 0xEFF00000: /* DDR_64BIT_4GB */
 536                 gd->bd->bi_dram[0].size = 0x70000000;
 537                 gd->bd->bi_dram[1].size = 0x7FF00000;
 538                 break;
 539         }
 540 }
 541
 542 int dram_init(void)
 543 {
 544         gd->ram_size = imx_ddr_size();
 545         switch (gd->ram_size) {
 546         case 0x10000000:
 547         case 0x20000000:
 548         case 0x40000000:
 549         case 0x80000000:
 550                 break;
 551         case 0xF0000000:
 552                 gd->ram_size -= 0x100000;
 553                 break;
 554         default:
 555                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 556                 return -1;
 557         }
 558
 559         return 0;
 560 }
 561
 562 u32 get_board_rev(void)
 563 {
 564         return cl_eeprom_get_board_rev();
 565 }
 566