2 * Copyright (C) 2009 Texas Instruments Incorporated
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/nand_defs.h>
13 #include <asm/arch/davinci_misc.h>
17 DECLARE_GLOBAL_DATA_PTR;
21 struct davinci_gpio *gpio01_base =
22 (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
23 struct davinci_gpio *gpio23_base =
24 (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
25 struct davinci_gpio *gpio67_base =
26 (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
28 gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
29 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
31 /* GIO 9 & 10 are used for IO */
32 writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
34 /* Interrupt set GIO 9 */
35 writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
38 writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
40 /* Both edge trigger GIO 9 */
41 writel((readl(&gpio01_base->set_rising) | (1 << 9)),
42 &gpio01_base->set_rising);
43 writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
46 writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
47 &gpio01_base->set_data);
49 /* set GIO 10 output */
50 writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
53 writel((readl(&gpio01_base->set_data) | (1 << 10)),
54 &gpio01_base->set_data);
56 /* set GIO 32 output */
57 writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
60 writel((readl(&gpio23_base->set_data) | (1 << 0)),
61 &gpio23_base->set_data);
63 /* Enable UART1 MUX Lines */
64 writel((readl(PINMUX0) & ~3), PINMUX0);
65 writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
66 writel((readl(&gpio67_base->set_data) | (1 << 6)),
67 &gpio67_base->set_data);
72 #ifdef CONFIG_DRIVER_DM9000
73 int board_eth_init(bd_t *bis)
75 return dm9000_initialize(bis);
79 #ifdef CONFIG_NAND_DAVINCI
80 int board_nand_init(struct nand_chip *nand)
82 davinci_nand_init(nand);