board/dbau1x00/memsetup.S

   1 /* Memory sub-system initialization code */
   2
   3 #include <config.h>
   4 #include <version.h>
   5 #include <asm/regdef.h>
   6 #include <asm/au1x00.h>
   7
   8         .globl  memsetup
   9 memsetup:
  10         /* First setup pll:s to make serial work ok */
  11         /* We have a 12 MHz crystal */
  12         li              t0, SYS_CPUPLL
  13         li              t1, 0x21 /* 396 MHz */
  14         sw              t1, 0(t0)
  15         sync
  16         nop
  17
  18         /* Setup AUX PLL */
  19         li              t0, SYS_AUXPLL
  20         li              t1, 8 /* 96 MHz */
  21         sw              t1, 0(t0) /* aux pll */
  22         sync
  23
  24 /* SDCS 0,1 SDRAM */
  25         li              t0, MEM_SDMODE0
  26         li              t1, 0x005522AA
  27         sw              t1, 0(t0)
  28
  29         li              t0, MEM_SDMODE1
  30         li              t1, 0x005522AA
  31         sw              t1, 0(t0)
  32
  33         li              t0, MEM_SDADDR0
  34         li              t1, 0x001003F8
  35         sw              t1, 0(t0)
  36
  37
  38         li              t0, MEM_SDADDR1
  39         li              t1, 0x001023F8
  40         sw              t1, 0(t0)
  41         sync
  42
  43         li              t0, MEM_SDREFCFG
  44         li              t1, 0x64000C24 /* Disable */
  45         sw              t1, 0(t0)
  46         sync
  47
  48         li              t0, MEM_SDPRECMD
  49         sw              zero, 0(t0)
  50         sync
  51
  52         li              t0, MEM_SDAUTOREF
  53         sw              zero, 0(t0)
  54         sync
  55         sw              zero, 0(t0)
  56         sync
  57
  58         li              t0, MEM_SDREFCFG
  59         li              t1, 0x66000C24 /* Enable */
  60         sw              t1, 0(t0)
  61         sync
  62
  63         li              t0, MEM_SDWRMD0
  64         li              t1, 0x00000033
  65         sw              t1, 0(t0)
  66         sync
  67
  68         li              t0, MEM_SDWRMD1
  69         li              t1, 0x00000033
  70         sw              t1, 0(t0)
  71         sync
  72
  73         /*  Static memory controller */
  74
  75         /* RCE0 AMD 29LV640M MirrorBit Flash */
  76         li              t0, MEM_STCFG0
  77         li              t1, 0x00000003
  78         sw              t1, 0(t0)
  79
  80         li              t0, MEM_STTIME0
  81         li              t1, 0x22080b20
  82         sw              t1, 0(t0)
  83
  84         li              t0, MEM_STADDR0
  85         li              t1, 0x11E03F80
  86         sw              t1, 0(t0)
  87
  88         /* RCE1 CPLD Board Logic */
  89         li              t0, MEM_STCFG1
  90         li              t1, 0x00000080
  91         sw              t1, 0(t0)
  92
  93         li              t0, MEM_STTIME1
  94         li              t1, 0x22080a20
  95         sw              t1, 0(t0)
  96
  97         li              t0, MEM_STADDR1
  98         li              t1, 0x10c03f00
  99         sw              t1, 0(t0)
 100
 101         /* RCE3 PCMCIA 250ns */
 102         li              t0, MEM_STCFG3
 103         li              t1, 0x00000002
 104         sw              t1, 0(t0)
 105
 106
 107         li              t0, MEM_STTIME3
 108         li              t1, 0x280E3E07
 109         sw              t1, 0(t0)
 110
 111         li              t0, MEM_STADDR3
 112         li              t1, 0x10000000
 113         sw              t1, 0(t0)
 114
 115         sync
 116
 117         j       ra
 118         nop