2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 extern long int spd_sdram (void);
28 #include <asm/processor.h>
30 #define BOOT_SMALL_FLASH 32 /* 00100000 */
31 #define FLASH_ONBD_N 2 /* 00000010 */
32 #define FLASH_SRAM_SEL 1 /* 00000001 */
34 long int fixed_sdram (void);
36 int board_pre_init (void)
39 unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
43 /*--------------------------------------------------------------------
44 * Setup the external bus controller/chip selects
45 *-------------------------------------------------------------------*/
46 mtdcr (ebccfga, xbcfg);
47 reg = mfdcr (ebccfgd);
48 mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */
50 mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */
51 mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
52 mtebc (pb7ap, 0x01015280); /* FPGA registers */
53 mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
55 /* read FPGA_REG0 and set the bus controller */
57 if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
58 mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */
59 mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
60 mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */
61 mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
63 mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */
64 mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
66 /* set CS2 if FLASH_ONBD_N == 0 */
67 if (!(status & FLASH_ONBD_N)) {
68 mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */
69 mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
73 /*--------------------------------------------------------------------
74 * Setup the interrupt controller polarities, triggers, etc.
75 *-------------------------------------------------------------------*/
76 mtdcr (uic0sr, 0xffffffff); /* clear all */
77 mtdcr (uic0er, 0x00000000); /* disable all */
78 mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
79 mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
80 mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
81 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
82 mtdcr (uic0sr, 0xffffffff); /* clear all */
84 mtdcr (uic1sr, 0xffffffff); /* clear all */
85 mtdcr (uic1er, 0x00000000); /* disable all */
86 mtdcr (uic1cr, 0x00000000); /* all non-critical */
87 mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
88 mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
89 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
90 mtdcr (uic1sr, 0xffffffff); /* clear all */
101 get_sys_info (&sysinfo);
103 printf ("Board: IBM 440GP Evaluation Board (Ebony)\n");
104 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
105 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
106 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
107 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
108 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
113 long int initdram (int board_type)
116 extern long spd_sdram (void);
118 #if defined(CONFIG_SPD_EEPROM)
119 dram_size = spd_sdram ();
121 dram_size = fixed_sdram ();
127 #if defined(CFG_DRAM_TEST)
130 uint *pstart = (uint *) 0x00000000;
131 uint *pend = (uint *) 0x08000000;
134 for (p = pstart; p < pend; p++)
137 for (p = pstart; p < pend; p++) {
138 if (*p != 0xaaaaaaaa) {
139 printf ("SDRAM test fails at: %08x\n", (uint) p);
144 for (p = pstart; p < pend; p++)
147 for (p = pstart; p < pend; p++) {
148 if (*p != 0x55555555) {
149 printf ("SDRAM test fails at: %08x\n", (uint) p);
157 #if !defined(CONFIG_SPD_EEPROM)
158 /*************************************************************************
159 * fixed sdram init -- doesn't use serial presence detect.
161 * Assumes: 128 MB, non-ECC, non-registered
164 ************************************************************************/
165 long int fixed_sdram (void)
169 /*--------------------------------------------------------------------
171 *------------------------------------------------------------------*/
172 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
173 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
174 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
175 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
176 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
178 /*--------------------------------------------------------------------
179 * Setup for board-specific specific mem
180 *------------------------------------------------------------------*/
182 * Following for CAS Latency = 2.5 @ 133 MHz PLB
184 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
185 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
187 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
188 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
189 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
190 udelay (400); /* Delay 200 usecs (min) */
192 /*--------------------------------------------------------------------
193 * Enable the controller, then wait for DCEN to complete
194 *------------------------------------------------------------------*/
195 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
197 mfsdram (mem_mcsts, reg);
198 if (reg & 0x80000000)
202 return (128 * 1024 * 1024); /* 128 MB */
204 #endif /* !defined(CONFIG_SPD_EEPROM) */
207 /*************************************************************************
210 * This routine is called just prior to registering the hose and gives
211 * the board the opportunity to check things. Returning a value of zero
212 * indicates that things are bad & PCI initialization should be aborted.
214 * Different boards may wish to customize the pci controller structure
215 * (add regions, override default access routines, etc) or perform
216 * certain pre-initialization actions.
218 ************************************************************************/
219 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
220 int pci_pre_init(struct pci_controller * hose )
224 /*--------------------------------------------------------------------------+
225 * The ebony board is always configured as the host & requires the
226 * PCI arbiter to be enabled.
227 *--------------------------------------------------------------------------*/
228 strap = mfdcr(cpc0_strp1);
229 if( (strap & 0x00100000) == 0 ){
230 printf("PCI: CPC0_STRP1[PAE] not set.\n");
236 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
238 /*************************************************************************
241 * The bootstrap configuration provides default settings for the pci
242 * inbound map (PIM). But the bootstrap config choices are limited and
243 * may not be sufficient for a given board.
245 ************************************************************************/
246 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
247 void pci_target_init(struct pci_controller * hose )
249 DECLARE_GLOBAL_DATA_PTR;
251 /*--------------------------------------------------------------------------+
253 *--------------------------------------------------------------------------*/
254 out32r( PCIX0_PIM0SA, 0 ); /* disable */
255 out32r( PCIX0_PIM1SA, 0 ); /* disable */
256 out32r( PCIX0_PIM2SA, 0 ); /* disable */
257 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
259 /*--------------------------------------------------------------------------+
260 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
261 * options to not support sizes such as 128/256 MB.
262 *--------------------------------------------------------------------------*/
263 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
264 out32r( PCIX0_PIM0LAH, 0 );
265 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
267 out32r( PCIX0_BAR0, 0 );
269 /*--------------------------------------------------------------------------+
270 * Program the board's subsystem id/vendor id
271 *--------------------------------------------------------------------------*/
272 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
273 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
275 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
277 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
280 /*************************************************************************
283 * This routine is called to determine if a pci scan should be
284 * performed. With various hardware environments (especially cPCI and
285 * PPMC) it's insufficient to depend on the state of the arbiter enable
286 * bit in the strap register, or generic host/adapter assumptions.
288 * Rather than hard-code a bad assumption in the general 440 code, the
289 * 440 pci code requires the board to decide at runtime.
291 * Return 0 for adapter mode, non-zero for host (monarch) mode.
294 ************************************************************************/
295 #if defined(CONFIG_PCI)
296 int is_pci_host(struct pci_controller *hose)
298 /* The ebony board is always configured as host. */
301 #endif /* defined(CONFIG_PCI) */