board/embest/mx6boards/mx6boards.c

   1 /*
   2  * Copyright (C) 2014 Eukréa Electromatique
   3  * Author: Eric Bénard <eric@eukrea.com>
   4  *         Fabio Estevam <fabio.estevam@freescale.com>
   5  *         Jon Nettleton <jon.nettleton@gmail.com>
   6  *
   7  * based on sabresd.c which is :
   8  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   9  * and on hummingboard.c which is :
  10  * Copyright (C) 2013 SolidRun ltd.
  11  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/errno.h>
  22 #include <asm/gpio.h>
  23 #include <asm/imx-common/iomux-v3.h>
  24 #include <asm/imx-common/boot_mode.h>
  25 #include <asm/imx-common/mxc_i2c.h>
  26 #include <asm/imx-common/video.h>
  27 #include <i2c.h>
  28 #include <mmc.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/mxc_hdmi.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <linux/fb.h>
  35 #include <ipu_pixfmt.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/sys_proto.h>
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |         \
  49         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |                  \
  50         PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  57
  58 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  66                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  67
  68 static int board_type = -1;
  69 #define BOARD_IS_MARSBOARD      0
  70 #define BOARD_IS_RIOTBOARD      1
  71
  72 int dram_init(void)
  73 {
  74         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  75
  76         return 0;
  77 }
  78
  79 static iomux_v3_cfg_t const uart2_pads[] = {
  80         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 static void setup_iomux_uart(void)
  85 {
  86         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  87 }
  88
  89 iomux_v3_cfg_t const enet_pads[] = {
  90         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         /* GPIO16 -> AR8035 25MHz */
  93         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  94         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
  95         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 101         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
 102         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 104         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 105         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 106         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 107         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 108         /* AR8035 PHY Reset */
 109         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 110         /* AR8035 PHY Interrupt */
 111         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112 };
 113
 114 static void setup_iomux_enet(void)
 115 {
 116         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 117
 118         /* Reset AR8035 PHY */
 119         gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
 120         mdelay(2);
 121         gpio_set_value(IMX_GPIO_NR(3, 31), 1);
 122 }
 123
 124 int mx6_rgmii_rework(struct phy_device *phydev)
 125 {
 126         /* from linux/arch/arm/mach-imx/mach-imx6q.c :
 127          * Ar803x phy SmartEEE feature cause link status generates glitch,
 128          * which cause ethernet link down/up issue, so disable SmartEEE
 129          */
 130         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 131         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 132         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 133
 134         return 0;
 135 }
 136
 137 int board_phy_config(struct phy_device *phydev)
 138 {
 139         mx6_rgmii_rework(phydev);
 140
 141         if (phydev->drv->config)
 142                 phydev->drv->config(phydev);
 143
 144         return 0;
 145 }
 146
 147 iomux_v3_cfg_t const usdhc2_pads[] = {
 148         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 149         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 155         MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 156 };
 157
 158 iomux_v3_cfg_t const usdhc3_pads[] = {
 159         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 160         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165 };
 166
 167 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
 168         MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 169         MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 170 };
 171
 172 iomux_v3_cfg_t const usdhc4_pads[] = {
 173         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 174         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 177         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 178         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         /* eMMC RST */
 180         MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 181 };
 182
 183 #ifdef CONFIG_FSL_ESDHC
 184 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 185         {USDHC2_BASE_ADDR},
 186         {USDHC3_BASE_ADDR},
 187         {USDHC4_BASE_ADDR},
 188 };
 189
 190 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 191 #define USDHC3_CD_GPIO  IMX_GPIO_NR(7, 0)
 192
 193 int board_mmc_getcd(struct mmc *mmc)
 194 {
 195         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 196         int ret = 0;
 197
 198         switch (cfg->esdhc_base) {
 199         case USDHC2_BASE_ADDR:
 200                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 201                 break;
 202         case USDHC3_BASE_ADDR:
 203                 if (board_type == BOARD_IS_RIOTBOARD)
 204                         ret = !gpio_get_value(USDHC3_CD_GPIO);
 205                 else if (board_type == BOARD_IS_MARSBOARD)
 206                         ret = 1; /* eMMC/uSDHC3 is always present */
 207                 break;
 208         case USDHC4_BASE_ADDR:
 209                 ret = 1; /* eMMC/uSDHC4 is always present */
 210                 break;
 211         }
 212
 213         return ret;
 214 }
 215
 216 int board_mmc_init(bd_t *bis)
 217 {
 218         s32 status = 0;
 219         int i;
 220
 221         /*
 222          * According to the board_mmc_init() the following map is done:
 223          * (U-boot device node)    (Physical Port)
 224          * ** RiOTboard :
 225          * mmc0                    SDCard slot (bottom)
 226          * mmc1                    uSDCard slot (top)
 227          * mmc2                    eMMC
 228          * ** MarSBoard :
 229          * mmc0                    uSDCard slot (bottom)
 230          * mmc1                    eMMC
 231          */
 232         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 233                 switch (i) {
 234                 case 0:
 235                         imx_iomux_v3_setup_multiple_pads(
 236                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 237                         gpio_direction_input(USDHC2_CD_GPIO);
 238                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 239                         usdhc_cfg[0].max_bus_width = 4;
 240                         break;
 241                 case 1:
 242                         imx_iomux_v3_setup_multiple_pads(
 243                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 244                         if (board_type == BOARD_IS_RIOTBOARD) {
 245                                 imx_iomux_v3_setup_multiple_pads(
 246                                         riotboard_usdhc3_pads,
 247                                         ARRAY_SIZE(riotboard_usdhc3_pads));
 248                                 gpio_direction_input(USDHC3_CD_GPIO);
 249                         } else {
 250                                 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
 251                                 udelay(250);
 252                                 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
 253                         }
 254                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 255                         usdhc_cfg[1].max_bus_width = 4;
 256                         break;
 257                 case 2:
 258                         imx_iomux_v3_setup_multiple_pads(
 259                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 260                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 261                         usdhc_cfg[2].max_bus_width = 4;
 262                         gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
 263                         udelay(250);
 264                         gpio_set_value(IMX_GPIO_NR(6, 8), 1);
 265                         break;
 266                 default:
 267                         printf("Warning: you configured more USDHC controllers"
 268                                "(%d) then supported by the board (%d)\n",
 269                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 270                         return status;
 271                 }
 272
 273                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 274         }
 275
 276         return status;
 277 }
 278 #endif
 279
 280 #ifdef CONFIG_MXC_SPI
 281 iomux_v3_cfg_t const ecspi1_pads[] = {
 282         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 283         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 284         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 285         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 286 };
 287
 288 static void setup_spi(void)
 289 {
 290         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 291 }
 292 #endif
 293
 294 struct i2c_pads_info i2c_pad_info1 = {
 295         .scl = {
 296                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
 297                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 298                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
 299                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 300                 .gp = IMX_GPIO_NR(5, 27)
 301         },
 302         .sda = {
 303                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
 304                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 305                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
 306                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 307                 .gp = IMX_GPIO_NR(5, 26)
 308         }
 309 };
 310
 311 struct i2c_pads_info i2c_pad_info2 = {
 312         .scl = {
 313                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
 314                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 315                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
 316                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 317                 .gp = IMX_GPIO_NR(4, 12)
 318         },
 319         .sda = {
 320                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
 321                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 322                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
 323                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 324                 .gp = IMX_GPIO_NR(4, 13)
 325         }
 326 };
 327
 328 struct i2c_pads_info i2c_pad_info3 = {
 329         .scl = {
 330                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
 331                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 332                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
 333                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 334                 .gp = IMX_GPIO_NR(1, 5)
 335         },
 336         .sda = {
 337                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
 338                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 339                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
 340                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 341                 .gp = IMX_GPIO_NR(1, 6)
 342         }
 343 };
 344
 345 iomux_v3_cfg_t const tft_pads_riot[] = {
 346         /* LCD_PWR_EN */
 347         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 348         /* TOUCH_INT */
 349         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 350         /* LED_PWR_EN */
 351         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 352         /* BL LEVEL */
 353         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 354 };
 355
 356 iomux_v3_cfg_t const tft_pads_mars[] = {
 357         /* LCD_PWR_EN */
 358         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 359         /* TOUCH_INT */
 360         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 361         /* LED_PWR_EN */
 362         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 363         /* BL LEVEL (PWM4) */
 364         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 365 };
 366
 367 #if defined(CONFIG_VIDEO_IPUV3)
 368
 369 static void enable_lvds(struct display_info_t const *dev)
 370 {
 371         struct iomuxc *iomux = (struct iomuxc *)
 372                                 IOMUXC_BASE_ADDR;
 373         setbits_le32(&iomux->gpr[2],
 374                      IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
 375         /* set backlight level to ON */
 376         if (board_type == BOARD_IS_RIOTBOARD)
 377                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
 378         else if (board_type == BOARD_IS_MARSBOARD)
 379                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
 380 }
 381
 382 static void disable_lvds(struct display_info_t const *dev)
 383 {
 384         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 385
 386         /* set backlight level to OFF */
 387         if (board_type == BOARD_IS_RIOTBOARD)
 388                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 389         else if (board_type == BOARD_IS_MARSBOARD)
 390                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 391
 392         clrbits_le32(&iomux->gpr[2],
 393                      IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
 394 }
 395
 396 static void do_enable_hdmi(struct display_info_t const *dev)
 397 {
 398         disable_lvds(dev);
 399         imx_enable_hdmi_phy();
 400 }
 401
 402 static int detect_i2c(struct display_info_t const *dev)
 403 {
 404         return (0 == i2c_set_bus_num(dev->bus)) &&
 405                 (0 == i2c_probe(dev->addr));
 406 }
 407
 408 struct display_info_t const displays[] = {{
 409         .bus    = -1,
 410         .addr   = 0,
 411         .pixfmt = IPU_PIX_FMT_RGB24,
 412         .detect = detect_hdmi,
 413         .enable = do_enable_hdmi,
 414         .mode   = {
 415                 .name           = "HDMI",
 416                 .refresh        = 60,
 417                 .xres           = 1024,
 418                 .yres           = 768,
 419                 .pixclock       = 15385,
 420                 .left_margin    = 220,
 421                 .right_margin   = 40,
 422                 .upper_margin   = 21,
 423                 .lower_margin   = 7,
 424                 .hsync_len      = 60,
 425                 .vsync_len      = 10,
 426                 .sync           = FB_SYNC_EXT,
 427                 .vmode          = FB_VMODE_NONINTERLACED
 428 } }, {
 429         .bus    = 2,
 430         .addr   = 0x1,
 431         .pixfmt = IPU_PIX_FMT_LVDS666,
 432         .detect = detect_i2c,
 433         .enable = enable_lvds,
 434         .mode   = {
 435                 .name           = "LCD8000-97C",
 436                 .refresh        = 60,
 437                 .xres           = 1024,
 438                 .yres           = 768,
 439                 .pixclock       = 15385,
 440                 .left_margin    = 100,
 441                 .right_margin   = 200,
 442                 .upper_margin   = 10,
 443                 .lower_margin   = 20,
 444                 .hsync_len      = 20,
 445                 .vsync_len      = 8,
 446                 .sync           = FB_SYNC_EXT,
 447                 .vmode          = FB_VMODE_NONINTERLACED
 448 } } };
 449 size_t display_count = ARRAY_SIZE(displays);
 450
 451 static void setup_display(void)
 452 {
 453         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 454         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 455         int reg;
 456
 457         enable_ipu_clock();
 458         imx_setup_hdmi();
 459
 460         /* Turn on LDB0, IPU,IPU DI0 clocks */
 461         setbits_le32(&mxc_ccm->CCGR3,
 462                      MXC_CCM_CCGR3_LDB_DI0_MASK);
 463
 464         /* set LDB0 clk select to 011/011 */
 465         clrsetbits_le32(&mxc_ccm->cs2cdr,
 466                         MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
 467                         (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 468
 469         setbits_le32(&mxc_ccm->cscmr2,
 470                      MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 471
 472         setbits_le32(&mxc_ccm->chsccdr,
 473                      (CHSCCDR_CLK_SEL_LDB_DI0
 474                      << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 475
 476         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 477              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 478              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 479              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 480              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 481              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 482              | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 483              | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 484         writel(reg, &iomux->gpr[2]);
 485
 486         clrsetbits_le32(&iomux->gpr[3],
 487                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 488                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 489                         IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 490                         << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 491 }
 492 #endif /* CONFIG_VIDEO_IPUV3 */
 493
 494 /*
 495  * Do not overwrite the console
 496  * Use always serial for U-Boot console
 497  */
 498 int overwrite_console(void)
 499 {
 500         return 1;
 501 }
 502
 503 int board_eth_init(bd_t *bis)
 504 {
 505         setup_iomux_enet();
 506
 507         return cpu_eth_init(bis);
 508 }
 509
 510 int board_early_init_f(void)
 511 {
 512         u32 cputype = cpu_type(get_cpu_rev());
 513
 514         switch (cputype) {
 515         case MXC_CPU_MX6SOLO:
 516                 board_type = BOARD_IS_RIOTBOARD;
 517                 break;
 518         case MXC_CPU_MX6D:
 519                 board_type = BOARD_IS_MARSBOARD;
 520                 break;
 521         }
 522
 523         setup_iomux_uart();
 524
 525         if (board_type == BOARD_IS_RIOTBOARD)
 526                 imx_iomux_v3_setup_multiple_pads(
 527                         tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
 528         else if (board_type == BOARD_IS_MARSBOARD)
 529                 imx_iomux_v3_setup_multiple_pads(
 530                         tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
 531 #if defined(CONFIG_VIDEO_IPUV3)
 532         /* power ON LCD */
 533         gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
 534         /* touch interrupt is an input */
 535         gpio_direction_input(IMX_GPIO_NR(6, 14));
 536         /* power ON backlight */
 537         gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
 538         /* set backlight level to off */
 539         if (board_type == BOARD_IS_RIOTBOARD)
 540                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 541         else if (board_type == BOARD_IS_MARSBOARD)
 542                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 543         setup_display();
 544 #endif
 545
 546         return 0;
 547 }
 548
 549 int board_init(void)
 550 {
 551         /* address of boot parameters */
 552         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 553         /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
 554         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 555         /* i2c2 : HDMI EDID */
 556         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 557         /* i2c3 : LVDS, Expansion connector */
 558         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 559 #ifdef CONFIG_MXC_SPI
 560         setup_spi();
 561 #endif
 562         return 0;
 563 }
 564
 565 #ifdef CONFIG_CMD_BMODE
 566 static const struct boot_mode riotboard_boot_modes[] = {
 567         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 568         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 569         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 570         {NULL,   0},
 571 };
 572 static const struct boot_mode marsboard_boot_modes[] = {
 573         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 574         {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 575         {NULL,   0},
 576 };
 577 #endif
 578
 579 int board_late_init(void)
 580 {
 581 #ifdef CONFIG_CMD_BMODE
 582         if (board_type == BOARD_IS_RIOTBOARD)
 583                 add_board_boot_modes(riotboard_boot_modes);
 584         else if (board_type == BOARD_IS_RIOTBOARD)
 585                 add_board_boot_modes(marsboard_boot_modes);
 586 #endif
 587
 588         return 0;
 589 }
 590
 591 int checkboard(void)
 592 {
 593         puts("Board: ");
 594         if (board_type == BOARD_IS_MARSBOARD)
 595                 puts("MarSBoard\n");
 596         else if (board_type == BOARD_IS_RIOTBOARD)
 597                 puts("RIoTboard\n");
 598         else
 599                 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
 600
 601         return 0;
 602 }