board/embest/mx6boards/mx6boards.c

   1 /*
   2  * Copyright (C) 2014 Eukréa Electromatique
   3  * Author: Eric Bénard <eric@eukrea.com>
   4  *         Fabio Estevam <fabio.estevam@freescale.com>
   5  *         Jon Nettleton <jon.nettleton@gmail.com>
   6  *
   7  * based on sabresd.c which is :
   8  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   9  * and on hummingboard.c which is :
  10  * Copyright (C) 2013 SolidRun ltd.
  11  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/errno.h>
  22 #include <asm/gpio.h>
  23 #include <asm/imx-common/iomux-v3.h>
  24 #include <asm/imx-common/boot_mode.h>
  25 #include <asm/imx-common/mxc_i2c.h>
  26 #include <asm/imx-common/video.h>
  27 #include <i2c.h>
  28 #include <mmc.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/mxc_hdmi.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <linux/fb.h>
  35 #include <ipu_pixfmt.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/sys_proto.h>
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW |         \
  49         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST |                  \
  50         PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  57
  58 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  66                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  67
  68 static int board_type = -1;
  69 #define BOARD_IS_MARSBOARD      0
  70 #define BOARD_IS_RIOTBOARD      1
  71
  72 int dram_init(void)
  73 {
  74         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  75
  76         return 0;
  77 }
  78
  79 static iomux_v3_cfg_t const uart2_pads[] = {
  80         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 static void setup_iomux_uart(void)
  85 {
  86         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  87 }
  88
  89 iomux_v3_cfg_t const enet_pads[] = {
  90         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         /* GPIO16 -> AR8035 25MHz */
  93         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  94         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
  95         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 101         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
 102         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 104         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 105         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 106         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 107         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 108         /* AR8035 PHY Reset */
 109         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 110         /* AR8035 PHY Interrupt */
 111         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112 };
 113
 114 static void setup_iomux_enet(void)
 115 {
 116         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 117
 118         /* Reset AR8035 PHY */
 119         gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
 120         mdelay(2);
 121         gpio_set_value(IMX_GPIO_NR(3, 31), 1);
 122 }
 123
 124 int mx6_rgmii_rework(struct phy_device *phydev)
 125 {
 126         /* from linux/arch/arm/mach-imx/mach-imx6q.c :
 127          * Ar803x phy SmartEEE feature cause link status generates glitch,
 128          * which cause ethernet link down/up issue, so disable SmartEEE
 129          */
 130         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 131         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 132         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 133
 134         return 0;
 135 }
 136
 137 int board_phy_config(struct phy_device *phydev)
 138 {
 139         mx6_rgmii_rework(phydev);
 140
 141         if (phydev->drv->config)
 142                 phydev->drv->config(phydev);
 143
 144         return 0;
 145 }
 146
 147 iomux_v3_cfg_t const usdhc2_pads[] = {
 148         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 149         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 155         MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 156 };
 157
 158 iomux_v3_cfg_t const usdhc3_pads[] = {
 159         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 160         MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165 };
 166
 167 iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
 168         MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
 169         MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 170 };
 171
 172 iomux_v3_cfg_t const usdhc4_pads[] = {
 173         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
 174         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 177         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 178         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         /* eMMC RST */
 180         MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 181 };
 182
 183 #ifdef CONFIG_FSL_ESDHC
 184 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 185         {USDHC2_BASE_ADDR},
 186         {USDHC3_BASE_ADDR},
 187         {USDHC4_BASE_ADDR},
 188 };
 189
 190 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 191 #define USDHC3_CD_GPIO  IMX_GPIO_NR(7, 0)
 192
 193 int board_mmc_getcd(struct mmc *mmc)
 194 {
 195         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 196         int ret = 0;
 197
 198         switch (cfg->esdhc_base) {
 199         case USDHC2_BASE_ADDR:
 200                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 201                 break;
 202         case USDHC3_BASE_ADDR:
 203                 if (board_type == BOARD_IS_RIOTBOARD)
 204                         ret = !gpio_get_value(USDHC3_CD_GPIO);
 205                 else if (board_type == BOARD_IS_MARSBOARD)
 206                         ret = 1; /* eMMC/uSDHC3 is always present */
 207                 break;
 208         case USDHC4_BASE_ADDR:
 209                 ret = 1; /* eMMC/uSDHC4 is always present */
 210                 break;
 211         }
 212
 213         return ret;
 214 }
 215
 216 int board_mmc_init(bd_t *bis)
 217 {
 218         s32 status = 0;
 219         int i;
 220
 221         /*
 222          * According to the board_mmc_init() the following map is done:
 223          * (U-boot device node)    (Physical Port)
 224          * ** RiOTboard :
 225          * mmc0                    SDCard slot (bottom)
 226          * mmc1                    uSDCard slot (top)
 227          * mmc2                    eMMC
 228          * ** MarSBoard :
 229          * mmc0                    uSDCard slot (bottom)
 230          * mmc1                    eMMC
 231          */
 232         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 233                 switch (i) {
 234                 case 0:
 235                         imx_iomux_v3_setup_multiple_pads(
 236                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 237                         gpio_direction_input(USDHC2_CD_GPIO);
 238                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 239                         usdhc_cfg[0].max_bus_width = 4;
 240                         break;
 241                 case 1:
 242                         imx_iomux_v3_setup_multiple_pads(
 243                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 244                         if (board_type == BOARD_IS_RIOTBOARD) {
 245                                 imx_iomux_v3_setup_multiple_pads(
 246                                         riotboard_usdhc3_pads,
 247                                         ARRAY_SIZE(riotboard_usdhc3_pads));
 248                                 gpio_direction_input(USDHC3_CD_GPIO);
 249                         } else {
 250                                 gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
 251                                 udelay(250);
 252                                 gpio_set_value(IMX_GPIO_NR(7, 8), 1);
 253                         }
 254                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 255                         usdhc_cfg[1].max_bus_width = 4;
 256                         break;
 257                 case 2:
 258                         imx_iomux_v3_setup_multiple_pads(
 259                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 260                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 261                         usdhc_cfg[2].max_bus_width = 4;
 262                         gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
 263                         udelay(250);
 264                         gpio_set_value(IMX_GPIO_NR(6, 8), 1);
 265                         break;
 266                 default:
 267                         printf("Warning: you configured more USDHC controllers"
 268                                "(%d) then supported by the board (%d)\n",
 269                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 270                         return status;
 271                 }
 272
 273                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 274         }
 275
 276         return status;
 277 }
 278 #endif
 279
 280 #ifdef CONFIG_MXC_SPI
 281 iomux_v3_cfg_t const ecspi1_pads[] = {
 282         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 283         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 284         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 285         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 286 };
 287
 288 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 289 {
 290         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 291 }
 292
 293 static void setup_spi(void)
 294 {
 295         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 296 }
 297 #endif
 298
 299 struct i2c_pads_info i2c_pad_info1 = {
 300         .scl = {
 301                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
 302                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 303                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
 304                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 305                 .gp = IMX_GPIO_NR(5, 27)
 306         },
 307         .sda = {
 308                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
 309                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 310                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
 311                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 312                 .gp = IMX_GPIO_NR(5, 26)
 313         }
 314 };
 315
 316 struct i2c_pads_info i2c_pad_info2 = {
 317         .scl = {
 318                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
 319                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 320                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
 321                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 322                 .gp = IMX_GPIO_NR(4, 12)
 323         },
 324         .sda = {
 325                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
 326                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 327                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
 328                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 329                 .gp = IMX_GPIO_NR(4, 13)
 330         }
 331 };
 332
 333 struct i2c_pads_info i2c_pad_info3 = {
 334         .scl = {
 335                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
 336                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 337                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
 338                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 339                 .gp = IMX_GPIO_NR(1, 5)
 340         },
 341         .sda = {
 342                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
 343                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 344                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
 345                                 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 346                 .gp = IMX_GPIO_NR(1, 6)
 347         }
 348 };
 349
 350 iomux_v3_cfg_t const tft_pads_riot[] = {
 351         /* LCD_PWR_EN */
 352         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 353         /* TOUCH_INT */
 354         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 355         /* LED_PWR_EN */
 356         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 357         /* BL LEVEL */
 358         MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 359 };
 360
 361 iomux_v3_cfg_t const tft_pads_mars[] = {
 362         /* LCD_PWR_EN */
 363         MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 364         /* TOUCH_INT */
 365         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 366         /* LED_PWR_EN */
 367         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 368         /* BL LEVEL (PWM4) */
 369         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 370 };
 371
 372 #if defined(CONFIG_VIDEO_IPUV3)
 373
 374 static void enable_lvds(struct display_info_t const *dev)
 375 {
 376         struct iomuxc *iomux = (struct iomuxc *)
 377                                 IOMUXC_BASE_ADDR;
 378         setbits_le32(&iomux->gpr[2],
 379                      IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
 380         /* set backlight level to ON */
 381         if (board_type == BOARD_IS_RIOTBOARD)
 382                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
 383         else if (board_type == BOARD_IS_MARSBOARD)
 384                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
 385 }
 386
 387 static void disable_lvds(struct display_info_t const *dev)
 388 {
 389         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 390
 391         /* set backlight level to OFF */
 392         if (board_type == BOARD_IS_RIOTBOARD)
 393                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 394         else if (board_type == BOARD_IS_MARSBOARD)
 395                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 396
 397         clrbits_le32(&iomux->gpr[2],
 398                      IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
 399 }
 400
 401 static void do_enable_hdmi(struct display_info_t const *dev)
 402 {
 403         disable_lvds(dev);
 404         imx_enable_hdmi_phy();
 405 }
 406
 407 static int detect_i2c(struct display_info_t const *dev)
 408 {
 409         return (0 == i2c_set_bus_num(dev->bus)) &&
 410                 (0 == i2c_probe(dev->addr));
 411 }
 412
 413 struct display_info_t const displays[] = {{
 414         .bus    = -1,
 415         .addr   = 0,
 416         .pixfmt = IPU_PIX_FMT_RGB24,
 417         .detect = detect_hdmi,
 418         .enable = do_enable_hdmi,
 419         .mode   = {
 420                 .name           = "HDMI",
 421                 .refresh        = 60,
 422                 .xres           = 1024,
 423                 .yres           = 768,
 424                 .pixclock       = 15385,
 425                 .left_margin    = 220,
 426                 .right_margin   = 40,
 427                 .upper_margin   = 21,
 428                 .lower_margin   = 7,
 429                 .hsync_len      = 60,
 430                 .vsync_len      = 10,
 431                 .sync           = FB_SYNC_EXT,
 432                 .vmode          = FB_VMODE_NONINTERLACED
 433 } }, {
 434         .bus    = 2,
 435         .addr   = 0x1,
 436         .pixfmt = IPU_PIX_FMT_LVDS666,
 437         .detect = detect_i2c,
 438         .enable = enable_lvds,
 439         .mode   = {
 440                 .name           = "LCD8000-97C",
 441                 .refresh        = 60,
 442                 .xres           = 1024,
 443                 .yres           = 768,
 444                 .pixclock       = 15385,
 445                 .left_margin    = 100,
 446                 .right_margin   = 200,
 447                 .upper_margin   = 10,
 448                 .lower_margin   = 20,
 449                 .hsync_len      = 20,
 450                 .vsync_len      = 8,
 451                 .sync           = FB_SYNC_EXT,
 452                 .vmode          = FB_VMODE_NONINTERLACED
 453 } } };
 454 size_t display_count = ARRAY_SIZE(displays);
 455
 456 static void setup_display(void)
 457 {
 458         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 459         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 460         int reg;
 461
 462         enable_ipu_clock();
 463         imx_setup_hdmi();
 464
 465         /* Turn on LDB0, IPU,IPU DI0 clocks */
 466         setbits_le32(&mxc_ccm->CCGR3,
 467                      MXC_CCM_CCGR3_LDB_DI0_MASK);
 468
 469         /* set LDB0 clk select to 011/011 */
 470         clrsetbits_le32(&mxc_ccm->cs2cdr,
 471                         MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
 472                         (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 473
 474         setbits_le32(&mxc_ccm->cscmr2,
 475                      MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 476
 477         setbits_le32(&mxc_ccm->chsccdr,
 478                      (CHSCCDR_CLK_SEL_LDB_DI0
 479                      << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 480
 481         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 482              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 483              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 484              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 485              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 486              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 487              | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 488              | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 489         writel(reg, &iomux->gpr[2]);
 490
 491         clrsetbits_le32(&iomux->gpr[3],
 492                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 493                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 494                         IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 495                         << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 496 }
 497 #endif /* CONFIG_VIDEO_IPUV3 */
 498
 499 /*
 500  * Do not overwrite the console
 501  * Use always serial for U-Boot console
 502  */
 503 int overwrite_console(void)
 504 {
 505         return 1;
 506 }
 507
 508 int board_eth_init(bd_t *bis)
 509 {
 510         setup_iomux_enet();
 511
 512         return cpu_eth_init(bis);
 513 }
 514
 515 int board_early_init_f(void)
 516 {
 517         u32 cputype = cpu_type(get_cpu_rev());
 518
 519         switch (cputype) {
 520         case MXC_CPU_MX6SOLO:
 521                 board_type = BOARD_IS_RIOTBOARD;
 522                 break;
 523         case MXC_CPU_MX6D:
 524                 board_type = BOARD_IS_MARSBOARD;
 525                 break;
 526         }
 527
 528         setup_iomux_uart();
 529
 530         if (board_type == BOARD_IS_RIOTBOARD)
 531                 imx_iomux_v3_setup_multiple_pads(
 532                         tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
 533         else if (board_type == BOARD_IS_MARSBOARD)
 534                 imx_iomux_v3_setup_multiple_pads(
 535                         tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
 536 #if defined(CONFIG_VIDEO_IPUV3)
 537         /* power ON LCD */
 538         gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
 539         /* touch interrupt is an input */
 540         gpio_direction_input(IMX_GPIO_NR(6, 14));
 541         /* power ON backlight */
 542         gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
 543         /* set backlight level to off */
 544         if (board_type == BOARD_IS_RIOTBOARD)
 545                 gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
 546         else if (board_type == BOARD_IS_MARSBOARD)
 547                 gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
 548         setup_display();
 549 #endif
 550
 551         return 0;
 552 }
 553
 554 int board_init(void)
 555 {
 556         /* address of boot parameters */
 557         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 558         /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
 559         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 560         /* i2c2 : HDMI EDID */
 561         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 562         /* i2c3 : LVDS, Expansion connector */
 563         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 564 #ifdef CONFIG_MXC_SPI
 565         setup_spi();
 566 #endif
 567         return 0;
 568 }
 569
 570 #ifdef CONFIG_CMD_BMODE
 571 static const struct boot_mode riotboard_boot_modes[] = {
 572         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 573         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 574         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 575         {NULL,   0},
 576 };
 577 static const struct boot_mode marsboard_boot_modes[] = {
 578         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 579         {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 580         {NULL,   0},
 581 };
 582 #endif
 583
 584 int board_late_init(void)
 585 {
 586 #ifdef CONFIG_CMD_BMODE
 587         if (board_type == BOARD_IS_RIOTBOARD)
 588                 add_board_boot_modes(riotboard_boot_modes);
 589         else if (board_type == BOARD_IS_RIOTBOARD)
 590                 add_board_boot_modes(marsboard_boot_modes);
 591 #endif
 592
 593         return 0;
 594 }
 595
 596 int checkboard(void)
 597 {
 598         puts("Board: ");
 599         if (board_type == BOARD_IS_MARSBOARD)
 600                 puts("MarSBoard\n");
 601         else if (board_type == BOARD_IS_RIOTBOARD)
 602                 puts("RIoTboard\n");
 603         else
 604                 printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
 605
 606         return 0;
 607 }