board/esd/apc405/apc405.c

   1 /*
   2  * (C) Copyright 2005-2008
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2003
   6  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <asm/processor.h>
  29 #include <asm/io.h>
  30 #include <command.h>
  31 #include <malloc.h>
  32 #include <flash.h>
  33 #include <mtd/cfi_flash.h>
  34 #include <asm/4xx_pci.h>
  35 #include <pci.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #undef FPGA_DEBUG
  40
  41 extern void lxt971_no_sleep(void);
  42
  43 /* fpga configuration data - gzip compressed and generated by bin2c */
  44 const unsigned char fpgadata[] =
  45 {
  46 #include "fpgadata.c"
  47 };
  48
  49 /*
  50  * include common fpga code (for esd boards)
  51  */
  52 #include "../common/fpga.c"
  53
  54 #ifdef CONFIG_LCD_USED
  55 /* logo bitmap data - gzip compressed and generated by bin2c */
  56 unsigned char logo_bmp[] =
  57 {
  58 #include "logo_640_480_24bpp.c"
  59 };
  60
  61 /*
  62  * include common lcd code (for esd boards)
  63  */
  64 #include "../common/lcd.c"
  65 #include "../common/s1d13505_640_480_16bpp.h"
  66 #include "../common/s1d13806_640_480_16bpp.h"
  67 #endif /* CONFIG_LCD_USED */
  68
  69 /*
  70  * include common auto-update code (for esd boards)
  71  */
  72 #include "../common/auto_update.h"
  73
  74 au_image_t au_image[] = {
  75         {"preinst.img", 0, -1, AU_SCRIPT},
  76         {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
  77         {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
  78         {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
  79         {"work.img", 0xfe500000, 0x01400000, AU_NOR},
  80         {"data.img", 0xff900000, 0x00580000, AU_NOR},
  81         {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
  82         {"postinst.img", 0, 0, AU_SCRIPT},
  83 };
  84
  85 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
  86
  87 int board_revision(void)
  88 {
  89         unsigned long CPC0_CR0Reg;
  90         unsigned long value;
  91
  92         /*
  93          * Get version of APC405 board from GPIO's
  94          */
  95
  96         /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
  97         CPC0_CR0Reg = mfdcr(CPC0_CR0);
  98         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
  99         out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
 100         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
 101
 102         /* wait some time before reading input */
 103         udelay(1000);
 104
 105         /* get config bits */
 106         value = in_be32((void*)GPIO0_IR) & 0x001c0000;
 107         /*
 108          * Restore GPIO settings
 109          */
 110         mtdcr(CPC0_CR0, CPC0_CR0Reg);
 111
 112         switch (value) {
 113         case 0x001c0000:
 114                 /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
 115                 return 2;
 116         case 0x000c0000:
 117                 /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
 118                 return 3;
 119         case 0x00180000:
 120                 /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
 121                 return 6;
 122         case 0x00140000:
 123                 /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
 124                 return 8;
 125         default:
 126                 /* should not be reached! */
 127                 return 0;
 128         }
 129 }
 130
 131 int board_early_init_f (void)
 132 {
 133         /*
 134          * First pull fpga-prg pin low, to disable fpga logic
 135          */
 136         out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
 137         out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
 138         out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
 139
 140         /*
 141          * IRQ 0-15  405GP internally generated; active high; level sensitive
 142          * IRQ 16    405GP internally generated; active low; level sensitive
 143          * IRQ 17-24 RESERVED
 144          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 145          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 146          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 147          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 148          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 149          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 150          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 151          */
 152         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 153         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
 154         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
 155         mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
 156         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
 157         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
 158         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 159
 160         /*
 161          * EBC Configuration Register: set ready timeout to 512 ebc-clks
 162          */
 163         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 164
 165         /*
 166          * New boards have a single 32MB flash connected to CS0
 167          * instead of two 16MB flashes on CS0+1.
 168          */
 169         if (board_revision() >= 8) {
 170                 /* disable CS1 */
 171                 mtebc(PB1AP, 0);
 172                 mtebc(PB1CR, 0);
 173
 174                 /* resize CS0 to 32MB */
 175                 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
 176                 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
 177         }
 178
 179         return 0;
 180 }
 181
 182 int board_early_init_r(void)
 183 {
 184         if (gd->board_type >= 8)
 185                 cfi_flash_num_flash_banks = 1;
 186
 187         return 0;
 188 }
 189
 190 #define FUJI_BASE    0xf0100200
 191 #define LCDBL_PWM    0xa0
 192 #define LCDBL_PWMMIN 0xa4
 193 #define LCDBL_PWMMAX 0xa8
 194
 195 int misc_init_r(void)
 196 {
 197         u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 198         u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
 199         u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
 200         u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
 201         unsigned char *dst;
 202         ulong len = sizeof(fpgadata);
 203         int status;
 204         int index;
 205         int i;
 206         unsigned long CPC0_CR0Reg;
 207         char *str;
 208         uchar *logo_addr;
 209         ulong logo_size;
 210         ushort minb, maxb;
 211         int result;
 212
 213         /*
 214          * Setup GPIO pins (CS6+CS7 as GPIO)
 215          */
 216         CPC0_CR0Reg = mfdcr(CPC0_CR0);
 217         mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 218
 219         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 220         if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 221                 printf("GUNZIP ERROR - must RESET board to recover\n");
 222                 do_reset(NULL, 0, 0, NULL);
 223         }
 224
 225         status = fpga_boot(dst, len);
 226         if (status != 0) {
 227                 printf("\nFPGA: Booting failed ");
 228                 switch (status) {
 229                 case ERROR_FPGA_PRG_INIT_LOW:
 230                         printf("(Timeout: "
 231                                "INIT not low after asserting PROGRAM*)\n ");
 232                         break;
 233                 case ERROR_FPGA_PRG_INIT_HIGH:
 234                         printf("(Timeout: "
 235                                "INIT not high after deasserting PROGRAM*)\n ");
 236                         break;
 237                 case ERROR_FPGA_PRG_DONE:
 238                         printf("(Timeout: "
 239                                "DONE not high after programming FPGA)\n ");
 240                         break;
 241                 }
 242
 243                 /* display infos on fpgaimage */
 244                 index = 15;
 245                 for (i = 0; i < 4; i++) {
 246                         len = dst[index];
 247                         printf("FPGA: %s\n", &(dst[index+1]));
 248                         index += len + 3;
 249                 }
 250                 putc('\n');
 251                 /* delayed reboot */
 252                 for (i = 20; i > 0; i--) {
 253                         printf("Rebooting in %2d seconds \r",i);
 254                         for (index = 0; index < 1000; index++)
 255                                 udelay(1000);
 256                 }
 257                 putc('\n');
 258                 do_reset(NULL, 0, 0, NULL);
 259         }
 260
 261         /* restore gpio/cs settings */
 262         mtdcr(CPC0_CR0, CPC0_CR0Reg);
 263
 264         puts("FPGA:  ");
 265
 266         /* display infos on fpgaimage */
 267         index = 15;
 268         for (i = 0; i < 4; i++) {
 269                 len = dst[index];
 270                 printf("%s ", &(dst[index + 1]));
 271                 index += len + 3;
 272         }
 273         putc('\n');
 274
 275         free(dst);
 276
 277         /*
 278          * Reset FPGA via FPGA_DATA pin
 279          */
 280         SET_FPGA(FPGA_PRG | FPGA_CLK);
 281         udelay(1000); /* wait 1ms */
 282         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 283         udelay(1000); /* wait 1ms */
 284
 285         /*
 286          * Write board revision in FPGA
 287          */
 288         out_be16(fpga_ctrl2,
 289                  (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
 290
 291         /*
 292          * Enable power on PS/2 interface (with reset)
 293          */
 294         out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 295         for (i=0;i<100;i++)
 296                 udelay(1000);
 297         udelay(1000);
 298         out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 299
 300         /*
 301          * Enable interrupts in exar duart mcr[3]
 302          */
 303         out_8(duart0_mcr, 0x08);
 304         out_8(duart1_mcr, 0x08);
 305
 306         /*
 307          * Init lcd interface and display logo
 308          */
 309         str = getenv("splashimage");
 310         if (str) {
 311                 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
 312                 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 313         } else {
 314                 logo_addr = logo_bmp;
 315                 logo_size = sizeof(logo_bmp);
 316         }
 317
 318         if (gd->board_type >= 6) {
 319                 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 320                                   (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 321                                   regs_13505_640_480_16bpp,
 322                                   sizeof(regs_13505_640_480_16bpp) /
 323                                   sizeof(regs_13505_640_480_16bpp[0]),
 324                                   logo_addr, logo_size);
 325                 if (result && str) {
 326                         /* retry with internal image */
 327                         logo_addr = logo_bmp;
 328                         logo_size = sizeof(logo_bmp);
 329                         lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 330                                  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 331                                  regs_13505_640_480_16bpp,
 332                                  sizeof(regs_13505_640_480_16bpp) /
 333                                  sizeof(regs_13505_640_480_16bpp[0]),
 334                                  logo_addr, logo_size);
 335                 }
 336         } else {
 337                 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 338                                   (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 339                                   regs_13806_640_480_16bpp,
 340                                   sizeof(regs_13806_640_480_16bpp) /
 341                                   sizeof(regs_13806_640_480_16bpp[0]),
 342                                   logo_addr, logo_size);
 343                 if (result && str) {
 344                         /* retry with internal image */
 345                         logo_addr = logo_bmp;
 346                         logo_size = sizeof(logo_bmp);
 347                         lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
 348                                  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 349                                  regs_13806_640_480_16bpp,
 350                                  sizeof(regs_13806_640_480_16bpp) /
 351                                  sizeof(regs_13806_640_480_16bpp[0]),
 352                                  logo_addr, logo_size);
 353                 }
 354         }
 355
 356         /*
 357          * Reset microcontroller and setup backlight PWM controller
 358          */
 359         out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
 360         for (i=0;i<10;i++)
 361                 udelay(1000);
 362         out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
 363
 364         minb = 0;
 365         maxb = 0xff;
 366         str = getenv("lcdbl");
 367         if (str) {
 368                 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
 369                 if (str && (*str=',')) {
 370                         str++;
 371                         maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
 372                 } else
 373                         minb = 0;
 374
 375                 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
 376                 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
 377
 378                 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
 379         }
 380         out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
 381
 382         /*
 383          * fix environment for field updated units
 384          */
 385         if (getenv("altbootcmd") == NULL) {
 386                 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
 387                 setenv("usbargs", CONFIG_SYS_USB_ARGS);
 388                 setenv("bootcmd", CONFIG_BOOTCOMMAND);
 389                 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
 390                 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
 391                 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
 392                 saveenv();
 393         }
 394
 395         return (0);
 396 }
 397
 398 /*
 399  * Check Board Identity:
 400  */
 401 int checkboard (void)
 402 {
 403         char str[64];
 404         int i = getenv_f("serial#", str, sizeof(str));
 405
 406         puts ("Board: ");
 407
 408         if (i == -1) {
 409                 puts ("### No HW ID - assuming APC405");
 410         } else {
 411                 puts(str);
 412         }
 413
 414         gd->board_type = board_revision();
 415         printf(", Rev. 1.%ld\n", gd->board_type);
 416
 417         return 0;
 418 }
 419
 420 #ifdef CONFIG_IDE_RESET
 421 void ide_set_reset(int on)
 422 {
 423         u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 424
 425         /*
 426          * Assert or deassert CompactFlash Reset Pin
 427          */
 428         if (on) {
 429                 out_be16(fpga_mode,
 430                          in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 431         } else {
 432                 out_be16(fpga_mode,
 433                          in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 434         }
 435 }
 436 #endif /* CONFIG_IDE_RESET */
 437
 438 void reset_phy(void)
 439 {
 440         /*
 441          * Disable sleep mode in LXT971
 442          */
 443         lxt971_no_sleep();
 444 }
 445
 446 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 447 int usb_board_init(void)
 448 {
 449         return 0;
 450 }
 451
 452 int usb_board_stop(void)
 453 {
 454         unsigned short tmp;
 455         int i;
 456
 457         /*
 458          * reset PCI bus
 459          * This is required to make some very old Linux OHCI driver
 460          * work after U-Boot has used the OHCI controller.
 461          */
 462         pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
 463         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
 464
 465         for (i = 0; i < 100; i++)
 466                 udelay(1000);
 467
 468         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
 469         return 0;
 470 }
 471
 472 int usb_board_init_fail(void)
 473 {
 474         usb_board_stop();
 475         return 0;
 476 }
 477 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */