board/esd/hh405/hh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006-2007
   9  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <asm/processor.h>
  32 #include <asm/io.h>
  33 #include <command.h>
  34 #include <malloc.h>
  35 #include <pci.h>
  36 #include <sm501.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 /* FPGA internal regs */
  41 #define FPGA_CTRL       ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
  42 #define FPGA_STATUS     ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
  43 #define FPGA_CTR        ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
  44 #define FPGA_BL         ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
  45
  46 /* FPGA Control Reg */
  47 #define FPGA_CTRL_REV0      0x0001
  48 #define FPGA_CTRL_REV1      0x0002
  49 #define FPGA_CTRL_VGA0_BL   0x0004
  50 #define FPGA_CTRL_VGA0_BL_MODE 0x0008
  51 #define FPGA_CTRL_CF_RESET  0x0040
  52 #define FPGA_CTRL_PS2_PWR   0x0080
  53 #define FPGA_CTRL_CF_PWRN   0x0100      /* low active */
  54 #define FPGA_CTRL_CF_BUS_EN 0x0200
  55 #define FPGA_CTRL_LCD_CLK   0x7000      /* mask for lcd clock */
  56 #define FPGA_CTRL_OW_ENABLE 0x8000
  57
  58 #define FPGA_STATUS_CF_DETECT 0x8000
  59
  60 #ifdef CONFIG_VIDEO_SM501
  61
  62 #define SWAP32(x)        ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
  63                           (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
  64
  65 #ifdef CONFIG_VIDEO_SM501_8BPP
  66 #error CONFIG_VIDEO_SM501_8BPP not supported.
  67 #endif /* CONFIG_VIDEO_SM501_8BPP */
  68
  69 #ifdef CONFIG_VIDEO_SM501_16BPP
  70 #define BPP     16
  71
  72 /*
  73  * 800x600 display B084SN03: PCLK = 40MHz
  74  * => 2*PCLK = 80MHz
  75  * 336/4 = 84MHz
  76  * => PCLK = 84MHz
  77  */
  78 static const SMI_REGS init_regs_800x600 [] =
  79 {
  80 #if 1 /* test-only */
  81         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
  82 #else
  83         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
  84 #endif
  85         {0x00004, SWAP32(0x00000000)},
  86         /* clocks for pm1... */
  87         {0x00048, SWAP32(0x00021807)},
  88         {0x0004C, SWAP32(0x221a0a01)},
  89         {0x00054, SWAP32(0x00000001)},
  90         /* clocks for pm0... */
  91         {0x00040, SWAP32(0x00021807)},
  92         {0x00044, SWAP32(0x221a0a01)},
  93         {0x00054, SWAP32(0x00000000)},
  94         /* GPIO */
  95         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
  96         /* panel control regs... */
  97         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
  98         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
  99         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 100         {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
 101         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
 102         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
 103         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 104         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
 105         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
 106         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
 107         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
 108         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
 109         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 110         {0, 0}
 111 };
 112
 113 /*
 114  * 1024x768 display G150XG02: PCLK = 65MHz
 115  * => 2*PCLK = 130MHz
 116  * 288/2 = 144MHz
 117  * => PCLK = 72MHz
 118  */
 119 static const SMI_REGS init_regs_1024x768 [] =
 120 {
 121         {0x00004, SWAP32(0x00000000)},
 122         /* clocks for pm1... */
 123         {0x00048, SWAP32(0x00021807)},
 124         {0x0004C, SWAP32(0x011a0a01)},
 125         {0x00054, SWAP32(0x00000001)},
 126         /* clocks for pm0... */
 127         {0x00040, SWAP32(0x00021807)},
 128         {0x00044, SWAP32(0x011a0a01)},
 129         {0x00054, SWAP32(0x00000000)},
 130         /* GPIO */
 131         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
 132         /* panel control regs... */
 133         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
 134         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 135         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 136         {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
 137         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
 138         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
 139         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 140         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
 141         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
 142         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
 143         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
 144         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
 145         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 146         {0, 0}
 147 };
 148
 149 #endif /* CONFIG_VIDEO_SM501_16BPP */
 150
 151 #ifdef CONFIG_VIDEO_SM501_32BPP
 152 #define BPP     32
 153
 154 /*
 155  * 800x600 display B084SN03: PCLK = 40MHz
 156  * => 2*PCLK = 80MHz
 157  * 336/4 = 84MHz
 158  * => PCLK = 84MHz
 159  */
 160 static const SMI_REGS init_regs_800x600 [] =
 161 {
 162 #if 0 /* test-only */
 163         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
 164 #else
 165         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
 166 #endif
 167         {0x00004, SWAP32(0x00000000)},
 168         /* clocks for pm1... */
 169         {0x00048, SWAP32(0x00021807)},
 170         {0x0004C, SWAP32(0x221a0a01)},
 171         {0x00054, SWAP32(0x00000001)},
 172         /* clocks for pm0... */
 173         {0x00040, SWAP32(0x00021807)},
 174         {0x00044, SWAP32(0x221a0a01)},
 175         {0x00054, SWAP32(0x00000000)},
 176         /* GPIO */
 177         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
 178         /* panel control regs... */
 179         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
 180         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 181         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 182         {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
 183         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
 184         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
 185         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 186         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
 187         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
 188         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
 189         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
 190         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
 191         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 192         {0, 0}
 193 };
 194
 195 /*
 196  * 1024x768 display G150XG02: PCLK = 65MHz
 197  * => 2*PCLK = 130MHz
 198  * 288/2 = 144MHz
 199  * => PCLK = 72MHz
 200  */
 201 static const SMI_REGS init_regs_1024x768 [] =
 202 {
 203         {0x00004, SWAP32(0x00000000)},
 204         /* clocks for pm1... */
 205         {0x00048, SWAP32(0x00021807)},
 206         {0x0004C, SWAP32(0x011a0a01)},
 207         {0x00054, SWAP32(0x00000001)},
 208         /* clocks for pm0... */
 209         {0x00040, SWAP32(0x00021807)},
 210         {0x00044, SWAP32(0x011a0a01)},
 211         {0x00054, SWAP32(0x00000000)},
 212         /* GPIO */
 213         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
 214         /* panel control regs... */
 215         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
 216         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 217         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 218         {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
 219         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
 220         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
 221         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 222         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
 223         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
 224         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
 225         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
 226         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
 227         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 228         {0, 0}
 229 };
 230
 231 #endif /* CONFIG_VIDEO_SM501_32BPP */
 232
 233 #endif /* CONFIG_VIDEO_SM501 */
 234
 235 #if 0
 236 #define FPGA_DEBUG
 237 #endif
 238
 239 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 240 extern void lxt971_no_sleep(void);
 241
 242 /* fpga configuration data - gzip compressed and generated by bin2c */
 243 const unsigned char fpgadata[] =
 244 {
 245 #include "fpgadata.c"
 246 };
 247
 248 /*
 249  * include common fpga code (for esd boards)
 250  */
 251 #include "../common/fpga.c"
 252
 253
 254 /* Prototypes */
 255 int gunzip(void *, int, unsigned char *, unsigned long *);
 256
 257
 258 /* logo bitmap data - gzip compressed and generated by bin2c */
 259 unsigned char logo_bmp_320[] =
 260 {
 261 #include "logo_320_240_4bpp.c"
 262 };
 263
 264 unsigned char logo_bmp_320_8bpp[] =
 265 {
 266 #include "logo_320_240_8bpp.c"
 267 };
 268
 269 unsigned char logo_bmp_640[] =
 270 {
 271 #include "logo_640_480_24bpp.c"
 272 };
 273
 274 unsigned char logo_bmp_1024[] =
 275 {
 276 #include "logo_1024_768_8bpp.c"
 277 };
 278
 279
 280 /*
 281  * include common lcd code (for esd boards)
 282  */
 283 #include "../common/lcd.c"
 284
 285 #include "../common/s1d13704_320_240_4bpp.h"
 286 #include "../common/s1d13705_320_240_8bpp.h"
 287 #include "../common/s1d13806_640_480_16bpp.h"
 288 #include "../common/s1d13806_1024_768_8bpp.h"
 289
 290
 291 /*
 292  * include common auto-update code (for esd boards)
 293  */
 294 #include "../common/auto_update.h"
 295
 296 au_image_t au_image[] = {
 297         {"hh405/preinst.img", 0, -1, AU_SCRIPT},
 298         {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
 299         {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
 300         {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
 301         {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
 302         {"hh405/postinst.img", 0, 0, AU_SCRIPT},
 303 };
 304
 305 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 306
 307
 308 /*
 309  * Get version of HH405 board from GPIO's
 310  */
 311 int board_revision(void)
 312 {
 313         unsigned long osrh_reg;
 314         unsigned long isr1h_reg;
 315         unsigned long tcr_reg;
 316         unsigned long value;
 317
 318         /*
 319          * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
 320          */
 321         osrh_reg = in_be32((void *)GPIO0_OSRH);
 322         isr1h_reg = in_be32((void *)GPIO0_ISR1H);
 323         tcr_reg = in_be32((void *)GPIO0_TCR);
 324         out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
 325         out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
 326         out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
 327
 328         udelay(1000);            /* wait some time before reading input */
 329         value = in_be32((void *)GPIO0_IR) & 0x80400000;         /* get config bits */
 330
 331         /*
 332          * Restore GPIO settings
 333          */
 334         out_be32((void *)GPIO0_OSRH, osrh_reg);                   /* output select */
 335         out_be32((void *)GPIO0_ISR1H, isr1h_reg);                 /* input select  */
 336         out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
 337
 338         if (value & 0x80000000) {
 339                 /* Revision 1.0 or 1.1 detected */
 340                 return 1;
 341         } else {
 342                 if (value & 0x00400000) {
 343                         /* unused */
 344                         return 3;
 345                 } else {
 346                         return 2;
 347                 }
 348         }
 349 }
 350
 351
 352 int board_early_init_f (void)
 353 {
 354         /*
 355          * IRQ 0-15  405GP internally generated; active high; level sensitive
 356          * IRQ 16    405GP internally generated; active low; level sensitive
 357          * IRQ 17-24 RESERVED
 358          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 359          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 360          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 361          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 362          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 363          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 364          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 365          */
 366         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 367         mtdcr(uicer, 0x00000000);       /* disable all ints */
 368         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 369         mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
 370         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 371         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 372         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 373
 374         /*
 375          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 376          */
 377         mtebc(epcr, 0xa8400000); /* ebc always driven */
 378
 379         return 0;
 380 }
 381
 382 int cf_enable(void)
 383 {
 384         int i;
 385
 386         if (gd->board_type >= 2) {
 387                 if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
 388                         if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
 389                                 out_be16(FPGA_CTRL,
 390                                          in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
 391
 392                                 for (i=0; i<300; i++)
 393                                         udelay(1000);
 394
 395                                 out_be16(FPGA_CTRL,
 396                                          in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
 397
 398                                 for (i=0; i<20; i++)
 399                                         udelay(1000);
 400                         }
 401                 } else {
 402                         out_be16(FPGA_CTRL,
 403                                  in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
 404                         out_be16(FPGA_CTRL,
 405                                  in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
 406                 }
 407         }
 408
 409         return 0;
 410 }
 411
 412 int misc_init_r (void)
 413 {
 414         unsigned char *dst;
 415         ulong len = sizeof(fpgadata);
 416         int status;
 417         int index;
 418         int i;
 419         char *str;
 420         unsigned long contrast0 = 0xffffffff;
 421
 422         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 423         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 424                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 425                 do_reset (NULL, 0, 0, NULL);
 426         }
 427
 428         status = fpga_boot(dst, len);
 429         if (status != 0) {
 430                 printf("\nFPGA: Booting failed ");
 431                 switch (status) {
 432                 case ERROR_FPGA_PRG_INIT_LOW:
 433                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 434                         break;
 435                 case ERROR_FPGA_PRG_INIT_HIGH:
 436                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 437                         break;
 438                 case ERROR_FPGA_PRG_DONE:
 439                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 440                         break;
 441                 }
 442
 443                 /* display infos on fpgaimage */
 444                 index = 15;
 445                 for (i=0; i<4; i++) {
 446                         len = dst[index];
 447                         printf("FPGA: %s\n", &(dst[index+1]));
 448                         index += len+3;
 449                 }
 450                 putc ('\n');
 451                 /* delayed reboot */
 452                 for (i=20; i>0; i--) {
 453                         printf("Rebooting in %2d seconds \r",i);
 454                         for (index=0;index<1000;index++)
 455                                 udelay(1000);
 456                 }
 457                 putc ('\n');
 458                 do_reset(NULL, 0, 0, NULL);
 459         }
 460
 461         puts("FPGA:  ");
 462
 463         /* display infos on fpgaimage */
 464         index = 15;
 465         for (i=0; i<4; i++) {
 466                 len = dst[index];
 467                 printf("%s ", &(dst[index+1]));
 468                 index += len+3;
 469         }
 470         putc ('\n');
 471
 472         free(dst);
 473
 474         /*
 475          * Reset FPGA via FPGA_INIT pin
 476          */
 477         /* setup FPGA_INIT as output */
 478         out_be32((void *)GPIO0_TCR,
 479                  in_be32((void *)GPIO0_TCR) | FPGA_INIT);
 480         out_be32((void *)GPIO0_OR,
 481                  in_be32((void *)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 482         udelay(1000); /* wait 1ms */
 483         out_be32((void *)GPIO0_OR,
 484                  in_be32((void *)GPIO0_OR) | FPGA_INIT);   /* reset high */
 485         udelay(1000); /* wait 1ms */
 486
 487         /*
 488          * Write Board revision into FPGA
 489          */
 490         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
 491
 492         /*
 493          * Setup and enable EEPROM write protection
 494          */
 495         out_be32((void *)GPIO0_OR,
 496                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 497
 498         /*
 499          * Reset touch-screen controller
 500          */
 501         out_be32((void *)GPIO0_OR,
 502                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
 503         udelay(1000);
 504         out_be32((void *)GPIO0_OR,
 505                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
 506
 507         /*
 508          * Enable power on PS/2 interface (with reset)
 509          */
 510         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
 511         for (i=0;i<500;i++)
 512                 udelay(1000);
 513         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
 514
 515         /*
 516          * Get contrast value from environment variable
 517          */
 518         str = getenv("contrast0");
 519         if (str) {
 520                 contrast0 = simple_strtol(str, NULL, 16);
 521                 if (contrast0 > 255) {
 522                         printf("ERROR: contrast0 value too high (0x%lx)!\n",
 523                                contrast0);
 524                         contrast0 = 0xffffffff;
 525                 }
 526         }
 527
 528         /*
 529          * Init lcd interface and display logo
 530          */
 531
 532         str = getenv("bd_type");
 533         if (strcmp(str, "ppc230") == 0) {
 534                 /*
 535                  * Switch backlight on
 536                  */
 537                 out_be16(FPGA_CTRL,
 538                          in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
 539                 out_be16(FPGA_BL, 0x0000);
 540
 541                 lcd_setup(1, 0);
 542                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 543                          regs_13806_1024_768_8bpp,
 544                          sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
 545                          logo_bmp_1024, sizeof(logo_bmp_1024));
 546         } else if (strcmp(str, "ppc220") == 0) {
 547                 /*
 548                  * Switch backlight on
 549                  */
 550                 out_be16(FPGA_CTRL,
 551                          in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
 552                 out_be16(FPGA_BL, 0x0000);
 553
 554                 lcd_setup(1, 0);
 555                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 556                          regs_13806_640_480_16bpp,
 557                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 558                          logo_bmp_640, sizeof(logo_bmp_640));
 559         } else if (strcmp(str, "ppc215") == 0) {
 560                 /*
 561                  * Set default display contrast voltage
 562                  */
 563                 if (contrast0 == 0xffffffff) {
 564                         out_be16(FPGA_CTR, 0x0082);
 565                 } else {
 566                         out_be16(FPGA_CTR, contrast0);
 567                 }
 568                 out_be16(FPGA_BL, 0xffff);
 569                 /*
 570                  * Switch backlight on
 571                  */
 572                 out_be16(FPGA_CTRL,
 573                          in_be16(FPGA_CTRL) |
 574                          FPGA_CTRL_VGA0_BL |
 575                          FPGA_CTRL_VGA0_BL_MODE);
 576                 /*
 577                  * Set lcd clock (small epson)
 578                  */
 579                 out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
 580                 udelay(100);               /* wait for 100 us */
 581
 582                 lcd_setup(0, 1);
 583                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 584                          regs_13705_320_240_8bpp,
 585                          sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
 586                          logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
 587         } else if (strcmp(str, "ppc210") == 0) {
 588                 /*
 589                  * Set default display contrast voltage
 590                  */
 591                 if (contrast0 == 0xffffffff) {
 592                         out_be16(FPGA_CTR, 0x0060);
 593                 } else {
 594                         out_be16(FPGA_CTR, contrast0);
 595                 }
 596                 out_be16(FPGA_BL, 0xffff);
 597                 /*
 598                  * Switch backlight on
 599                  */
 600                 out_be16(FPGA_CTRL,
 601                          in_be16(FPGA_CTRL) |
 602                          FPGA_CTRL_VGA0_BL |
 603                          FPGA_CTRL_VGA0_BL_MODE);
 604                 /*
 605                  * Set lcd clock (small epson), enable 1-wire interface
 606                  */
 607                 out_be16(FPGA_CTRL,
 608                          in_be16(FPGA_CTRL) |
 609                          LCD_CLK_08330 |
 610                          FPGA_CTRL_OW_ENABLE);
 611
 612                 lcd_setup(0, 1);
 613                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 614                          regs_13704_320_240_4bpp,
 615                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 616                          logo_bmp_320, sizeof(logo_bmp_320));
 617 #ifdef CONFIG_VIDEO_SM501
 618         } else {
 619                 pci_dev_t devbusfn;
 620
 621                 /*
 622                  * Is SM501 connected (ppc221/ppc231)?
 623                  */
 624                 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 625                 if (devbusfn != -1) {
 626                         puts("VGA:   SM501 with 8 MB ");
 627                         if (strcmp(str, "ppc221") == 0) {
 628                                 printf("(800*600, %dbpp)\n", BPP);
 629                                 out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
 630                         } else if (strcmp(str, "ppc231") == 0) {
 631                                 printf("(1024*768, %dbpp)\n", BPP);
 632                                 out_be16(FPGA_BL, 0x0000);
 633                         } else {
 634                                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 635                                 return 0;
 636                         }
 637                 } else {
 638                         printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 639                         return 0;
 640                 }
 641 #endif /* CONFIG_VIDEO_SM501 */
 642         }
 643
 644         cf_enable();
 645
 646         return (0);
 647 }
 648
 649
 650 /*
 651  * Check Board Identity:
 652  */
 653
 654 int checkboard (void)
 655 {
 656         char str[64];
 657         int i = getenv_r ("serial#", str, sizeof(str));
 658
 659         puts ("Board: ");
 660
 661         if (i == -1) {
 662                 puts ("### No HW ID - assuming HH405");
 663         } else {
 664                 puts(str);
 665         }
 666
 667         if (getenv_r("bd_type", str, sizeof(str)) != -1) {
 668                 printf(" (%s", str);
 669         } else {
 670                 puts(" (Missing bd_type!");
 671         }
 672
 673         gd->board_type = board_revision();
 674         printf(", Rev %ld.x)\n", gd->board_type);
 675
 676         return 0;
 677 }
 678
 679 #ifdef CONFIG_IDE_RESET
 680 void ide_set_reset(int on)
 681 {
 682         if (((gd->board_type >= 2) &&
 683              (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
 684             (gd->board_type < 2)) {
 685                 /*
 686                  * Assert or deassert CompactFlash Reset Pin
 687                  */
 688                 if (on) {               /* assert RESET */
 689                         cf_enable();
 690                         out_be16(FPGA_CTRL,
 691                                  in_be16(FPGA_CTRL) &
 692                                  ~FPGA_CTRL_CF_RESET);
 693                 } else {                /* release RESET */
 694                         out_be16(FPGA_CTRL,
 695                                  in_be16(FPGA_CTRL) |
 696                                  FPGA_CTRL_CF_RESET);
 697                 }
 698         }
 699 }
 700 #endif /* CONFIG_IDE_RESET */
 701
 702
 703 #if defined(CONFIG_SYS_EEPROM_WREN)
 704 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 705  *         <state>     -1: deliver current state
 706  *                     0: disable write
 707  *                     1: enable write
 708  *  Returns:           -1: wrong device address
 709  *                      0: dis-/en- able done
 710  *                   0/1: current state if <state> was -1.
 711  */
 712 int eeprom_write_enable (unsigned dev_addr, int state)
 713 {
 714         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 715                 return -1;
 716         } else {
 717                 switch (state) {
 718                 case 1:
 719                         /* Enable write access, clear bit GPIO_SINT2. */
 720                         out_be32((void *)GPIO0_OR,
 721                                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 722                         state = 0;
 723                         break;
 724                 case 0:
 725                         /* Disable write access, set bit GPIO_SINT2. */
 726                         out_be32((void *)GPIO0_OR,
 727                                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 728                         state = 0;
 729                         break;
 730                 default:
 731                         /* Read current status back. */
 732                         state = (0 == (in_be32((void *)GPIO0_OR) &
 733                                        CONFIG_SYS_EEPROM_WP));
 734                         break;
 735                 }
 736         }
 737         return state;
 738 }
 739
 740 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 741 {
 742         int query = argc == 1;
 743         int state = 0;
 744
 745         if (query) {
 746                 /* Query write access state. */
 747                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 748                 if (state < 0) {
 749                         puts ("Query of write access state failed.\n");
 750                 } else {
 751                         printf ("Write access for device 0x%0x is %sabled.\n",
 752                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 753                         state = 0;
 754                 }
 755         } else {
 756                 if ('0' == argv[1][0]) {
 757                         /* Disable write access. */
 758                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 759                 } else {
 760                         /* Enable write access. */
 761                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 762                 }
 763                 if (state < 0) {
 764                         puts ("Setup of write access state failed.\n");
 765                 }
 766         }
 767
 768         return state;
 769 }
 770
 771 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 772         "Enable / disable / query EEPROM write access",
 773         ""
 774 );
 775 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 776
 777
 778 #ifdef CONFIG_VIDEO_SM501
 779 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 780 /*
 781  * Return text to be printed besides the logo.
 782  */
 783 void video_get_info_str (int line_number, char *info)
 784 {
 785         char str[64];
 786         char str2[64];
 787         int i = getenv_r("serial#", str2, sizeof(str));
 788
 789         if (line_number == 1) {
 790                 sprintf(str, " Board: ");
 791
 792                 if (i == -1) {
 793                         strcat(str, "### No HW ID - assuming HH405");
 794                 } else {
 795                         strcat(str, str2);
 796                 }
 797
 798                 if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
 799                         strcat(str, " (");
 800                         strcat(str, str2);
 801                 } else {
 802                         strcat(str, " (Missing bd_type!");
 803                 }
 804
 805                 sprintf(str2, ", Rev %ld.x)", gd->board_type);
 806                 strcat(str, str2);
 807                 strcpy(info, str);
 808         } else {
 809                 info [0] = '\0';
 810         }
 811 }
 812 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
 813
 814 /*
 815  * Returns SM501 register base address. First thing called in the driver.
 816  */
 817 unsigned int board_video_init (void)
 818 {
 819         pci_dev_t devbusfn;
 820         u32 addr;
 821
 822         /*
 823          * Is SM501 connected (ppc221/ppc231)?
 824          */
 825         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 826         if (devbusfn != -1) {
 827                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
 828                 return (addr & 0xfffffffe);
 829         }
 830
 831         return 0;
 832 }
 833
 834 /*
 835  * Returns SM501 framebuffer address
 836  */
 837 unsigned int board_video_get_fb (void)
 838 {
 839         pci_dev_t devbusfn;
 840         u32 addr;
 841
 842         /*
 843          * Is SM501 connected (ppc221/ppc231)?
 844          */
 845         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 846         if (devbusfn != -1) {
 847                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
 848                 addr &= 0xfffffffe;
 849 #ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
 850                 addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
 851 #endif
 852                 return addr;
 853         }
 854
 855         return 0;
 856 }
 857
 858 /*
 859  * Called after initializing the SM501 and before clearing the screen.
 860  */
 861 void board_validate_screen (unsigned int base)
 862 {
 863 }
 864
 865 /*
 866  * Return a pointer to the initialization sequence.
 867  */
 868 const SMI_REGS *board_get_regs (void)
 869 {
 870         char *str;
 871
 872         str = getenv("bd_type");
 873         if (strcmp(str, "ppc221") == 0) {
 874                 return init_regs_800x600;
 875         } else {
 876                 return init_regs_1024x768;
 877         }
 878 }
 879
 880 int board_get_width (void)
 881 {
 882         char *str;
 883
 884         str = getenv("bd_type");
 885         if (strcmp(str, "ppc221") == 0) {
 886                 return 800;
 887         } else {
 888                 return 1024;
 889         }
 890 }
 891
 892 int board_get_height (void)
 893 {
 894         char *str;
 895
 896         str = getenv("bd_type");
 897         if (strcmp(str, "ppc221") == 0) {
 898                 return 600;
 899         } else {
 900                 return 768;
 901         }
 902 }
 903
 904 #endif /* CONFIG_VIDEO_SM501 */
 905
 906
 907 void reset_phy(void)
 908 {
 909 #ifdef CONFIG_LXT971_NO_SLEEP
 910
 911         /*
 912          * Disable sleep mode in LXT971
 913          */
 914         lxt971_no_sleep();
 915 #endif
 916 }