3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 #include <405gp_pci.h>
32 /* ------------------------------------------------------------------------- */
38 #define PCI_RECONFIG_MAGIC 0x07081967
41 struct pci_config_regs {
42 unsigned short command;
43 unsigned char latency_timer;
44 unsigned char int_line;
51 /* fpga configuration data - generated by bin2cc */
52 const unsigned char fpgadata[] =
58 * include common fpga code (for esd boards)
60 #include "../common/fpga.c"
64 int gunzip(void *, int, unsigned char *, int *);
67 int board_pre_init (void)
69 unsigned long cntrl0Reg;
72 * IRQ 0-15 405GP internally generated; active high; level sensitive
73 * IRQ 16 405GP internally generated; active low; level sensitive
75 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
76 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
77 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
78 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
79 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
80 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
81 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
83 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
84 mtdcr(uicer, 0x00000000); /* disable all ints */
85 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
86 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
87 mtdcr(uictr, 0x10000000); /* set int trigger levels */
88 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
89 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
92 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
94 cntrl0Reg = mfdcr(cntrl0);
95 mtdcr(cntrl0, cntrl0Reg | 0x00008000);
101 /* ------------------------------------------------------------------------- */
103 int misc_init_f (void)
105 return 0; /* dummy implementation */
109 int misc_init_r (void)
112 ulong len = sizeof(fpgadata);
116 struct pci_config_regs *pci_regs;
119 * On PCI-405 the environment is saved in eeprom!
120 * FPGA can be gzip compressed (malloc) and booted this late.
123 dst = malloc(CFG_FPGA_MAX_SIZE);
124 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
125 printf ("GUNZIP ERROR - must RESET board to recover\n");
126 do_reset (NULL, 0, 0, NULL);
129 status = fpga_boot(dst, len);
131 printf("\nFPGA: Booting failed ");
133 case ERROR_FPGA_PRG_INIT_LOW:
134 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
136 case ERROR_FPGA_PRG_INIT_HIGH:
137 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
139 case ERROR_FPGA_PRG_DONE:
140 printf("(Timeout: DONE not high after programming FPGA)\n ");
144 /* display infos on fpgaimage */
146 for (i=0; i<4; i++) {
148 printf("FPGA: %s\n", &(dst[index+1]));
153 for (i=20; i>0; i--) {
154 printf("Rebooting in %2d seconds \r",i);
155 for (index=0;index<1000;index++)
159 do_reset(NULL, 0, 0, NULL);
164 /* display infos on fpgaimage */
166 for (i=0; i<4; i++) {
168 printf("%s ", &(dst[index+1]));
174 * Rewrite pci config regs (only after soft-reset with magic set)
176 pci_regs = (struct pci_config_regs *)0x10;
177 if (pci_regs->magic == PCI_RECONFIG_MAGIC) {
178 puts("PCI: Found magic, rewriting config regs...\n");
179 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND,
181 pci_write_config_byte(PCIDEVID_405GP, PCI_LATENCY_TIMER,
182 pci_regs->latency_timer);
183 pci_write_config_byte(PCIDEVID_405GP, PCI_INTERRUPT_LINE,
185 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1,
187 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2,
190 pci_regs->magic = 0; /* clear magic again */
192 #if 0 /* test-only */
193 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &(pci_regs->command));
194 pci_read_config_byte(PCIDEVID_405GP, PCI_LATENCY_TIMER, &(pci_regs->latency_timer));
195 pci_read_config_byte(PCIDEVID_405GP, PCI_INTERRUPT_LINE, &(pci_regs->int_line));
196 pci_read_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, &(pci_regs->bar1));
197 pci_read_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, &(pci_regs->bar2));
198 pci_regs->magic = PCI_RECONFIG_MAGIC; /* set magic */
207 * Check Board Identity:
210 int checkboard (void)
212 unsigned char str[64];
213 int i = getenv_r ("serial#", str, sizeof(str));
218 puts ("### No HW ID - assuming CPCI405");
227 /* ------------------------------------------------------------------------- */
229 long int initdram (int board_type)
233 mtdcr(memcfga, mem_mb0cf);
234 val = mfdcr(memcfgd);
237 printf("\nmb0cf=%x\n", val); /* test-only */
238 printf("strap=%x\n", mfdcr(strap)); /* test-only */
241 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
244 /* ------------------------------------------------------------------------- */
248 /* TODO: XXX XXX XXX */
249 printf ("test: 16 MB - ok\n");
254 /* ------------------------------------------------------------------------- */