Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
[karo-tx-uboot.git] / board / freescale / ls1021atwr / ls1021atwr.c
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ns_access.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ls102xa_stream_id.h>
15 #include <asm/pcie_layerscape.h>
16 #include <mmc.h>
17 #include <fsl_esdhc.h>
18 #include <fsl_ifc.h>
19 #include <netdev.h>
20 #include <fsl_mdio.h>
21 #include <tsec.h>
22 #include <fsl_sec.h>
23 #include <spl.h>
24 #ifdef CONFIG_U_QE
25 #include "../../../drivers/qe/qe.h"
26 #endif
27
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define VERSION_MASK            0x00FF
32 #define BANK_MASK               0x0001
33 #define CONFIG_RESET            0x1
34 #define INIT_RESET              0x1
35
36 #define CPLD_SET_MUX_SERDES     0x20
37 #define CPLD_SET_BOOT_BANK      0x40
38
39 #define BOOT_FROM_UPPER_BANK    0x0
40 #define BOOT_FROM_LOWER_BANK    0x1
41
42 #define LANEB_SATA              (0x01)
43 #define LANEB_SGMII1            (0x02)
44 #define LANEC_SGMII1            (0x04)
45 #define LANEC_PCIEX1            (0x08)
46 #define LANED_PCIEX2            (0x10)
47 #define LANED_SGMII2            (0x20)
48
49 #define MASK_LANE_B             0x1
50 #define MASK_LANE_C             0x2
51 #define MASK_LANE_D             0x4
52 #define MASK_SGMII              0x8
53
54 #define KEEP_STATUS             0x0
55 #define NEED_RESET              0x1
56
57 struct cpld_data {
58         u8 cpld_ver;            /* cpld revision */
59         u8 cpld_ver_sub;        /* cpld sub revision */
60         u8 pcba_ver;            /* pcb revision number */
61         u8 system_rst;          /* reset system by cpld */
62         u8 soft_mux_on;         /* CPLD override physical switches Enable */
63         u8 cfg_rcw_src1;        /* Reset config word 1 */
64         u8 cfg_rcw_src2;        /* Reset config word 2 */
65         u8 vbank;               /* Flash bank selection Control */
66         u8 gpio;                /* GPIO for TWR-ELEV */
67         u8 i2c3_ifc_mux;
68         u8 mux_spi2;
69         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
70         u8 qe_lcd_mux;          /* QE and LCD Selection */
71         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
72         u8 global_rst;          /* reset with init CPLD reg to default */
73         u8 rev1;                /* Reserved */
74         u8 rev2;                /* Reserved */
75 };
76
77 #ifndef CONFIG_QSPI_BOOT
78 static void convert_serdes_mux(int type, int need_reset);
79
80 void cpld_show(void)
81 {
82         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
83
84         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
85                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
86                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
87                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
88                in_8(&cpld_data->vbank) & BANK_MASK);
89
90 #ifdef CONFIG_DEBUG
91         printf("soft_mux_on =%x\n",
92                in_8(&cpld_data->soft_mux_on));
93         printf("cfg_rcw_src1 =%x\n",
94                in_8(&cpld_data->cfg_rcw_src1));
95         printf("cfg_rcw_src2 =%x\n",
96                in_8(&cpld_data->cfg_rcw_src2));
97         printf("vbank =%x\n",
98                in_8(&cpld_data->vbank));
99         printf("gpio =%x\n",
100                in_8(&cpld_data->gpio));
101         printf("i2c3_ifc_mux =%x\n",
102                in_8(&cpld_data->i2c3_ifc_mux));
103         printf("mux_spi2 =%x\n",
104                in_8(&cpld_data->mux_spi2));
105         printf("can3_usb2_mux =%x\n",
106                in_8(&cpld_data->can3_usb2_mux));
107         printf("qe_lcd_mux =%x\n",
108                in_8(&cpld_data->qe_lcd_mux));
109         printf("serdes_mux =%x\n",
110                in_8(&cpld_data->serdes_mux));
111 #endif
112 }
113 #endif
114
115 int checkboard(void)
116 {
117         puts("Board: LS1021ATWR\n");
118 #ifndef CONFIG_QSPI_BOOT
119         cpld_show();
120 #endif
121
122         return 0;
123 }
124
125 void ddrmc_init(void)
126 {
127         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
128
129         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
130
131         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
132         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
133
134         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
135         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
136         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
137         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
138         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
139         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
140
141         out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
142
143         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
144         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
145
146         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
147
148         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
149
150         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
151         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
152
153         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
154         out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
155
156         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
157         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
158
159         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
160         udelay(1);
161         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
162 }
163
164 int dram_init(void)
165 {
166 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
167         ddrmc_init();
168 #endif
169
170         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
171         return 0;
172 }
173
174 #ifdef CONFIG_FSL_ESDHC
175 struct fsl_esdhc_cfg esdhc_cfg[1] = {
176         {CONFIG_SYS_FSL_ESDHC_ADDR},
177 };
178
179 int board_mmc_init(bd_t *bis)
180 {
181         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
182
183         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
184 }
185 #endif
186
187 #ifdef CONFIG_TSEC_ENET
188 int board_eth_init(bd_t *bis)
189 {
190         struct fsl_pq_mdio_info mdio_info;
191         struct tsec_info_struct tsec_info[4];
192         int num = 0;
193
194 #ifdef CONFIG_TSEC1
195         SET_STD_TSEC_INFO(tsec_info[num], 1);
196         if (is_serdes_configured(SGMII_TSEC1)) {
197                 puts("eTSEC1 is in sgmii mode.\n");
198                 tsec_info[num].flags |= TSEC_SGMII;
199         }
200         num++;
201 #endif
202 #ifdef CONFIG_TSEC2
203         SET_STD_TSEC_INFO(tsec_info[num], 2);
204         if (is_serdes_configured(SGMII_TSEC2)) {
205                 puts("eTSEC2 is in sgmii mode.\n");
206                 tsec_info[num].flags |= TSEC_SGMII;
207         }
208         num++;
209 #endif
210 #ifdef CONFIG_TSEC3
211         SET_STD_TSEC_INFO(tsec_info[num], 3);
212         num++;
213 #endif
214         if (!num) {
215                 printf("No TSECs initialized\n");
216                 return 0;
217         }
218
219         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
220         mdio_info.name = DEFAULT_MII_NAME;
221         fsl_pq_mdio_init(bis, &mdio_info);
222
223         tsec_eth_init(bis, tsec_info, num);
224
225         return pci_eth_init(bis);
226 }
227 #endif
228
229 #ifndef CONFIG_QSPI_BOOT
230 int config_serdes_mux(void)
231 {
232         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
233         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
234
235         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
236         switch (protocol) {
237         case 0x10:
238                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
239                 convert_serdes_mux(LANED_PCIEX2 |
240                                 LANEC_PCIEX1, KEEP_STATUS);
241                 break;
242         case 0x20:
243                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
244                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
245                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
246                 break;
247         case 0x30:
248                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
249                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
250                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
251                 break;
252         case 0x70:
253                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
254                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
255                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
256                 break;
257         }
258
259         return 0;
260 }
261 #endif
262
263 int board_early_init_f(void)
264 {
265         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
266
267 #ifdef CONFIG_TSEC_ENET
268         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
269         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
270 #endif
271
272 #ifdef CONFIG_FSL_IFC
273         init_early_memctl_regs();
274 #endif
275
276 #ifdef CONFIG_FSL_DCU_FB
277         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
278 #endif
279
280 #ifdef CONFIG_FSL_QSPI
281         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
282 #endif
283
284         return 0;
285 }
286
287 #ifdef CONFIG_SPL_BUILD
288 void board_init_f(ulong dummy)
289 {
290         /* Set global data pointer */
291         gd = &gdata;
292
293         /* Clear the BSS */
294         memset(__bss_start, 0, __bss_end - __bss_start);
295
296         get_clocks();
297
298         preloader_console_init();
299
300         dram_init();
301
302         board_init_r(NULL, 0);
303 }
304 #endif
305
306 #ifdef CONFIG_LS102XA_NS_ACCESS
307 static struct csu_ns_dev ns_dev[] = {
308         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
309         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
310         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
311         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
312         { CSU_CSLX_OCRAM, CSU_ALL_RW },
313         { CSU_CSLX_GIC, CSU_ALL_RW },
314         { CSU_CSLX_PCIE1, CSU_ALL_RW },
315         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
316         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
317         { CSU_CSLX_PCIE2, CSU_ALL_RW },
318         { CSU_CSLX_SATA, CSU_ALL_RW },
319         { CSU_CSLX_USB3, CSU_ALL_RW },
320         { CSU_CSLX_SERDES, CSU_ALL_RW },
321         { CSU_CSLX_QDMA, CSU_ALL_RW },
322         { CSU_CSLX_LPUART2, CSU_ALL_RW },
323         { CSU_CSLX_LPUART1, CSU_ALL_RW },
324         { CSU_CSLX_LPUART4, CSU_ALL_RW },
325         { CSU_CSLX_LPUART3, CSU_ALL_RW },
326         { CSU_CSLX_LPUART6, CSU_ALL_RW },
327         { CSU_CSLX_LPUART5, CSU_ALL_RW },
328         { CSU_CSLX_DSPI2, CSU_ALL_RW },
329         { CSU_CSLX_DSPI1, CSU_ALL_RW },
330         { CSU_CSLX_QSPI, CSU_ALL_RW },
331         { CSU_CSLX_ESDHC, CSU_ALL_RW },
332         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
333         { CSU_CSLX_IFC, CSU_ALL_RW },
334         { CSU_CSLX_I2C1, CSU_ALL_RW },
335         { CSU_CSLX_USB2, CSU_ALL_RW },
336         { CSU_CSLX_I2C3, CSU_ALL_RW },
337         { CSU_CSLX_I2C2, CSU_ALL_RW },
338         { CSU_CSLX_DUART2, CSU_ALL_RW },
339         { CSU_CSLX_DUART1, CSU_ALL_RW },
340         { CSU_CSLX_WDT2, CSU_ALL_RW },
341         { CSU_CSLX_WDT1, CSU_ALL_RW },
342         { CSU_CSLX_EDMA, CSU_ALL_RW },
343         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
344         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
345         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
346         { CSU_CSLX_DDR, CSU_ALL_RW },
347         { CSU_CSLX_QUICC, CSU_ALL_RW },
348         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
349         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
350         { CSU_CSLX_SFP, CSU_ALL_RW },
351         { CSU_CSLX_TMU, CSU_ALL_RW },
352         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
353         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
354         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
355         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
356         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
357         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
358         { CSU_CSLX_GPIO2, CSU_ALL_RW },
359         { CSU_CSLX_GPIO1, CSU_ALL_RW },
360         { CSU_CSLX_GPIO4, CSU_ALL_RW },
361         { CSU_CSLX_GPIO3, CSU_ALL_RW },
362         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
363         { CSU_CSLX_CSU, CSU_ALL_RW },
364         { CSU_CSLX_ASRC, CSU_ALL_RW },
365         { CSU_CSLX_SPDIF, CSU_ALL_RW },
366         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
367         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
368         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
369         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
370         { CSU_CSLX_SAI2, CSU_ALL_RW },
371         { CSU_CSLX_SAI1, CSU_ALL_RW },
372         { CSU_CSLX_SAI4, CSU_ALL_RW },
373         { CSU_CSLX_SAI3, CSU_ALL_RW },
374         { CSU_CSLX_FTM2, CSU_ALL_RW },
375         { CSU_CSLX_FTM1, CSU_ALL_RW },
376         { CSU_CSLX_FTM4, CSU_ALL_RW },
377         { CSU_CSLX_FTM3, CSU_ALL_RW },
378         { CSU_CSLX_FTM6, CSU_ALL_RW },
379         { CSU_CSLX_FTM5, CSU_ALL_RW },
380         { CSU_CSLX_FTM8, CSU_ALL_RW },
381         { CSU_CSLX_FTM7, CSU_ALL_RW },
382         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
383         { CSU_CSLX_EPU, CSU_ALL_RW },
384         { CSU_CSLX_GDI, CSU_ALL_RW },
385         { CSU_CSLX_DDI, CSU_ALL_RW },
386         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
387         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
388         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
389 };
390 #endif
391
392 struct smmu_stream_id dev_stream_id[] = {
393         { 0x100, 0x01, "ETSEC MAC1" },
394         { 0x104, 0x02, "ETSEC MAC2" },
395         { 0x108, 0x03, "ETSEC MAC3" },
396         { 0x10c, 0x04, "PEX1" },
397         { 0x110, 0x05, "PEX2" },
398         { 0x114, 0x06, "qDMA" },
399         { 0x118, 0x07, "SATA" },
400         { 0x11c, 0x08, "USB3" },
401         { 0x120, 0x09, "QE" },
402         { 0x124, 0x0a, "eSDHC" },
403         { 0x128, 0x0b, "eMA" },
404         { 0x14c, 0x0c, "2D-ACE" },
405         { 0x150, 0x0d, "USB2" },
406         { 0x18c, 0x0e, "DEBUG" },
407 };
408
409 int board_init(void)
410 {
411         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
412
413         /*
414          * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
415          * All transactions are treated as non-shareable
416          */
417         out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
418         out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
419         out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
420
421 #ifndef CONFIG_SYS_FSL_NO_SERDES
422         fsl_serdes_init();
423 #ifndef CONFIG_QSPI_BOOT
424         config_serdes_mux();
425 #endif
426 #endif
427
428         ls102xa_config_smmu_stream_id(dev_stream_id,
429                                       ARRAY_SIZE(dev_stream_id));
430
431 #ifdef CONFIG_LS102XA_NS_ACCESS
432         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
433 #endif
434
435 #ifdef CONFIG_U_QE
436         u_qe_init();
437 #endif
438
439         return 0;
440 }
441
442 #if defined(CONFIG_MISC_INIT_R)
443 int misc_init_r(void)
444 {
445 #ifdef CONFIG_FSL_CAAM
446         return sec_init();
447 #endif
448 }
449 #endif
450
451 int ft_board_setup(void *blob, bd_t *bd)
452 {
453         ft_cpu_setup(blob, bd);
454
455 #ifdef CONFIG_PCIE_LAYERSCAPE
456         ft_pcie_setup(blob, bd);
457 #endif
458
459         return 0;
460 }
461
462 u8 flash_read8(void *addr)
463 {
464         return __raw_readb(addr + 1);
465 }
466
467 void flash_write16(u16 val, void *addr)
468 {
469         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
470
471         __raw_writew(shftval, addr);
472 }
473
474 u16 flash_read16(void *addr)
475 {
476         u16 val = __raw_readw(addr);
477
478         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
479 }
480
481 #ifndef CONFIG_QSPI_BOOT
482 static void convert_flash_bank(char bank)
483 {
484         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
485
486         printf("Now switch to boot from flash bank %d.\n", bank);
487         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
488         cpld_data->vbank = bank;
489
490         printf("Reset board to enable configuration.\n");
491         cpld_data->system_rst = CONFIG_RESET;
492 }
493
494 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
495                           char * const argv[])
496 {
497         if (argc != 2)
498                 return CMD_RET_USAGE;
499         if (strcmp(argv[1], "0") == 0)
500                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
501         else if (strcmp(argv[1], "1") == 0)
502                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
503         else
504                 return CMD_RET_USAGE;
505
506         return 0;
507 }
508
509 U_BOOT_CMD(
510         boot_bank, 2, 0, flash_bank_cmd,
511         "Flash bank Selection Control",
512         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
513 );
514
515 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
516                           char * const argv[])
517 {
518         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
519
520         if (argc > 2)
521                 return CMD_RET_USAGE;
522         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
523                 cpld_data->system_rst = CONFIG_RESET;
524         else if (strcmp(argv[1], "init") == 0)
525                 cpld_data->global_rst = INIT_RESET;
526         else
527                 return CMD_RET_USAGE;
528
529         return 0;
530 }
531
532 U_BOOT_CMD(
533         cpld_reset, 2, 0, cpld_reset_cmd,
534         "Reset via CPLD",
535         "conf\n"
536         "       -reset with current CPLD configuration\n"
537         "init\n"
538         "       -reset and initial CPLD configuration with default value"
539
540 );
541
542 static void convert_serdes_mux(int type, int need_reset)
543 {
544         char current_serdes;
545         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
546
547         current_serdes = cpld_data->serdes_mux;
548
549         switch (type) {
550         case LANEB_SATA:
551                 current_serdes &= ~MASK_LANE_B;
552                 break;
553         case LANEB_SGMII1:
554                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
555                 break;
556         case LANEC_SGMII1:
557                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
558                 break;
559         case LANED_SGMII2:
560                 current_serdes |= MASK_LANE_D;
561                 break;
562         case LANEC_PCIEX1:
563                 current_serdes |= MASK_LANE_C;
564                 break;
565         case (LANED_PCIEX2 | LANEC_PCIEX1):
566                 current_serdes |= MASK_LANE_C;
567                 current_serdes &= ~MASK_LANE_D;
568                 break;
569         default:
570                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
571                 return;
572         }
573
574         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
575         cpld_data->serdes_mux = current_serdes;
576
577         if (need_reset == 1) {
578                 printf("Reset board to enable configuration\n");
579                 cpld_data->system_rst = CONFIG_RESET;
580         }
581 }
582
583 void print_serdes_mux(void)
584 {
585         char current_serdes;
586         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
587
588         current_serdes = cpld_data->serdes_mux;
589
590         printf("Serdes Lane B: ");
591         if ((current_serdes & MASK_LANE_B) == 0)
592                 printf("SATA,\n");
593         else
594                 printf("SGMII 1,\n");
595
596         printf("Serdes Lane C: ");
597         if ((current_serdes & MASK_LANE_C) == 0)
598                 printf("SGMII 1,\n");
599         else
600                 printf("PCIe,\n");
601
602         printf("Serdes Lane D: ");
603         if ((current_serdes & MASK_LANE_D) == 0)
604                 printf("PCIe,\n");
605         else
606                 printf("SGMII 2,\n");
607
608         printf("SGMII 1 is on lane ");
609         if ((current_serdes & MASK_SGMII) == 0)
610                 printf("C.\n");
611         else
612                 printf("B.\n");
613 }
614
615 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
616                           char * const argv[])
617 {
618         if (argc != 2)
619                 return CMD_RET_USAGE;
620         if (strcmp(argv[1], "sata") == 0) {
621                 printf("Set serdes lane B to SATA.\n");
622                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
623         } else if (strcmp(argv[1], "sgmii1b") == 0) {
624                 printf("Set serdes lane B to SGMII 1.\n");
625                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
626         } else if (strcmp(argv[1], "sgmii1c") == 0) {
627                 printf("Set serdes lane C to SGMII 1.\n");
628                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
629         } else if (strcmp(argv[1], "sgmii2") == 0) {
630                 printf("Set serdes lane D to SGMII 2.\n");
631                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
632         } else if (strcmp(argv[1], "pciex1") == 0) {
633                 printf("Set serdes lane C to PCIe X1.\n");
634                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
635         } else if (strcmp(argv[1], "pciex2") == 0) {
636                 printf("Set serdes lane C & lane D to PCIe X2.\n");
637                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
638         } else if (strcmp(argv[1], "show") == 0) {
639                 print_serdes_mux();
640         } else {
641                 return CMD_RET_USAGE;
642         }
643
644         return 0;
645 }
646
647 U_BOOT_CMD(
648         lane_bank, 2, 0, serdes_mux_cmd,
649         "Multiplexed function setting for SerDes Lanes",
650         "sata\n"
651         "       -change lane B to sata\n"
652         "lane_bank sgmii1b\n"
653         "       -change lane B to SGMII1\n"
654         "lane_bank sgmii1c\n"
655         "       -change lane C to SGMII1\n"
656         "lane_bank sgmii2\n"
657         "       -change lane D to SGMII2\n"
658         "lane_bank pciex1\n"
659         "       -change lane C to PCIeX1\n"
660         "lane_bank pciex2\n"
661         "       -change lane C & lane D to PCIeX2\n"
662         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
663 );
664 #endif