board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/immap_fsl_pci.h>
  30 #include <asm/fsl_ddr_sdram.h>
  31 #include <asm/io.h>
  32 #include <miiphy.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35 #include <tsec.h>
  36 #include <netdev.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  42 extern void ddr_enable_ecc(unsigned int dram_size);
  43 #endif
  44
  45 int checkboard (void)
  46 {
  47         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  48         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  49         volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  50
  51         if ((uint)&gur->porpllsr != 0xe00e0000) {
  52                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  53         }
  54         printf ("Board: MPC8544DS, System ID: 0x%02x, "
  55                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  56                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  57                 in8(PIXIS_BASE + PIXIS_PVER));
  58
  59         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  60         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  61         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  62         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  63
  64         return 0;
  65 }
  66
  67 phys_size_t
  68 initdram(int board_type)
  69 {
  70         long dram_size = 0;
  71
  72         puts("Initializing\n");
  73
  74         dram_size = fsl_ddr_sdram();
  75
  76         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  77
  78         dram_size *= 0x100000;
  79
  80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  81         /*
  82          * Initialize and enable DDR ECC.
  83          */
  84         ddr_enable_ecc(dram_size);
  85 #endif
  86         puts("    DDR: ");
  87         return dram_size;
  88 }
  89
  90 #ifdef CONFIG_PCI1
  91 static struct pci_controller pci1_hose;
  92 #endif
  93
  94 #ifdef CONFIG_PCIE1
  95 static struct pci_controller pcie1_hose;
  96 #endif
  97
  98 #ifdef CONFIG_PCIE2
  99 static struct pci_controller pcie2_hose;
 100 #endif
 101
 102 #ifdef CONFIG_PCIE3
 103 static struct pci_controller pcie3_hose;
 104 #endif
 105
 106 int first_free_busno=0;
 107
 108 void
 109 pci_init_board(void)
 110 {
 111         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 112         uint devdisr = gur->devdisr;
 113         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 114         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 115
 116         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 117                 devdisr, io_sel, host_agent);
 118
 119         if (io_sel & 1) {
 120                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 121                         printf ("    eTSEC1 is in sgmii mode.\n");
 122                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 123                         printf ("    eTSEC3 is in sgmii mode.\n");
 124         }
 125
 126 #ifdef CONFIG_PCIE3
 127 {
 128         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 129         extern void fsl_pci_init(struct pci_controller *hose);
 130         struct pci_controller *hose = &pcie3_hose;
 131         int pcie_ep = (host_agent == 1);
 132         int pcie_configured  = io_sel >= 1;
 133
 134         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 135                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 136                         pcie_ep ? "End Point" : "Root Complex",
 137                         (uint)pci);
 138                 if (pci->pme_msg_det) {
 139                         pci->pme_msg_det = 0xffffffff;
 140                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 141                 }
 142                 printf ("\n");
 143
 144                 /* inbound */
 145                 pci_set_region(hose->regions + 0,
 146                                CONFIG_SYS_PCI_MEMORY_BUS,
 147                                CONFIG_SYS_PCI_MEMORY_PHYS,
 148                                CONFIG_SYS_PCI_MEMORY_SIZE,
 149                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 150
 151                 /* outbound memory */
 152                 pci_set_region(hose->regions + 1,
 153                                CONFIG_SYS_PCIE3_MEM_BASE,
 154                                CONFIG_SYS_PCIE3_MEM_PHYS,
 155                                CONFIG_SYS_PCIE3_MEM_SIZE,
 156                                PCI_REGION_MEM);
 157
 158                 /* outbound io */
 159                 pci_set_region(hose->regions + 2,
 160                                CONFIG_SYS_PCIE3_IO_BASE,
 161                                CONFIG_SYS_PCIE3_IO_PHYS,
 162                                CONFIG_SYS_PCIE3_IO_SIZE,
 163                                PCI_REGION_IO);
 164
 165                 hose->region_count = 3;
 166 #ifdef CONFIG_SYS_PCIE3_MEM_BASE2
 167                 /* outbound memory */
 168                 pci_set_region(hose->regions + 3,
 169                                CONFIG_SYS_PCIE3_MEM_BASE2,
 170                                CONFIG_SYS_PCIE3_MEM_PHYS2,
 171                                CONFIG_SYS_PCIE3_MEM_SIZE2,
 172                                PCI_REGION_MEM);
 173                 hose->region_count++;
 174 #endif
 175                 hose->first_busno=first_free_busno;
 176                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 177
 178                 fsl_pci_init(hose);
 179
 180                 first_free_busno=hose->last_busno+1;
 181                 printf ("    PCIE3 on bus %02x - %02x\n",
 182                         hose->first_busno,hose->last_busno);
 183
 184                 /*
 185                  * Activate ULI1575 legacy chip by performing a fake
 186                  * memory access.  Needed to make ULI RTC work.
 187                  */
 188                 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
 189         } else {
 190                 printf ("    PCIE3: disabled\n");
 191         }
 192
 193  }
 194 #else
 195         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 196 #endif
 197
 198 #ifdef CONFIG_PCIE1
 199  {
 200         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 201         extern void fsl_pci_init(struct pci_controller *hose);
 202         struct pci_controller *hose = &pcie1_hose;
 203         int pcie_ep = (host_agent == 5);
 204         int pcie_configured  = io_sel & 6;
 205
 206         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 207                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 208                         pcie_ep ? "End Point" : "Root Complex",
 209                         (uint)pci);
 210                 if (pci->pme_msg_det) {
 211                         pci->pme_msg_det = 0xffffffff;
 212                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 213                 }
 214                 printf ("\n");
 215
 216                 /* inbound */
 217                 pci_set_region(hose->regions + 0,
 218                                CONFIG_SYS_PCI_MEMORY_BUS,
 219                                CONFIG_SYS_PCI_MEMORY_PHYS,
 220                                CONFIG_SYS_PCI_MEMORY_SIZE,
 221                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 222
 223                 /* outbound memory */
 224                 pci_set_region(hose->regions + 1,
 225                                CONFIG_SYS_PCIE1_MEM_BASE,
 226                                CONFIG_SYS_PCIE1_MEM_PHYS,
 227                                CONFIG_SYS_PCIE1_MEM_SIZE,
 228                                PCI_REGION_MEM);
 229
 230                 /* outbound io */
 231                 pci_set_region(hose->regions + 2,
 232                                CONFIG_SYS_PCIE1_IO_BASE,
 233                                CONFIG_SYS_PCIE1_IO_PHYS,
 234                                CONFIG_SYS_PCIE1_IO_SIZE,
 235                                PCI_REGION_IO);
 236
 237                 hose->region_count = 3;
 238 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
 239                 /* outbound memory */
 240                 pci_set_region(hose->regions + 3,
 241                                CONFIG_SYS_PCIE1_MEM_BASE2,
 242                                CONFIG_SYS_PCIE1_MEM_PHYS2,
 243                                CONFIG_SYS_PCIE1_MEM_SIZE2,
 244                                PCI_REGION_MEM);
 245                 hose->region_count++;
 246 #endif
 247                 hose->first_busno=first_free_busno;
 248
 249                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 250
 251                 fsl_pci_init(hose);
 252
 253                 first_free_busno=hose->last_busno+1;
 254                 printf("    PCIE1 on bus %02x - %02x\n",
 255                        hose->first_busno,hose->last_busno);
 256
 257         } else {
 258                 printf ("    PCIE1: disabled\n");
 259         }
 260
 261  }
 262 #else
 263         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 264 #endif
 265
 266 #ifdef CONFIG_PCIE2
 267  {
 268         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 269         extern void fsl_pci_init(struct pci_controller *hose);
 270         struct pci_controller *hose = &pcie2_hose;
 271         int pcie_ep = (host_agent == 3);
 272         int pcie_configured  = io_sel & 4;
 273
 274         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 275                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 276                         pcie_ep ? "End Point" : "Root Complex",
 277                         (uint)pci);
 278                 if (pci->pme_msg_det) {
 279                         pci->pme_msg_det = 0xffffffff;
 280                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 281                 }
 282                 printf ("\n");
 283
 284                 /* inbound */
 285                 pci_set_region(hose->regions + 0,
 286                                CONFIG_SYS_PCI_MEMORY_BUS,
 287                                CONFIG_SYS_PCI_MEMORY_PHYS,
 288                                CONFIG_SYS_PCI_MEMORY_SIZE,
 289                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 290
 291                 /* outbound memory */
 292                 pci_set_region(hose->regions + 1,
 293                                CONFIG_SYS_PCIE2_MEM_BASE,
 294                                CONFIG_SYS_PCIE2_MEM_PHYS,
 295                                CONFIG_SYS_PCIE2_MEM_SIZE,
 296                                PCI_REGION_MEM);
 297
 298                 /* outbound io */
 299                 pci_set_region(hose->regions + 2,
 300                                CONFIG_SYS_PCIE2_IO_BASE,
 301                                CONFIG_SYS_PCIE2_IO_PHYS,
 302                                CONFIG_SYS_PCIE2_IO_SIZE,
 303                                PCI_REGION_IO);
 304
 305                 hose->region_count = 3;
 306 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
 307                 /* outbound memory */
 308                 pci_set_region(hose->regions + 3,
 309                                CONFIG_SYS_PCIE2_MEM_BASE2,
 310                                CONFIG_SYS_PCIE2_MEM_PHYS2,
 311                                CONFIG_SYS_PCIE2_MEM_SIZE2,
 312                                PCI_REGION_MEM);
 313                 hose->region_count++;
 314 #endif
 315                 hose->first_busno=first_free_busno;
 316                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 317
 318                 fsl_pci_init(hose);
 319                 first_free_busno=hose->last_busno+1;
 320                 printf ("    PCIE2 on bus %02x - %02x\n",
 321                         hose->first_busno,hose->last_busno);
 322
 323         } else {
 324                 printf ("    PCIE2: disabled\n");
 325         }
 326
 327  }
 328 #else
 329         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 330 #endif
 331
 332
 333 #ifdef CONFIG_PCI1
 334 {
 335         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 336         extern void fsl_pci_init(struct pci_controller *hose);
 337         struct pci_controller *hose = &pci1_hose;
 338
 339         uint pci_agent = (host_agent == 6);
 340         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 341         uint pci_32 = 1;
 342         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 343         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 344
 345
 346         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 347                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 348                         (pci_32) ? 32 : 64,
 349                         (pci_speed == 33333000) ? "33" :
 350                         (pci_speed == 66666000) ? "66" : "unknown",
 351                         pci_clk_sel ? "sync" : "async",
 352                         pci_agent ? "agent" : "host",
 353                         pci_arb ? "arbiter" : "external-arbiter",
 354                         (uint)pci
 355                         );
 356
 357                 /* inbound */
 358                 pci_set_region(hose->regions + 0,
 359                                CONFIG_SYS_PCI_MEMORY_BUS,
 360                                CONFIG_SYS_PCI_MEMORY_PHYS,
 361                                CONFIG_SYS_PCI_MEMORY_SIZE,
 362                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 363
 364                 /* outbound memory */
 365                 pci_set_region(hose->regions + 1,
 366                                CONFIG_SYS_PCI1_MEM_BASE,
 367                                CONFIG_SYS_PCI1_MEM_PHYS,
 368                                CONFIG_SYS_PCI1_MEM_SIZE,
 369                                PCI_REGION_MEM);
 370
 371                 /* outbound io */
 372                 pci_set_region(hose->regions + 2,
 373                                CONFIG_SYS_PCI1_IO_BASE,
 374                                CONFIG_SYS_PCI1_IO_PHYS,
 375                                CONFIG_SYS_PCI1_IO_SIZE,
 376                                PCI_REGION_IO);
 377                 hose->region_count = 3;
 378 #ifdef CONFIG_SYS_PCIE3_MEM_BASE2
 379                 /* outbound memory */
 380                 pci_set_region(hose->regions + 3,
 381                                CONFIG_SYS_PCIE3_MEM_BASE2,
 382                                CONFIG_SYS_PCIE3_MEM_PHYS2,
 383                                CONFIG_SYS_PCIE3_MEM_SIZE2,
 384                                PCI_REGION_MEM);
 385                 hose->region_count++;
 386 #endif
 387                 hose->first_busno=first_free_busno;
 388                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 389
 390                 fsl_pci_init(hose);
 391                 first_free_busno=hose->last_busno+1;
 392                 printf ("PCI on bus %02x - %02x\n",
 393                         hose->first_busno,hose->last_busno);
 394         } else {
 395                 printf ("    PCI: disabled\n");
 396         }
 397 }
 398 #else
 399         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 400 #endif
 401 }
 402
 403
 404 int last_stage_init(void)
 405 {
 406         return 0;
 407 }
 408
 409
 410 unsigned long
 411 get_board_sys_clk(ulong dummy)
 412 {
 413         u8 i, go_bit, rd_clks;
 414         ulong val = 0;
 415
 416         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 417         go_bit &= 0x01;
 418
 419         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 420         rd_clks &= 0x1C;
 421
 422         /*
 423          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 424          * should we be using the AUX register. Remember, we also set the
 425          * GO bit to boot from the alternate bank on the on-board flash
 426          */
 427
 428         if (go_bit) {
 429                 if (rd_clks == 0x1c)
 430                         i = in8(PIXIS_BASE + PIXIS_AUX);
 431                 else
 432                         i = in8(PIXIS_BASE + PIXIS_SPD);
 433         } else {
 434                 i = in8(PIXIS_BASE + PIXIS_SPD);
 435         }
 436
 437         i &= 0x07;
 438
 439         switch (i) {
 440         case 0:
 441                 val = 33333333;
 442                 break;
 443         case 1:
 444                 val = 40000000;
 445                 break;
 446         case 2:
 447                 val = 50000000;
 448                 break;
 449         case 3:
 450                 val = 66666666;
 451                 break;
 452         case 4:
 453                 val = 83000000;
 454                 break;
 455         case 5:
 456                 val = 100000000;
 457                 break;
 458         case 6:
 459                 val = 133333333;
 460                 break;
 461         case 7:
 462                 val = 166666666;
 463                 break;
 464         }
 465
 466         return val;
 467 }
 468
 469 int board_eth_init(bd_t *bis)
 470 {
 471 #ifdef CONFIG_TSEC_ENET
 472         struct tsec_info_struct tsec_info[2];
 473         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 474         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 475         int num = 0;
 476
 477 #ifdef CONFIG_TSEC1
 478         SET_STD_TSEC_INFO(tsec_info[num], 1);
 479         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 480                 tsec_info[num].flags |= TSEC_SGMII;
 481         num++;
 482 #endif
 483 #ifdef CONFIG_TSEC3
 484         SET_STD_TSEC_INFO(tsec_info[num], 3);
 485         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 486                 tsec_info[num].flags |= TSEC_SGMII;
 487         num++;
 488 #endif
 489
 490         if (!num) {
 491                 printf("No TSECs initialized\n");
 492
 493                 return 0;
 494         }
 495
 496         if (io_sel & 1)
 497                 fsl_sgmii_riser_init(tsec_info, num);
 498
 499
 500         tsec_eth_init(bis, tsec_info, num);
 501 #endif
 502         return pci_eth_init(bis);
 503 }
 504
 505 #if defined(CONFIG_OF_BOARD_SETUP)
 506
 507 void
 508 ft_board_setup(void *blob, bd_t *bd)
 509 {
 510         int node, tmp[2];
 511         const char *path;
 512
 513         ft_cpu_setup(blob, bd);
 514
 515         node = fdt_path_offset(blob, "/aliases");
 516         tmp[0] = 0;
 517         if (node >= 0) {
 518 #ifdef CONFIG_PCI1
 519                 path = fdt_getprop(blob, node, "pci0", NULL);
 520                 if (path) {
 521                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 522                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 523                 }
 524 #endif
 525 #ifdef CONFIG_PCIE2
 526                 path = fdt_getprop(blob, node, "pci1", NULL);
 527                 if (path) {
 528                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 529                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 530                 }
 531 #endif
 532 #ifdef CONFIG_PCIE1
 533                 path = fdt_getprop(blob, node, "pci2", NULL);
 534                 if (path) {
 535                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 536                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 537                 }
 538 #endif
 539 #ifdef CONFIG_PCIE3
 540                 path = fdt_getprop(blob, node, "pci3", NULL);
 541                 if (path) {
 542                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 543                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 544                 }
 545 #endif
 546         }
 547 }
 548 #endif