board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37
  38 #include "../common/pixis.h"
  39 #include "../common/sgmii_riser.h"
  40
  41 long int fixed_sdram(void);
  42
  43 int checkboard (void)
  44 {
  45         puts ("Board: MPC8572DS ");
  46 #ifdef CONFIG_PHYS_64BIT
  47         puts ("(36-bit addrmap) ");
  48 #endif
  49         printf ("Sys ID: 0x%02x, "
  50                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
  51                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  52                 in8(PIXIS_BASE + PIXIS_PVER));
  53         return 0;
  54 }
  55
  56 phys_size_t initdram(int board_type)
  57 {
  58         phys_size_t dram_size = 0;
  59
  60         puts("Initializing....");
  61
  62 #ifdef CONFIG_SPD_EEPROM
  63         dram_size = fsl_ddr_sdram();
  64 #else
  65         dram_size = fixed_sdram();
  66 #endif
  67         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  68         dram_size *= 0x100000;
  69
  70         puts("    DDR: ");
  71         return dram_size;
  72 }
  73
  74 #if !defined(CONFIG_SPD_EEPROM)
  75 /*
  76  * Fixed sdram init -- doesn't use serial presence detect.
  77  */
  78
  79 phys_size_t fixed_sdram (void)
  80 {
  81         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  82         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
  83         uint d_init;
  84
  85         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  86         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  87
  88         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  89         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  90         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  91         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  92         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  93         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  94         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  95         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  96         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  97         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  98
  99 #if defined (CONFIG_DDR_ECC)
 100         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 101         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 102         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 103 #endif
 104         asm("sync;isync");
 105
 106         udelay(500);
 107
 108         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 109
 110 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 111         d_init = 1;
 112         debug("DDR - 1st controller: memory initializing\n");
 113         /*
 114          * Poll until memory is initialized.
 115          * 512 Meg at 400 might hit this 200 times or so.
 116          */
 117         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 118                 udelay(1000);
 119         }
 120         debug("DDR: memory initialized\n\n");
 121         asm("sync; isync");
 122         udelay(500);
 123 #endif
 124
 125         return 512 * 1024 * 1024;
 126 }
 127
 128 #endif
 129
 130 #ifdef CONFIG_PCIE1
 131 static struct pci_controller pcie1_hose;
 132 #endif
 133
 134 #ifdef CONFIG_PCIE2
 135 static struct pci_controller pcie2_hose;
 136 #endif
 137
 138 #ifdef CONFIG_PCIE3
 139 static struct pci_controller pcie3_hose;
 140 #endif
 141
 142 int first_free_busno=0;
 143 #ifdef CONFIG_PCI
 144 void pci_init_board(void)
 145 {
 146         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 147         uint devdisr = gur->devdisr;
 148         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 149         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 150
 151         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 152                         devdisr, io_sel, host_agent);
 153
 154         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 155                 printf ("    eTSEC1 is in sgmii mode.\n");
 156         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 157                 printf ("    eTSEC2 is in sgmii mode.\n");
 158         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 159                 printf ("    eTSEC3 is in sgmii mode.\n");
 160         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 161                 printf ("    eTSEC4 is in sgmii mode.\n");
 162
 163
 164 #ifdef CONFIG_PCIE3
 165         {
 166                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 167                 struct pci_controller *hose = &pcie3_hose;
 168                 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 169                         (host_agent == 5) || (host_agent == 6);
 170                 int pcie_configured  = (io_sel == 0x7);
 171                 struct pci_region *r = hose->regions;
 172                 u32 temp32;
 173
 174                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 175                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 176                                         pcie_ep ? "End Point" : "Root Complex",
 177                                         (uint)pci);
 178                         if (pci->pme_msg_det) {
 179                                 pci->pme_msg_det = 0xffffffff;
 180                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 181                         }
 182                         printf ("\n");
 183
 184                         /* inbound */
 185                         r += fsl_pci_setup_inbound_windows(r);
 186
 187                         /* outbound memory */
 188                         pci_set_region(r++,
 189                                         CONFIG_SYS_PCIE3_MEM_BUS,
 190                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 191                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 192                                         PCI_REGION_MEM);
 193
 194                         /* outbound io */
 195                         pci_set_region(r++,
 196                                         CONFIG_SYS_PCIE3_IO_BUS,
 197                                         CONFIG_SYS_PCIE3_IO_PHYS,
 198                                         CONFIG_SYS_PCIE3_IO_SIZE,
 199                                         PCI_REGION_IO);
 200
 201                         hose->region_count = r - hose->regions;
 202                         hose->first_busno=first_free_busno;
 203                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 204
 205                         fsl_pci_init(hose);
 206
 207                         first_free_busno=hose->last_busno+1;
 208                         printf ("    PCIE3 on bus %02x - %02x\n",
 209                                         hose->first_busno,hose->last_busno);
 210
 211                         /*
 212                          * Activate ULI1575 legacy chip by performing a fake
 213                          * memory access.  Needed to make ULI RTC work.
 214                          * Device 1d has the first on-board memory BAR.
 215                          */
 216
 217                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 218                                         PCI_BASE_ADDRESS_1, &temp32);
 219                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 220                                 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 221                                                                 temp32, 4, 0);
 222                                 debug(" uli1572 read to %p\n", p);
 223                                 in_be32(p);
 224                         }
 225                 } else {
 226                         printf ("    PCIE3: disabled\n");
 227                 }
 228
 229         }
 230 #else
 231         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 232 #endif
 233
 234 #ifdef CONFIG_PCIE2
 235         {
 236                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 237                 struct pci_controller *hose = &pcie2_hose;
 238                 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 239                         (host_agent == 6) || (host_agent == 0);
 240                 int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
 241                 struct pci_region *r = hose->regions;
 242
 243                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 244                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 245                                         pcie_ep ? "End Point" : "Root Complex",
 246                                         (uint)pci);
 247                         if (pci->pme_msg_det) {
 248                                 pci->pme_msg_det = 0xffffffff;
 249                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 250                         }
 251                         printf ("\n");
 252
 253                         /* inbound */
 254                         r += fsl_pci_setup_inbound_windows(r);
 255
 256                         /* outbound memory */
 257                         pci_set_region(r++,
 258                                         CONFIG_SYS_PCIE2_MEM_BUS,
 259                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 260                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 261                                         PCI_REGION_MEM);
 262
 263                         /* outbound io */
 264                         pci_set_region(r++,
 265                                         CONFIG_SYS_PCIE2_IO_BUS,
 266                                         CONFIG_SYS_PCIE2_IO_PHYS,
 267                                         CONFIG_SYS_PCIE2_IO_SIZE,
 268                                         PCI_REGION_IO);
 269
 270                         hose->region_count = r - hose->regions;
 271                         hose->first_busno=first_free_busno;
 272                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 273
 274                         fsl_pci_init(hose);
 275                         first_free_busno=hose->last_busno+1;
 276                         printf ("    PCIE2 on bus %02x - %02x\n",
 277                                         hose->first_busno,hose->last_busno);
 278
 279                 } else {
 280                         printf ("    PCIE2: disabled\n");
 281                 }
 282
 283         }
 284 #else
 285         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 286 #endif
 287 #ifdef CONFIG_PCIE1
 288         {
 289                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 290                 struct pci_controller *hose = &pcie1_hose;
 291                 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 292                         (host_agent == 5);
 293                 int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
 294                                         (io_sel == 0x7) || (io_sel == 0xb) ||
 295                                         (io_sel == 0xc) || (io_sel == 0xf);
 296                 struct pci_region *r = hose->regions;
 297
 298                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 299                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 300                                         pcie_ep ? "End Point" : "Root Complex",
 301                                         (uint)pci);
 302                         if (pci->pme_msg_det) {
 303                                 pci->pme_msg_det = 0xffffffff;
 304                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 305                         }
 306                         printf ("\n");
 307
 308                         /* inbound */
 309                         r += fsl_pci_setup_inbound_windows(r);
 310
 311                         /* outbound memory */
 312                         pci_set_region(r++,
 313                                         CONFIG_SYS_PCIE1_MEM_BUS,
 314                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 315                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 316                                         PCI_REGION_MEM);
 317
 318                         /* outbound io */
 319                         pci_set_region(r++,
 320                                         CONFIG_SYS_PCIE1_IO_BUS,
 321                                         CONFIG_SYS_PCIE1_IO_PHYS,
 322                                         CONFIG_SYS_PCIE1_IO_SIZE,
 323                                         PCI_REGION_IO);
 324
 325                         hose->region_count = r - hose->regions;
 326                         hose->first_busno=first_free_busno;
 327
 328                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 329
 330                         fsl_pci_init(hose);
 331
 332                         first_free_busno=hose->last_busno+1;
 333                         printf("    PCIE1 on bus %02x - %02x\n",
 334                                         hose->first_busno,hose->last_busno);
 335
 336                 } else {
 337                         printf ("    PCIE1: disabled\n");
 338                 }
 339
 340         }
 341 #else
 342         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 343 #endif
 344 }
 345 #endif
 346
 347 int board_early_init_r(void)
 348 {
 349         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 350         const u8 flash_esel = 2;
 351
 352         /*
 353          * Remap Boot flash + PROMJET region to caching-inhibited
 354          * so that flash can be erased properly.
 355          */
 356
 357         /* Flush d-cache and invalidate i-cache of any FLASH data */
 358         flush_dcache();
 359         invalidate_icache();
 360
 361         /* invalidate existing TLB entry for flash + promjet */
 362         disable_tlb(flash_esel);
 363
 364         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 365                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 366                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 367
 368         return 0;
 369 }
 370
 371 #ifdef CONFIG_GET_CLK_FROM_ICS307
 372 /* decode S[0-2] to Output Divider (OD) */
 373 static unsigned char ics307_S_to_OD[] = {
 374         10, 2, 8, 4, 5, 7, 3, 6
 375 };
 376
 377 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 378  * the control bytes being programmed into it. */
 379 /* XXX: This function should probably go into a common library */
 380 static unsigned long
 381 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 382 {
 383         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 384         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 385         unsigned long RDW = cw2 & 0x7F;
 386         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 387         unsigned long freq;
 388
 389         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 390
 391         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 392          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 393          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 394          *
 395          * R6:R0 = Reference Divider Word (RDW)
 396          * V8:V0 = VCO Divider Word (VDW)
 397          * S2:S0 = Output Divider Select (OD)
 398          * F1:F0 = Function of CLK2 Output
 399          * TTL = duty cycle
 400          * C1:C0 = internal load capacitance for cyrstal
 401          */
 402
 403         /* Adding 1 to get a "nicely" rounded number, but this needs
 404          * more tweaking to get a "properly" rounded number. */
 405
 406         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 407
 408         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 409                         freq);
 410         return freq;
 411 }
 412
 413 unsigned long get_board_sys_clk(ulong dummy)
 414 {
 415         return ics307_clk_freq (
 416                         in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 417                         in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 418                         in8(PIXIS_BASE + PIXIS_VSYSCLK2)
 419                         );
 420 }
 421
 422 unsigned long get_board_ddr_clk(ulong dummy)
 423 {
 424         return ics307_clk_freq (
 425                         in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 426                         in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 427                         in8(PIXIS_BASE + PIXIS_VDDRCLK2)
 428                         );
 429 }
 430 #else
 431 unsigned long get_board_sys_clk(ulong dummy)
 432 {
 433         u8 i;
 434         ulong val = 0;
 435
 436         i = in8(PIXIS_BASE + PIXIS_SPD);
 437         i &= 0x07;
 438
 439         switch (i) {
 440                 case 0:
 441                         val = 33333333;
 442                         break;
 443                 case 1:
 444                         val = 40000000;
 445                         break;
 446                 case 2:
 447                         val = 50000000;
 448                         break;
 449                 case 3:
 450                         val = 66666666;
 451                         break;
 452                 case 4:
 453                         val = 83333333;
 454                         break;
 455                 case 5:
 456                         val = 100000000;
 457                         break;
 458                 case 6:
 459                         val = 133333333;
 460                         break;
 461                 case 7:
 462                         val = 166666666;
 463                         break;
 464         }
 465
 466         return val;
 467 }
 468
 469 unsigned long get_board_ddr_clk(ulong dummy)
 470 {
 471         u8 i;
 472         ulong val = 0;
 473
 474         i = in8(PIXIS_BASE + PIXIS_SPD);
 475         i &= 0x38;
 476         i >>= 3;
 477
 478         switch (i) {
 479                 case 0:
 480                         val = 33333333;
 481                         break;
 482                 case 1:
 483                         val = 40000000;
 484                         break;
 485                 case 2:
 486                         val = 50000000;
 487                         break;
 488                 case 3:
 489                         val = 66666666;
 490                         break;
 491                 case 4:
 492                         val = 83333333;
 493                         break;
 494                 case 5:
 495                         val = 100000000;
 496                         break;
 497                 case 6:
 498                         val = 133333333;
 499                         break;
 500                 case 7:
 501                         val = 166666666;
 502                         break;
 503         }
 504         return val;
 505 }
 506 #endif
 507
 508 #ifdef CONFIG_TSEC_ENET
 509 int board_eth_init(bd_t *bis)
 510 {
 511         struct tsec_info_struct tsec_info[4];
 512         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 513         int num = 0;
 514
 515 #ifdef CONFIG_TSEC1
 516         SET_STD_TSEC_INFO(tsec_info[num], 1);
 517         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 518                 tsec_info[num].flags |= TSEC_SGMII;
 519         num++;
 520 #endif
 521 #ifdef CONFIG_TSEC2
 522         SET_STD_TSEC_INFO(tsec_info[num], 2);
 523         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 524                 tsec_info[num].flags |= TSEC_SGMII;
 525         num++;
 526 #endif
 527 #ifdef CONFIG_TSEC3
 528         SET_STD_TSEC_INFO(tsec_info[num], 3);
 529         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 530                 tsec_info[num].flags |= TSEC_SGMII;
 531         num++;
 532 #endif
 533 #ifdef CONFIG_TSEC4
 534         SET_STD_TSEC_INFO(tsec_info[num], 4);
 535         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 536                 tsec_info[num].flags |= TSEC_SGMII;
 537         num++;
 538 #endif
 539
 540         if (!num) {
 541                 printf("No TSECs initialized\n");
 542
 543                 return 0;
 544         }
 545
 546 #ifdef CONFIG_FSL_SGMII_RISER
 547         fsl_sgmii_riser_init(tsec_info, num);
 548 #endif
 549
 550         tsec_eth_init(bis, tsec_info, num);
 551
 552         return 0;
 553 }
 554 #endif
 555
 556 #if defined(CONFIG_OF_BOARD_SETUP)
 557 void ft_board_setup(void *blob, bd_t *bd)
 558 {
 559         phys_addr_t base;
 560         phys_size_t size;
 561
 562         ft_cpu_setup(blob, bd);
 563
 564         base = getenv_bootm_low();
 565         size = getenv_bootm_size();
 566
 567         fdt_fixup_memory(blob, (u64)base, (u64)size);
 568
 569 #ifdef CONFIG_PCIE3
 570         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 571 #endif
 572 #ifdef CONFIG_PCIE2
 573         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 574 #endif
 575 #ifdef CONFIG_PCIE1
 576         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 577 #endif
 578 #ifdef CONFIG_FSL_SGMII_RISER
 579         fsl_sgmii_riser_fdt_fixup(blob);
 580 #endif
 581 }
 582 #endif
 583
 584 #ifdef CONFIG_MP
 585 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 586
 587 void board_lmb_reserve(struct lmb *lmb)
 588 {
 589         cpu_mp_lmb_reserve(lmb);
 590 }
 591 #endif