board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/immap_fsl_pci.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <asm/io.h>
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32 #include <netdev.h>
  33
  34 #include "../common/pixis.h"
  35
  36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  37 extern void ddr_enable_ecc(unsigned int dram_size);
  38 #endif
  39
  40 long int fixed_sdram(void);
  41
  42 int board_early_init_f(void)
  43 {
  44         return 0;
  45 }
  46
  47 int checkboard(void)
  48 {
  49         printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
  50                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  51                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  52                 in8(PIXIS_BASE + PIXIS_PVER));
  53         return 0;
  54 }
  55
  56
  57 phys_size_t
  58 initdram(int board_type)
  59 {
  60         long dram_size = 0;
  61
  62 #if defined(CONFIG_SPD_EEPROM)
  63         dram_size = fsl_ddr_sdram();
  64 #else
  65         dram_size = fixed_sdram();
  66 #endif
  67
  68 #if defined(CONFIG_SYS_RAMBOOT)
  69         puts("    DDR: ");
  70         return dram_size;
  71 #endif
  72
  73 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  74         /*
  75          * Initialize and enable DDR ECC.
  76          */
  77         ddr_enable_ecc(dram_size);
  78 #endif
  79
  80         puts("    DDR: ");
  81         return dram_size;
  82 }
  83
  84
  85 #if !defined(CONFIG_SPD_EEPROM)
  86 /*
  87  * Fixed sdram init -- doesn't use serial presence detect.
  88  */
  89 long int
  90 fixed_sdram(void)
  91 {
  92 #if !defined(CONFIG_SYS_RAMBOOT)
  93         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  94         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  95
  96         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  97         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  98         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  99         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 100         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 101         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 102         ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
 103         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 104         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 105         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 106         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 107         ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
 108         ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
 109
 110 #if defined (CONFIG_DDR_ECC)
 111         ddr->err_disable = 0x0000008D;
 112         ddr->err_sbe = 0x00ff0000;
 113 #endif
 114         asm("sync;isync");
 115
 116         udelay(500);
 117
 118 #if defined (CONFIG_DDR_ECC)
 119         /* Enable ECC checking */
 120         ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 121 #else
 122         ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
 123         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 124 #endif
 125         asm("sync; isync");
 126
 127         udelay(500);
 128 #endif
 129         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 130 }
 131 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 132
 133
 134 #if defined(CONFIG_PCI)
 135 /*
 136  * Initialize PCI Devices, report devices found.
 137  */
 138
 139 #ifndef CONFIG_PCI_PNP
 140 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 141         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 142          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 143          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 144                                      PCI_ENET0_MEMADDR,
 145                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 146         {}
 147 };
 148 #endif
 149
 150
 151 static struct pci_controller pci1_hose = {
 152 #ifndef CONFIG_PCI_PNP
 153         config_table:pci_mpc86xxcts_config_table
 154 #endif
 155 };
 156 #endif /* CONFIG_PCI */
 157
 158 #ifdef CONFIG_PCI2
 159 static struct pci_controller pci2_hose;
 160 #endif  /* CONFIG_PCI2 */
 161
 162 int first_free_busno = 0;
 163
 164
 165 void pci_init_board(void)
 166 {
 167         volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 168         volatile ccsr_gur_t *gur = &immap->im_gur;
 169         uint devdisr = gur->devdisr;
 170         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 171                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 172
 173 #ifdef CONFIG_PCI1
 174 {
 175         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 176         extern void fsl_pci_init(struct pci_controller *hose);
 177         struct pci_controller *hose = &pci1_hose;
 178 #ifdef DEBUG
 179         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 180                 >> MPC8641_PORBMSR_HA_SHIFT;
 181         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 182 #endif
 183         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 184              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 185             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 186                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 187                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 188                 if (pci->pme_msg_det) {
 189                         pci->pme_msg_det = 0xffffffff;
 190                         debug(" with errors.  Clearing.  Now 0x%08x",
 191                               pci->pme_msg_det);
 192                 }
 193                 debug("\n");
 194
 195                 /* inbound */
 196                 pci_set_region(hose->regions + 0,
 197                                CONFIG_SYS_PCI_MEMORY_BUS,
 198                                CONFIG_SYS_PCI_MEMORY_PHYS,
 199                                CONFIG_SYS_PCI_MEMORY_SIZE,
 200                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 201
 202                 /* outbound memory */
 203                 pci_set_region(hose->regions + 1,
 204                                CONFIG_SYS_PCI1_MEM_BASE,
 205                                CONFIG_SYS_PCI1_MEM_PHYS,
 206                                CONFIG_SYS_PCI1_MEM_SIZE,
 207                                PCI_REGION_MEM);
 208
 209                 /* outbound io */
 210                 pci_set_region(hose->regions + 2,
 211                                CONFIG_SYS_PCI1_IO_BASE,
 212                                CONFIG_SYS_PCI1_IO_PHYS,
 213                                CONFIG_SYS_PCI1_IO_SIZE,
 214                                PCI_REGION_IO);
 215
 216                 hose->region_count = 3;
 217
 218                 hose->first_busno=first_free_busno;
 219                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 220
 221                 fsl_pci_init(hose);
 222
 223                 first_free_busno=hose->last_busno+1;
 224                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 225                         hose->first_busno,hose->last_busno);
 226
 227                 /*
 228                  * Activate ULI1575 legacy chip by performing a fake
 229                  * memory access.  Needed to make ULI RTC work.
 230                  */
 231                 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
 232                                        + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
 233
 234         } else {
 235                 puts("PCI-EXPRESS 1: Disabled\n");
 236         }
 237 }
 238 #else
 239         puts("PCI-EXPRESS1: Disabled\n");
 240 #endif /* CONFIG_PCI1 */
 241
 242 #ifdef CONFIG_PCI2
 243 {
 244         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 245         extern void fsl_pci_init(struct pci_controller *hose);
 246         struct pci_controller *hose = &pci2_hose;
 247
 248
 249         /* inbound */
 250         pci_set_region(hose->regions + 0,
 251                        CONFIG_SYS_PCI_MEMORY_BUS,
 252                        CONFIG_SYS_PCI_MEMORY_PHYS,
 253                        CONFIG_SYS_PCI_MEMORY_SIZE,
 254                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 255
 256         /* outbound memory */
 257         pci_set_region(hose->regions + 1,
 258                        CONFIG_SYS_PCI2_MEM_BASE,
 259                        CONFIG_SYS_PCI2_MEM_PHYS,
 260                        CONFIG_SYS_PCI2_MEM_SIZE,
 261                        PCI_REGION_MEM);
 262
 263         /* outbound io */
 264         pci_set_region(hose->regions + 2,
 265                        CONFIG_SYS_PCI2_IO_BASE,
 266                        CONFIG_SYS_PCI2_IO_PHYS,
 267                        CONFIG_SYS_PCI2_IO_SIZE,
 268                        PCI_REGION_IO);
 269
 270         hose->region_count = 3;
 271
 272         hose->first_busno=first_free_busno;
 273         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 274
 275         fsl_pci_init(hose);
 276
 277         first_free_busno=hose->last_busno+1;
 278         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 279                 hose->first_busno,hose->last_busno);
 280 }
 281 #else
 282         puts("PCI-EXPRESS 2: Disabled\n");
 283 #endif /* CONFIG_PCI2 */
 284
 285 }
 286
 287
 288 #if defined(CONFIG_OF_BOARD_SETUP)
 289
 290 void
 291 ft_board_setup(void *blob, bd_t *bd)
 292 {
 293         int node, tmp[2];
 294         const char *path;
 295
 296         ft_cpu_setup(blob, bd);
 297
 298         node = fdt_path_offset(blob, "/aliases");
 299         tmp[0] = 0;
 300         if (node >= 0) {
 301 #ifdef CONFIG_PCI1
 302                 path = fdt_getprop(blob, node, "pci0", NULL);
 303                 if (path) {
 304                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 305                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 306                 }
 307 #endif
 308 #ifdef CONFIG_PCI2
 309                 path = fdt_getprop(blob, node, "pci1", NULL);
 310                 if (path) {
 311                         tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
 312                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 313                 }
 314 #endif
 315         }
 316 }
 317 #endif
 318
 319
 320 /*
 321  * get_board_sys_clk
 322  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 323  */
 324
 325 unsigned long
 326 get_board_sys_clk(ulong dummy)
 327 {
 328         u8 i, go_bit, rd_clks;
 329         ulong val = 0;
 330
 331         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 332         go_bit &= 0x01;
 333
 334         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 335         rd_clks &= 0x1C;
 336
 337         /*
 338          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 339          * should we be using the AUX register. Remember, we also set the
 340          * GO bit to boot from the alternate bank on the on-board flash
 341          */
 342
 343         if (go_bit) {
 344                 if (rd_clks == 0x1c)
 345                         i = in8(PIXIS_BASE + PIXIS_AUX);
 346                 else
 347                         i = in8(PIXIS_BASE + PIXIS_SPD);
 348         } else {
 349                 i = in8(PIXIS_BASE + PIXIS_SPD);
 350         }
 351
 352         i &= 0x07;
 353
 354         switch (i) {
 355         case 0:
 356                 val = 33000000;
 357                 break;
 358         case 1:
 359                 val = 40000000;
 360                 break;
 361         case 2:
 362                 val = 50000000;
 363                 break;
 364         case 3:
 365                 val = 66000000;
 366                 break;
 367         case 4:
 368                 val = 83000000;
 369                 break;
 370         case 5:
 371                 val = 100000000;
 372                 break;
 373         case 6:
 374                 val = 134000000;
 375                 break;
 376         case 7:
 377                 val = 166000000;
 378                 break;
 379         }
 380
 381         return val;
 382 }
 383
 384 int board_eth_init(bd_t *bis)
 385 {
 386         /* Initialize TSECs */
 387         cpu_eth_init(bis);
 388         return pci_eth_init(bis);
 389 }