2 * Copyright (c) 2009 Freescale Semiconductor
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define DCDGEN(i,type, addr, data) \
39 app_code_jump_v: .long reset
40 app_code_barker: .long 0xB1
42 hwcfg_ptr_ptr: .long hwcfg_ptr
43 super_root_key: .long 0
44 hwcfg_ptr: .long dcd_data
45 app_dest_ptr: .long TEXT_BASE
46 dcd_data: .long 0xB17219E9
48 #ifdef MXC_MEMORY_MDDR
54 /* WEIM config-CS5 init -- CPLD */
55 DCDGEN( 1, 4, 0xB8002050, 0x0000D843) /* CS5_CSCRU */
56 DCDGEN( 2, 4, 0xB8002054, 0x22252521) /* CS5_CSCRL */
57 DCDGEN( 3, 4, 0xB8002058, 0x22220A00) /* CS5_CSCRA */
58 #ifdef MXC_MEMORY_MDDR
60 DCDGEN( 4, 4, 0xB8001010, 0x00000004) /* enable mDDR */
61 DCDGEN( 5, 4, 0xB8001000, 0x92100000) /* precharge command */
62 DCDGEN( 6, 1, 0x80000400, 0x12344321) /* precharge all dummy write */
63 DCDGEN( 7, 4, 0xB8001000, 0xA2100000) /* auto-refresh command */
64 DCDGEN( 8, 4, 0x80000000, 0x12344321) /* dummy write for refresh */
65 DCDGEN( 9, 4, 0x80000000, 0x12344321) /* dummy write for refresh */
66 DCDGEN(10, 4, 0xB8001000, 0xB2100000) /* Load Mode Reg command - cas=3 bl=8 */
67 DCDGEN(11, 1, 0x80000033, 0xda) /* dummy write -- address has the mode bits */
68 DCDGEN(12, 1, 0x81000000, 0xff) /* dummy write -- address has the mode bits */
69 DCDGEN(13, 4, 0xB8001000, 0x82216880)
70 DCDGEN(14, 4, 0xB8001004, 0x00295729)
73 DCDGEN( 4, 4, 0xB8001004, 0x0076E83A) /* initial value for ESDCFG0 */
74 DCDGEN( 5, 4, 0xB8001010, 0x00000204) /* ESD_MISC */
75 DCDGEN( 6, 4, 0xB8001000, 0x92210000) /* CS0 precharge command */
76 DCDGEN( 7, 4, 0x80000f00, 0x12344321) /* precharge all dummy write */
77 DCDGEN( 8, 4, 0xB8001000, 0xB2210000) /* Load Mode Register command */
78 DCDGEN( 9, 1, 0x82000000, 0xda) /* dummy write Load EMR2 */
79 DCDGEN(10, 1, 0x83000000, 0xda) /* dummy write Load EMR3 */
80 DCDGEN(11, 1, 0x81000400, 0xda) /* dummy write Load EMR1; enable DLL */
81 DCDGEN(12, 1, 0x80000333, 0xda) /* dummy write Load MR; reset DLL */
83 DCDGEN(13, 4, 0xB8001000, 0x92210000) /* CS0 precharge command */
84 DCDGEN(14, 1, 0x80000400, 0x12345678) /* precharge all dummy write */
86 DCDGEN(15, 4, 0xB8001000, 0xA2210000) /* select manual refresh mode */
87 DCDGEN(16, 4, 0x80000000, 0x87654321) /* manual refresh */
88 DCDGEN(17, 4, 0x80000000, 0x87654321) /* manual refresh twice */
90 DCDGEN(18, 4, 0xB8001000, 0xB2210000) /* Load Mode Register command */
91 DCDGEN(19, 1, 0x80000233, 0xda) /* Load MR; CL=3, BL=8, end DLL reset */
92 DCDGEN(20, 1, 0x81000780, 0xda) /* Load EMR1; OCD default */
93 DCDGEN(21, 1, 0x81000400, 0xda) /* Load EMR1; OCD exit */
94 DCDGEN(22, 4, 0xB8001000, 0x82216080) /* normal mode */
95 DCDGEN(23, 4, 0x43FAC454, 0x00001000) /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */
98 DCDGEN(99, 4, 0x53F80008, 0x20034000) /* CLKCTL ARM=400 AHB=133 */
99 card_cfg: .long UBOOT_IMAGE_SIZE